arch/arm/mach-at91/at91sam9g45_reset.S

   1 /*
   2  * reset AT91SAM9G45 as per errata
   3  *
   4  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
   5  *
   6  * unless the SDRAM is cleanly shutdown before we hit the
   7  * reset register it can be left driving the data bus and
   8  * killing the chance of a subsequent boot from NAND
   9  *
  10  * GPLv2 Only
  11  */
  12
  13 #include <linux/linkage.h>
  14 #include <mach/hardware.h>
  15 #include <mach/at91_ramc.h>
  16 #include "at91_rstc.h"
  17                         .arm
  18
  19 /*
  20  * at91_ramc_base is an array void*
  21  * init at NULL if only one DDR controler is present in or DT
  22  */
  23                         .globl  at91sam9g45_restart
  24
  25 at91sam9g45_restart:
  26                         ldr     r5, =at91_ramc_base             @ preload constants
  27                         ldr     r0, [r5]
  28                         ldr     r5, [r5, #4]                    @ ddr1
  29                         cmp     r5, #0
  30                         ldr     r4, =at91_rstc_base
  31                         ldr     r1, [r4]
  32
  33                         mov     r2, #1
  34                         mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
  35                         ldr     r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
  36
  37                         .balign 32                              @ align to cache line
  38
  39                         strne   r2, [r5, #AT91_DDRSDRC_RTR]     @ disable DDR1 access
  40                         strne   r3, [r5, #AT91_DDRSDRC_LPR]     @ power down DDR1
  41                         str     r2, [r0, #AT91_DDRSDRC_RTR]     @ disable DDR0 access
  42                         str     r3, [r0, #AT91_DDRSDRC_LPR]     @ power down DDR0
  43                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
  44
  45                         b       .