2 * Chip-specific setup code for the SAMA5D3 family
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * Licensed under GPLv2 or later.
10 #include <linux/module.h>
11 #include <linux/dma-mapping.h>
14 #include <asm/mach/arch.h>
15 #include <asm/mach/map.h>
16 #include <mach/sama5d3.h>
17 #include <mach/at91_pmc.h>
25 /* --------------------------------------------------------------------
27 * -------------------------------------------------------------------- */
30 * The peripheral clocks.
33 static struct clk pioA_clk
= {
35 .pid
= SAMA5D3_ID_PIOA
,
36 .type
= CLK_TYPE_PERIPHERAL
,
38 static struct clk pioB_clk
= {
40 .pid
= SAMA5D3_ID_PIOB
,
41 .type
= CLK_TYPE_PERIPHERAL
,
43 static struct clk pioC_clk
= {
45 .pid
= SAMA5D3_ID_PIOC
,
46 .type
= CLK_TYPE_PERIPHERAL
,
48 static struct clk pioD_clk
= {
50 .pid
= SAMA5D3_ID_PIOD
,
51 .type
= CLK_TYPE_PERIPHERAL
,
53 static struct clk pioE_clk
= {
55 .pid
= SAMA5D3_ID_PIOE
,
56 .type
= CLK_TYPE_PERIPHERAL
,
58 static struct clk usart0_clk
= {
60 .pid
= SAMA5D3_ID_USART0
,
61 .type
= CLK_TYPE_PERIPHERAL
,
62 .div
= AT91_PMC_PCR_DIV2
,
64 static struct clk usart1_clk
= {
66 .pid
= SAMA5D3_ID_USART1
,
67 .type
= CLK_TYPE_PERIPHERAL
,
68 .div
= AT91_PMC_PCR_DIV2
,
70 static struct clk usart2_clk
= {
72 .pid
= SAMA5D3_ID_USART2
,
73 .type
= CLK_TYPE_PERIPHERAL
,
74 .div
= AT91_PMC_PCR_DIV2
,
76 static struct clk usart3_clk
= {
78 .pid
= SAMA5D3_ID_USART3
,
79 .type
= CLK_TYPE_PERIPHERAL
,
80 .div
= AT91_PMC_PCR_DIV2
,
82 static struct clk uart0_clk
= {
84 .pid
= SAMA5D3_ID_UART0
,
85 .type
= CLK_TYPE_PERIPHERAL
,
86 .div
= AT91_PMC_PCR_DIV2
,
88 static struct clk uart1_clk
= {
90 .pid
= SAMA5D3_ID_UART1
,
91 .type
= CLK_TYPE_PERIPHERAL
,
92 .div
= AT91_PMC_PCR_DIV2
,
94 static struct clk twi0_clk
= {
96 .pid
= SAMA5D3_ID_TWI0
,
97 .type
= CLK_TYPE_PERIPHERAL
,
98 .div
= AT91_PMC_PCR_DIV8
,
100 static struct clk twi1_clk
= {
102 .pid
= SAMA5D3_ID_TWI1
,
103 .type
= CLK_TYPE_PERIPHERAL
,
104 .div
= AT91_PMC_PCR_DIV8
,
106 static struct clk twi2_clk
= {
108 .pid
= SAMA5D3_ID_TWI2
,
109 .type
= CLK_TYPE_PERIPHERAL
,
110 .div
= AT91_PMC_PCR_DIV8
,
112 static struct clk mmc0_clk
= {
114 .pid
= SAMA5D3_ID_HSMCI0
,
115 .type
= CLK_TYPE_PERIPHERAL
,
117 static struct clk mmc1_clk
= {
119 .pid
= SAMA5D3_ID_HSMCI1
,
120 .type
= CLK_TYPE_PERIPHERAL
,
122 static struct clk mmc2_clk
= {
124 .pid
= SAMA5D3_ID_HSMCI2
,
125 .type
= CLK_TYPE_PERIPHERAL
,
127 static struct clk spi0_clk
= {
129 .pid
= SAMA5D3_ID_SPI0
,
130 .type
= CLK_TYPE_PERIPHERAL
,
132 static struct clk spi1_clk
= {
134 .pid
= SAMA5D3_ID_SPI1
,
135 .type
= CLK_TYPE_PERIPHERAL
,
137 static struct clk tcb0_clk
= {
139 .pid
= SAMA5D3_ID_TC0
,
140 .type
= CLK_TYPE_PERIPHERAL
,
141 .div
= AT91_PMC_PCR_DIV2
,
143 static struct clk tcb1_clk
= {
145 .pid
= SAMA5D3_ID_TC1
,
146 .type
= CLK_TYPE_PERIPHERAL
,
147 .div
= AT91_PMC_PCR_DIV2
,
149 static struct clk adc_clk
= {
151 .pid
= SAMA5D3_ID_ADC
,
152 .type
= CLK_TYPE_PERIPHERAL
,
153 .div
= AT91_PMC_PCR_DIV2
,
155 static struct clk adc_op_clk
= {
156 .name
= "adc_op_clk",
157 .type
= CLK_TYPE_PERIPHERAL
,
160 static struct clk dma0_clk
= {
162 .pid
= SAMA5D3_ID_DMA0
,
163 .type
= CLK_TYPE_PERIPHERAL
,
165 static struct clk dma1_clk
= {
167 .pid
= SAMA5D3_ID_DMA1
,
168 .type
= CLK_TYPE_PERIPHERAL
,
170 static struct clk uhphs_clk
= {
172 .pid
= SAMA5D3_ID_UHPHS
,
173 .type
= CLK_TYPE_PERIPHERAL
,
175 static struct clk udphs_clk
= {
177 .pid
= SAMA5D3_ID_UDPHS
,
178 .type
= CLK_TYPE_PERIPHERAL
,
180 /* gmac only for sama5d33, sama5d34, sama5d35 */
181 static struct clk macb0_clk
= {
183 .pid
= SAMA5D3_ID_GMAC
,
184 .type
= CLK_TYPE_PERIPHERAL
,
186 /* emac only for sama5d31, sama5d35 */
187 static struct clk macb1_clk
= {
189 .pid
= SAMA5D3_ID_EMAC
,
190 .type
= CLK_TYPE_PERIPHERAL
,
192 /* lcd only for sama5d31, sama5d33, sama5d34 */
193 static struct clk lcdc_clk
= {
195 .pid
= SAMA5D3_ID_LCDC
,
196 .type
= CLK_TYPE_PERIPHERAL
,
198 /* isi only for sama5d33, sama5d35 */
199 static struct clk isi_clk
= {
201 .pid
= SAMA5D3_ID_ISI
,
202 .type
= CLK_TYPE_PERIPHERAL
,
204 static struct clk can0_clk
= {
206 .pid
= SAMA5D3_ID_CAN0
,
207 .type
= CLK_TYPE_PERIPHERAL
,
208 .div
= AT91_PMC_PCR_DIV2
,
210 static struct clk can1_clk
= {
212 .pid
= SAMA5D3_ID_CAN1
,
213 .type
= CLK_TYPE_PERIPHERAL
,
214 .div
= AT91_PMC_PCR_DIV2
,
216 static struct clk ssc0_clk
= {
218 .pid
= SAMA5D3_ID_SSC0
,
219 .type
= CLK_TYPE_PERIPHERAL
,
220 .div
= AT91_PMC_PCR_DIV2
,
222 static struct clk ssc1_clk
= {
224 .pid
= SAMA5D3_ID_SSC1
,
225 .type
= CLK_TYPE_PERIPHERAL
,
226 .div
= AT91_PMC_PCR_DIV2
,
228 static struct clk sha_clk
= {
230 .pid
= SAMA5D3_ID_SHA
,
231 .type
= CLK_TYPE_PERIPHERAL
,
232 .div
= AT91_PMC_PCR_DIV8
,
234 static struct clk aes_clk
= {
236 .pid
= SAMA5D3_ID_AES
,
237 .type
= CLK_TYPE_PERIPHERAL
,
239 static struct clk tdes_clk
= {
241 .pid
= SAMA5D3_ID_TDES
,
242 .type
= CLK_TYPE_PERIPHERAL
,
245 static struct clk
*periph_clocks
[] __initdata
= {
286 static struct clk pck0
= {
288 .pmc_mask
= AT91_PMC_PCK0
,
289 .type
= CLK_TYPE_PROGRAMMABLE
,
293 static struct clk pck1
= {
295 .pmc_mask
= AT91_PMC_PCK1
,
296 .type
= CLK_TYPE_PROGRAMMABLE
,
300 static struct clk pck2
= {
302 .pmc_mask
= AT91_PMC_PCK2
,
303 .type
= CLK_TYPE_PROGRAMMABLE
,
307 static struct clk_lookup periph_clocks_lookups
[] = {
308 /* lookup table for DT entries */
309 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck
),
310 CLKDEV_CON_DEV_ID(NULL
, "fffff200.gpio", &pioA_clk
),
311 CLKDEV_CON_DEV_ID(NULL
, "fffff400.gpio", &pioB_clk
),
312 CLKDEV_CON_DEV_ID(NULL
, "fffff600.gpio", &pioC_clk
),
313 CLKDEV_CON_DEV_ID(NULL
, "fffff800.gpio", &pioD_clk
),
314 CLKDEV_CON_DEV_ID(NULL
, "fffffa00.gpio", &pioE_clk
),
315 CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk
),
316 CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk
),
317 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk
),
318 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk
),
319 CLKDEV_CON_DEV_ID(NULL
, "f0014000.i2c", &twi0_clk
),
320 CLKDEV_CON_DEV_ID(NULL
, "f0018000.i2c", &twi1_clk
),
321 CLKDEV_CON_DEV_ID(NULL
, "f801c000.i2c", &twi2_clk
),
322 CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk
),
323 CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk
),
324 CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk
),
325 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk
),
326 CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk
),
327 CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk
),
328 CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk
),
329 CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk
),
330 CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk
),
331 CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk
),
332 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk
),
333 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk
),
334 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk
),
335 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk
),
336 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk
),
337 CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk
),
338 CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk
),
339 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk
),
340 CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk
),
341 CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk
),
342 CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk
),
343 CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk
),
344 CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk
),
345 CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk
),
346 CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk
),
347 CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk
),
350 static void __init
sama5d3_register_clocks(void)
354 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
355 clk_register(periph_clocks
[i
]);
357 clkdev_add_table(periph_clocks_lookups
,
358 ARRAY_SIZE(periph_clocks_lookups
));
365 /* --------------------------------------------------------------------
366 * AT91SAM9x5 processor initialization
367 * -------------------------------------------------------------------- */
369 static void __init
sama5d3_map_io(void)
371 at91_init_sram(0, SAMA5D3_SRAM_BASE
, SAMA5D3_SRAM_SIZE
);
374 static void __init
sama5d3_initialize(void)
376 at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC
);
379 AT91_SOC_START(sama5d3
)
380 .map_io
= sama5d3_map_io
,
381 .register_clocks
= sama5d3_register_clocks
,
382 .init
= sama5d3_initialize
,