2 * arch/arm/mach-dove/include/mach/bridge-regs.h
4 * Mbus-L to Mbus Bridge Registers
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #ifndef __ASM_ARCH_BRIDGE_REGS_H
12 #define __ASM_ARCH_BRIDGE_REGS_H
14 #include <mach/dove.h>
16 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
18 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
19 #define CPU_CTRL_PCIE0_LINK 0x00000001
20 #define CPU_RESET 0x00000002
21 #define CPU_CTRL_PCIE1_LINK 0x00000008
23 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
24 #define SOFT_RESET_OUT_EN 0x00000004
26 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27 #define SOFT_RESET 0x00000001
29 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
30 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
32 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
33 #define IRQ_CAUSE_LOW_OFF 0x0000
34 #define IRQ_MASK_LOW_OFF 0x0004
35 #define FIQ_MASK_LOW_OFF 0x0008
36 #define ENDPOINT_MASK_LOW_OFF 0x000c
37 #define IRQ_CAUSE_HIGH_OFF 0x0010
38 #define IRQ_MASK_HIGH_OFF 0x0014
39 #define FIQ_MASK_HIGH_OFF 0x0018
40 #define ENDPOINT_MASK_HIGH_OFF 0x001c
41 #define PCIE_INTERRUPT_MASK_OFF 0x0020
43 #define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
44 #define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
45 #define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
46 #define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
47 #define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
48 #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
49 #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
51 #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
53 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
54 #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)