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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-imx / clk-imx6q.c
blobef85ac49d9ac4b55e38584e3be6f5420b2503e5b
1 /*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23
24 #include "clk.h"
25 #include "common.h"
26 #include "hardware.h"
27
28 #define CCR 0x0
29 #define BM_CCR_WB_COUNT (0x7 << 16)
30 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
31 #define BM_CCR_RBC_EN (0x1 << 27)
32
33 #define CCGR0 0x68
34 #define CCGR1 0x6c
35 #define CCGR2 0x70
36 #define CCGR3 0x74
37 #define CCGR4 0x78
38 #define CCGR5 0x7c
39 #define CCGR6 0x80
40 #define CCGR7 0x84
41
42 #define CLPCR 0x54
43 #define BP_CLPCR_LPM 0
44 #define BM_CLPCR_LPM (0x3 << 0)
45 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
46 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
47 #define BM_CLPCR_SBYOS (0x1 << 6)
48 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
49 #define BM_CLPCR_VSTBY (0x1 << 8)
50 #define BP_CLPCR_STBY_COUNT 9
51 #define BM_CLPCR_STBY_COUNT (0x3 << 9)
52 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
53 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
54 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
55 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
56 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
57 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
58 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
59 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
60 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
61 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
62 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
63
64 #define CGPR 0x64
65 #define BM_CGPR_CHICKEN_BIT (0x1 << 17)
66
67 static void __iomem *ccm_base;
68
69 void imx6q_set_chicken_bit(void)
70 {
71 u32 val = readl_relaxed(ccm_base + CGPR);
72
73 val |= BM_CGPR_CHICKEN_BIT;
74 writel_relaxed(val, ccm_base + CGPR);
75 }
76
77 static void imx6q_enable_rbc(bool enable)
78 {
79 u32 val;
80 static bool last_rbc_mode;
81
82 if (last_rbc_mode == enable)
83 return;
84 /*
85 * need to mask all interrupts in GPC before
86 * operating RBC configurations
87 */
88 imx_gpc_mask_all();
89
90 /* configure RBC enable bit */
91 val = readl_relaxed(ccm_base + CCR);
92 val &= ~BM_CCR_RBC_EN;
93 val |= enable ? BM_CCR_RBC_EN : 0;
94 writel_relaxed(val, ccm_base + CCR);
95
96 /* configure RBC count */
97 val = readl_relaxed(ccm_base + CCR);
98 val &= ~BM_CCR_RBC_BYPASS_COUNT;
99 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
100 writel(val, ccm_base + CCR);
101
102 /*
103 * need to delay at least 2 cycles of CKIL(32K)
104 * due to hardware design requirement, which is
105 * ~61us, here we use 65us for safe
106 */
107 udelay(65);
108
109 /* restore GPC interrupt mask settings */
110 imx_gpc_restore_all();
111
112 last_rbc_mode = enable;
113 }
114
115 static void imx6q_enable_wb(bool enable)
116 {
117 u32 val;
118 static bool last_wb_mode;
119
120 if (last_wb_mode == enable)
121 return;
122
123 /* configure well bias enable bit */
124 val = readl_relaxed(ccm_base + CLPCR);
125 val &= ~BM_CLPCR_WB_PER_AT_LPM;
126 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
127 writel_relaxed(val, ccm_base + CLPCR);
128
129 /* configure well bias count */
130 val = readl_relaxed(ccm_base + CCR);
131 val &= ~BM_CCR_WB_COUNT;
132 val |= enable ? BM_CCR_WB_COUNT : 0;
133 writel_relaxed(val, ccm_base + CCR);
134
135 last_wb_mode = enable;
136 }
137
138 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
139 {
140 u32 val = readl_relaxed(ccm_base + CLPCR);
141
142 val &= ~BM_CLPCR_LPM;
143 switch (mode) {
144 case WAIT_CLOCKED:
145 imx6q_enable_wb(false);
146 imx6q_enable_rbc(false);
147 break;
148 case WAIT_UNCLOCKED:
149 val |= 0x1 << BP_CLPCR_LPM;
150 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
151 break;
152 case STOP_POWER_ON:
153 val |= 0x2 << BP_CLPCR_LPM;
154 break;
155 case WAIT_UNCLOCKED_POWER_OFF:
156 val |= 0x1 << BP_CLPCR_LPM;
157 val &= ~BM_CLPCR_VSTBY;
158 val &= ~BM_CLPCR_SBYOS;
159 break;
160 case STOP_POWER_OFF:
161 val |= 0x2 << BP_CLPCR_LPM;
162 val |= 0x3 << BP_CLPCR_STBY_COUNT;
163 val |= BM_CLPCR_VSTBY;
164 val |= BM_CLPCR_SBYOS;
165 imx6q_enable_wb(true);
166 imx6q_enable_rbc(true);
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 writel_relaxed(val, ccm_base + CLPCR);
173
174 return 0;
175 }
176
177 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
178 static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
179 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
180 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
181 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
182 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
183 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
184 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
185 static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
186 static const char *gpu_axi_sels[] = { "axi", "ahb", };
187 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
188 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
189 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
190 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
191 static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
192 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
193 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
194 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
195 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
196 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
197 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
198 static const char *pcie_axi_sels[] = { "axi", "ahb", };
199 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
200 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
201 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
202 static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
203 static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
204 static const char *vdo_axi_sels[] = { "axi", "ahb", };
205 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
206 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
207 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
208 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
209 static const char *cko2_sels[] = {
210 "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
211 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
212 "usdhc3", "dummy", "arm", "ipu1",
213 "ipu2", "vdo_axi", "osc", "gpu2d_core",
214 "gpu3d_core", "usdhc2", "ssi1", "ssi2",
215 "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
216 "ldb_di0", "ldb_di1", "esai", "eim_slow",
217 "uart_serial", "spdif", "asrc", "hsi_tx",
218 };
219 static const char *cko_sels[] = { "cko1", "cko2", };
220
221 enum mx6q_clks {
222 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
223 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
224 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
225 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
226 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
227 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
228 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
229 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
230 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
231 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
232 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
233 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
234 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
235 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
236 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
237 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
238 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
239 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
240 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
241 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
242 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
243 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
244 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
245 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
246 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
247 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
248 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
249 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
250 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
251 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
252 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
253 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
254 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
255 };
256
257 static struct clk *clk[clk_max];
258 static struct clk_onecell_data clk_data;
259
260 static enum mx6q_clks const clks_init_on[] __initconst = {
261 mmdc_ch0_axi, rom, pll1_sys,
262 };
263
264 static struct clk_div_table clk_enet_ref_table[] = {
265 { .val = 0, .div = 20, },
266 { .val = 1, .div = 10, },
267 { .val = 2, .div = 5, },
268 { .val = 3, .div = 4, },
269 };
270
271 static struct clk_div_table post_div_table[] = {
272 { .val = 2, .div = 1, },
273 { .val = 1, .div = 2, },
274 { .val = 0, .div = 4, },
275 { }
276 };
277
278 static struct clk_div_table video_div_table[] = {
279 { .val = 0, .div = 1, },
280 { .val = 1, .div = 2, },
281 { .val = 2, .div = 1, },
282 { .val = 3, .div = 4, },
283 { }
284 };
285
286 static void __init imx6q_clocks_init(struct device_node *ccm_node)
287 {
288 struct device_node *np;
289 void __iomem *base;
290 int i, irq;
291 int ret;
292
293 clk[dummy] = imx_clk_fixed("dummy", 0);
294 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
295 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
296 clk[osc] = imx_obtain_fixed_clock("osc", 0);
297
298 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
299 base = of_iomap(np, 0);
300 WARN_ON(!base);
301
302 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
303 if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
304 post_div_table[1].div = 1;
305 post_div_table[2].div = 1;
306 video_div_table[1].div = 1;
307 video_div_table[2].div = 1;
308 };
309
310 /* type name parent_name base div_mask */
311 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
312 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
313 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
314 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
315 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
316 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
317 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
318
319 /*
320 * Bit 20 is the reserved and read-only bit, we do this only for:
321 * - Do nothing for usbphy clk_enable/disable
322 * - Keep refcount when do usbphy clk_enable/disable, in that case,
323 * the clk framework may need to enable/disable usbphy's parent
324 */
325 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
326 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
327
328 /*
329 * usbphy*_gate needs to be on after system boots up, and software
330 * never needs to control it anymore.
331 */
332 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
333 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
334
335 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
336 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
337
338 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
339 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
340
341 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
342 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
343 &imx_ccm_lock);
344
345 /* name parent_name reg idx */
346 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
347 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
348 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
349 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
350 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
351 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
352 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
353
354 /* name parent_name mult div */
355 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
356 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
357 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
358 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
359 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
360
361 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
362 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
363 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
364
365 np = ccm_node;
366 base = of_iomap(np, 0);
367 WARN_ON(!base);
368 ccm_base = base;
369
370 /* name reg shift width parent_names num_parents */
371 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
372 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
373 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
374 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
375 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
376 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
377 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
378 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
379 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
380 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
381 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
382 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
383 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
384 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
385 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
386 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
387 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
388 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
389 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
390 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
391 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
392 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
393 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
394 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
395 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
396 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
397 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
398 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
399 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
400 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
401 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
402 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
403 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
404 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
405 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
406 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
407 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
408 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
409 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
410 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
411 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
412 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
413 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
414 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
415
416 /* name reg shift width busy: reg, shift parent_names num_parents */
417 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
418 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
419
420 /* name parent_name reg shift width */
421 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
422 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
423 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
424 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
425 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
426 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
427 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
428 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
429 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
430 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
431 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
432 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
433 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
434 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
435 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
436 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
437 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
438 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
439 clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
440 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
441 clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
442 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
443 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
444 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
445 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
446 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
447 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
448 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
449 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
450 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
451 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
452 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
453 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
454 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
455 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
456 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
457 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
458 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
459 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
460 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
461 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
462 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
463 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
464 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
465
466 /* name parent_name reg shift width busy: reg, shift */
467 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
468 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
469 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
470 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
471 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
472
473 /* name parent_name reg shift */
474 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
475 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
476 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
477 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
478 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
479 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
480 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
481 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
482 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
483 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
484 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
485 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
486 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
487 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
488 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
489 if (cpu_is_imx6dl())
490 /*
491 * The multiplexer and divider of imx6q clock gpu3d_shader get
492 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
493 */
494 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
495 else
496 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
497 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
498 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
499 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
500 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
501 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
502 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
503 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
504 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
505 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
506 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
507 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
508 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
509 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
510 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
511 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
512 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
513 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
514 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
515 if (cpu_is_imx6dl())
516 /*
517 * The multiplexer and divider of the imx6q clock gpu2d get
518 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
519 */
520 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
521 else
522 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
523 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
524 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
525 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
526 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
527 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
528 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
529 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
530 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
531 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
532 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
533 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
534 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
535 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
536 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
537 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
538 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
539 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
540 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
541 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
542 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
543 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
544 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
545 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
546 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
547 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
548 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
549 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
550 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
551 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
552 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
553 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
554 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
555 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
556 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
557
558 for (i = 0; i < ARRAY_SIZE(clk); i++)
559 if (IS_ERR(clk[i]))
560 pr_err("i.MX6q clk %d: register failed with %ld\n",
561 i, PTR_ERR(clk[i]));
562
563 clk_data.clks = clk;
564 clk_data.clk_num = ARRAY_SIZE(clk);
565 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
566
567 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
568 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
569 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
570 clk_register_clkdev(clk[ahb], "ahb", NULL);
571 clk_register_clkdev(clk[cko1], "cko1", NULL);
572 clk_register_clkdev(clk[arm], NULL, "cpu0");
573 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
574 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
575
576 if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
577 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
578 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
579 }
580
581 /*
582 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
583 * We can not get the 100MHz from the pll2_pfd0_352m.
584 * So choose pll2_pfd2_396m as enfc_sel's parent.
585 */
586 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
587
588 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
589 clk_prepare_enable(clk[clks_init_on[i]]);
590
591 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
592 clk_prepare_enable(clk[usbphy1_gate]);
593 clk_prepare_enable(clk[usbphy2_gate]);
594 }
595
596 /*
597 * Let's initially set up CLKO with OSC24M, since this configuration
598 * is widely used by imx6q board designs to clock audio codec.
599 */
600 ret = clk_set_parent(clk[cko2_sel], clk[osc]);
601 if (!ret)
602 ret = clk_set_parent(clk[cko], clk[cko2]);
603 if (ret)
604 pr_warn("failed to set up CLKO: %d\n", ret);
605
606 /* Set initial power mode */
607 imx6q_set_lpm(WAIT_CLOCKED);
608
609 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
610 base = of_iomap(np, 0);
611 WARN_ON(!base);
612 irq = irq_of_parse_and_map(np, 0);
613 mxc_timer_init(base, irq);
614 }
615 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
Linux with added FPC-III support