2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
21 #define __ASM_ARCH_MXC_HARDWARE_H__
24 #include <asm/sizes.h>
26 #define addr_in_module(addr, mod) \
27 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
29 #define IMX_IO_P2V_MODULE(addr, module) \
30 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
31 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
34 * This is rather complicated for humans and ugly to verify, but for a machine
35 * it's OK. Still more as it is usually only applied to constants. The upsides
36 * on using this approach are:
38 * - same mapping on all i.MX machines
39 * - works for assembler, too
40 * - no need to nurture #defines for virtual addresses
42 * The downside it, it's hard to verify (but I have a script for that).
44 * Obviously this needs to be injective for each SoC. In general it maps the
45 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
46 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
48 * It applies the following mappings for the different SoCs:
51 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
53 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
54 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
55 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
57 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
58 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
59 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
61 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
62 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
63 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
65 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
66 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
67 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
68 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
69 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
71 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
72 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
73 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
74 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
75 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
77 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
78 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
79 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
80 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
81 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
82 * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
84 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
85 * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
86 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
90 * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
91 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
92 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
93 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
95 #define IMX_IO_P2V(x) ( \
96 (((x) & 0x80000000) >> 7) | \
98 (((x) & 0x50000000) >> 6) + \
99 (((x) & 0x0b000000) >> 4) + \
100 (((x) & 0x000fffff))))
102 #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
117 #define imx_map_entry(soc, name, _type) { \
118 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
119 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
120 .length = soc ## _ ## name ## _SIZE, \
124 /* There's a off-by-one betweem the gpio bank number and the gpiochip */
125 /* range e.g. GPIO_1_5 is gpio 5 under linux */
126 #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
128 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */