x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-imx / system.c
blob80c177c36c5f25665ada2fbf93cf2ac4b007eee6
1 /*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
6 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/err.h>
23 #include <linux/delay.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
27 #include <asm/system_misc.h>
28 #include <asm/proc-fns.h>
29 #include <asm/mach-types.h>
30 #include <asm/hardware/cache-l2x0.h>
32 #include "common.h"
33 #include "hardware.h"
35 static void __iomem *wdog_base;
36 static struct clk *wdog_clk;
39 * Reset the system. It is called by machine_restart().
41 void mxc_restart(enum reboot_mode mode, const char *cmd)
43 unsigned int wcr_enable;
45 if (wdog_clk)
46 clk_enable(wdog_clk);
48 if (cpu_is_mx1())
49 wcr_enable = (1 << 0);
50 else
51 wcr_enable = (1 << 2);
53 /* Assert SRS signal */
54 __raw_writew(wcr_enable, wdog_base);
56 /* wait for reset to assert... */
57 mdelay(500);
59 pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
61 /* delay to allow the serial port to show the message */
62 mdelay(50);
64 /* we'll take a jump through zero as a poor second */
65 soft_restart(0);
68 void __init mxc_arch_reset_init(void __iomem *base)
70 wdog_base = base;
72 wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
73 if (IS_ERR(wdog_clk)) {
74 pr_warn("%s: failed to get wdog clock\n", __func__);
75 wdog_clk = NULL;
76 return;
79 clk_prepare(wdog_clk);
82 void __init mxc_arch_reset_init_dt(void)
84 struct device_node *np;
86 np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
87 wdog_base = of_iomap(np, 0);
88 WARN_ON(!wdog_base);
90 wdog_clk = of_clk_get(np, 0);
91 if (IS_ERR(wdog_clk)) {
92 pr_warn("%s: failed to get wdog clock\n", __func__);
93 wdog_clk = NULL;
94 return;
97 clk_prepare(wdog_clk);
100 #ifdef CONFIG_CACHE_L2X0
101 void __init imx_init_l2cache(void)
103 void __iomem *l2x0_base;
104 struct device_node *np;
105 unsigned int val;
107 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
108 if (!np)
109 goto out;
111 l2x0_base = of_iomap(np, 0);
112 if (!l2x0_base) {
113 of_node_put(np);
114 goto out;
117 /* Configure the L2 PREFETCH and POWER registers */
118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119 val |= 0x70800000;
121 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
123 * But according to ARM PL310 errata: 752271
124 * ID: 752271: Double linefill feature can cause data corruption
125 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
126 * Workaround: The only workaround to this erratum is to disable the
127 * double linefill feature. This is the default behavior.
129 if (cpu_is_imx6q())
130 val &= ~(1 << 30 | 1 << 23);
131 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
132 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
133 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
135 iounmap(l2x0_base);
136 of_node_put(np);
138 out:
139 l2x0_of_init(0, ~0UL);
141 #endif