arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/device.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/versatile-fpga.h>
  24 #include <linux/gfp.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/platform_data/clk-integrator.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/platform.h>
  34 #include <asm/setup.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst.h>
  38
  39 #include <mach/cm.h>
  40 #include <mach/lm.h>
  41 #include <mach/irqs.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/map.h>
  46 #include <asm/mach/time.h>
  47
  48 #include <asm/hardware/timer-sp.h>
  49
  50 #include <plat/clcd.h>
  51 #include <plat/sched_clock.h>
  52
  53 #include "common.h"
  54
  55 /* Base address to the CP controller */
  56 static void __iomem *intcp_con_base;
  57
  58 #define INTCP_PA_FLASH_BASE             0x24000000
  59
  60 #define INTCP_PA_CLCD_BASE              0xc0000000
  61
  62 #define INTCP_FLASHPROG                 0x04
  63 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  64 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  65
  66 /*
  67  * Logical      Physical
  68  * f1000000     10000000        Core module registers
  69  * f1100000     11000000        System controller registers
  70  * f1200000     12000000        EBI registers
  71  * f1300000     13000000        Counter/Timer
  72  * f1400000     14000000        Interrupt controller
  73  * f1600000     16000000        UART 0
  74  * f1700000     17000000        UART 1
  75  * f1a00000     1a000000        Debug LEDs
  76  * fc900000     c9000000        GPIO
  77  * fca00000     ca000000        SIC
  78  * fcb00000     cb000000        CP system control
  79  */
  80
  81 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
  82         {
  83                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  84                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  85                 .length         = SZ_4K,
  86                 .type           = MT_DEVICE
  87         }, {
  88                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  89                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  90                 .length         = SZ_4K,
  91                 .type           = MT_DEVICE
  92         }, {
  93                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  94                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE
  97         }, {
  98                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  99                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 100                 .length         = SZ_4K,
 101                 .type           = MT_DEVICE
 102         }, {
 103                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 104                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE
 107         }, {
 108                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 109                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE
 112         }, {
 113                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 114                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE
 117         }, {
 118                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 119                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE
 122         }
 123 };
 124
 125 static void __init intcp_map_io(void)
 126 {
 127         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 128 }
 129
 130 /*
 131  * Flash handling.
 132  */
 133 static int intcp_flash_init(struct platform_device *dev)
 134 {
 135         u32 val;
 136
 137         val = readl(intcp_con_base + INTCP_FLASHPROG);
 138         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 139         writel(val, intcp_con_base + INTCP_FLASHPROG);
 140
 141         return 0;
 142 }
 143
 144 static void intcp_flash_exit(struct platform_device *dev)
 145 {
 146         u32 val;
 147
 148         val = readl(intcp_con_base + INTCP_FLASHPROG);
 149         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 150         writel(val, intcp_con_base + INTCP_FLASHPROG);
 151 }
 152
 153 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 154 {
 155         u32 val;
 156
 157         val = readl(intcp_con_base + INTCP_FLASHPROG);
 158         if (on)
 159                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 160         else
 161                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 162         writel(val, intcp_con_base + INTCP_FLASHPROG);
 163 }
 164
 165 static struct physmap_flash_data intcp_flash_data = {
 166         .width          = 4,
 167         .init           = intcp_flash_init,
 168         .exit           = intcp_flash_exit,
 169         .set_vpp        = intcp_flash_set_vpp,
 170 };
 171
 172 /*
 173  * It seems that the card insertion interrupt remains active after
 174  * we've acknowledged it.  We therefore ignore the interrupt, and
 175  * rely on reading it from the SIC.  This also means that we must
 176  * clear the latched interrupt.
 177  */
 178 static unsigned int mmc_status(struct device *dev)
 179 {
 180         unsigned int status = readl(__io_address(0xca000000 + 4));
 181         writel(8, intcp_con_base + 8);
 182
 183         return status & 8;
 184 }
 185
 186 static struct mmci_platform_data mmc_data = {
 187         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 188         .status         = mmc_status,
 189         .gpio_wp        = -1,
 190         .gpio_cd        = -1,
 191 };
 192
 193 /*
 194  * CLCD support
 195  */
 196 /*
 197  * Ensure VGA is selected.
 198  */
 199 static void cp_clcd_enable(struct clcd_fb *fb)
 200 {
 201         struct fb_var_screeninfo *var = &fb->fb.var;
 202         u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
 203                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
 204
 205         if (var->bits_per_pixel <= 8 ||
 206             (var->bits_per_pixel == 16 && var->green.length == 5))
 207                 /* Pseudocolor, RGB555, BGR555 */
 208                 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 209         else if (fb->fb.var.bits_per_pixel <= 16)
 210                 /* truecolor RGB565 */
 211                 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 212         else
 213                 val = 0; /* no idea for this, don't trust the docs */
 214
 215         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 216                    CM_CTRL_LCDEN0|
 217                    CM_CTRL_LCDEN1|
 218                    CM_CTRL_STATIC1|
 219                    CM_CTRL_STATIC2|
 220                    CM_CTRL_STATIC|
 221                    CM_CTRL_n24BITEN, val);
 222 }
 223
 224 static int cp_clcd_setup(struct clcd_fb *fb)
 225 {
 226         fb->panel = versatile_clcd_get_panel("VGA");
 227         if (!fb->panel)
 228                 return -EINVAL;
 229
 230         return versatile_clcd_setup_dma(fb, SZ_1M);
 231 }
 232
 233 static struct clcd_board clcd_data = {
 234         .name           = "Integrator/CP",
 235         .caps           = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 236         .check          = clcdfb_check,
 237         .decode         = clcdfb_decode,
 238         .enable         = cp_clcd_enable,
 239         .setup          = cp_clcd_setup,
 240         .mmap           = versatile_clcd_mmap_dma,
 241         .remove         = versatile_clcd_remove_dma,
 242 };
 243
 244 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 245
 246 static void __init intcp_init_early(void)
 247 {
 248 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
 249         versatile_sched_clock_init(REFCOUNTER, 24000000);
 250 #endif
 251 }
 252
 253 #ifdef CONFIG_OF
 254 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 255         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 256         { /* Sentinel */ }
 257 };
 258
 259 static void __init intcp_init_irq_of(void)
 260 {
 261         of_irq_init(fpga_irq_of_match);
 262         integrator_clk_init(true);
 263 }
 264
 265 /*
 266  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 267  * and enforce the bus names since these are used for clock lookups.
 268  */
 269 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 270         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 271                 "rtc", NULL),
 272         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 273                 "uart0", NULL),
 274         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 275                 "uart1", NULL),
 276         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 277                 "kmi0", NULL),
 278         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 279                 "kmi1", NULL),
 280         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
 281                 "mmci", &mmc_data),
 282         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
 283                 "aaci", &mmc_data),
 284         OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 285                 "clcd", &clcd_data),
 286         OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
 287                 "physmap-flash", &intcp_flash_data),
 288         { /* sentinel */ },
 289 };
 290
 291 static void __init intcp_init_of(void)
 292 {
 293         struct device_node *root;
 294         struct device_node *cpcon;
 295         struct device *parent;
 296         struct soc_device *soc_dev;
 297         struct soc_device_attribute *soc_dev_attr;
 298         u32 intcp_sc_id;
 299         int err;
 300
 301         /* Here we create an SoC device for the root node */
 302         root = of_find_node_by_path("/");
 303         if (!root)
 304                 return;
 305         cpcon = of_find_node_by_path("/cpcon");
 306         if (!cpcon)
 307                 return;
 308
 309         intcp_con_base = of_iomap(cpcon, 0);
 310         if (!intcp_con_base)
 311                 return;
 312
 313         intcp_sc_id = readl(intcp_con_base);
 314
 315         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 316         if (!soc_dev_attr)
 317                 return;
 318
 319         err = of_property_read_string(root, "compatible",
 320                                       &soc_dev_attr->soc_id);
 321         if (err)
 322                 return;
 323         err = of_property_read_string(root, "model", &soc_dev_attr->machine);
 324         if (err)
 325                 return;
 326         soc_dev_attr->family = "Integrator";
 327         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
 328                                            'A' + (intcp_sc_id & 0x0f));
 329
 330         soc_dev = soc_device_register(soc_dev_attr);
 331         if (IS_ERR(soc_dev)) {
 332                 kfree(soc_dev_attr->revision);
 333                 kfree(soc_dev_attr);
 334                 return;
 335         }
 336
 337         parent = soc_device_to_device(soc_dev);
 338         integrator_init_sysfs(parent, intcp_sc_id);
 339         of_platform_populate(root, of_default_bus_match_table,
 340                         intcp_auxdata_lookup, parent);
 341 }
 342
 343 static const char * intcp_dt_board_compat[] = {
 344         "arm,integrator-cp",
 345         NULL,
 346 };
 347
 348 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 349         .reserve        = integrator_reserve,
 350         .map_io         = intcp_map_io,
 351         .init_early     = intcp_init_early,
 352         .init_irq       = intcp_init_irq_of,
 353         .handle_irq     = fpga_handle_irq,
 354         .init_machine   = intcp_init_of,
 355         .restart        = integrator_restart,
 356         .dt_compat      = intcp_dt_board_compat,
 357 MACHINE_END
 358
 359 #endif
 360
 361 #ifdef CONFIG_ATAGS
 362
 363 /*
 364  * For the ATAG boot some static mappings are needed. This will
 365  * go away with the ATAG support down the road.
 366  */
 367
 368 static struct map_desc intcp_io_desc_atag[] __initdata = {
 369         {
 370                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
 371                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
 372                 .length         = SZ_4K,
 373                 .type           = MT_DEVICE
 374         },
 375 };
 376
 377 static void __init intcp_map_io_atag(void)
 378 {
 379         iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
 380         intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
 381         intcp_map_io();
 382 }
 383
 384
 385 /*
 386  * This is where non-devicetree initialization code is collected and stashed
 387  * for eventual deletion.
 388  */
 389
 390 #define INTCP_FLASH_SIZE                SZ_32M
 391
 392 static struct resource intcp_flash_resource = {
 393         .start          = INTCP_PA_FLASH_BASE,
 394         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 395         .flags          = IORESOURCE_MEM,
 396 };
 397
 398 static struct platform_device intcp_flash_device = {
 399         .name           = "physmap-flash",
 400         .id             = 0,
 401         .dev            = {
 402                 .platform_data  = &intcp_flash_data,
 403         },
 404         .num_resources  = 1,
 405         .resource       = &intcp_flash_resource,
 406 };
 407
 408 #define INTCP_ETH_SIZE                  0x10
 409
 410 static struct resource smc91x_resources[] = {
 411         [0] = {
 412                 .start  = INTEGRATOR_CP_ETH_BASE,
 413                 .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
 414                 .flags  = IORESOURCE_MEM,
 415         },
 416         [1] = {
 417                 .start  = IRQ_CP_ETHINT,
 418                 .end    = IRQ_CP_ETHINT,
 419                 .flags  = IORESOURCE_IRQ,
 420         },
 421 };
 422
 423 static struct platform_device smc91x_device = {
 424         .name           = "smc91x",
 425         .id             = 0,
 426         .num_resources  = ARRAY_SIZE(smc91x_resources),
 427         .resource       = smc91x_resources,
 428 };
 429
 430 static struct platform_device *intcp_devs[] __initdata = {
 431         &intcp_flash_device,
 432         &smc91x_device,
 433 };
 434
 435 #define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
 436 #define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
 437 #define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
 438
 439 static void __init intcp_init_irq(void)
 440 {
 441         u32 pic_mask, cic_mask, sic_mask;
 442
 443         /* These masks are for the HW IRQ registers */
 444         pic_mask = ~((~0u) << (11 - 0));
 445         pic_mask |= (~((~0u) << (29 - 22))) << 22;
 446         cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
 447         sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
 448
 449         /*
 450          * Disable all interrupt sources
 451          */
 452         writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 453         writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 454         writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 455         writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 456         writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 457         writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 458
 459         fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
 460                       -1, pic_mask, NULL);
 461
 462         fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
 463                       -1, cic_mask, NULL);
 464
 465         fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
 466                       IRQ_CP_CPPLDINT, sic_mask, NULL);
 467
 468         integrator_clk_init(true);
 469 }
 470
 471 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
 472 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 473 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 474
 475 static void __init cp_timer_init(void)
 476 {
 477         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 478         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 479         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 480
 481         sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
 482         sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
 483 }
 484
 485 #define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
 486 #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
 487
 488 static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
 489         INTEGRATOR_CP_MMC_IRQS, &mmc_data);
 490
 491 static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
 492         INTEGRATOR_CP_AACI_IRQS, NULL);
 493
 494 static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
 495         { IRQ_CP_CLCDCINT }, &clcd_data);
 496
 497 static struct amba_device *amba_devs[] __initdata = {
 498         &mmc_device,
 499         &aaci_device,
 500         &clcd_device,
 501 };
 502
 503 static void __init intcp_init(void)
 504 {
 505         int i;
 506
 507         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 508
 509         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 510                 struct amba_device *d = amba_devs[i];
 511                 amba_device_register(d, &iomem_resource);
 512         }
 513         integrator_init(true);
 514 }
 515
 516 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 517         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 518         .atag_offset    = 0x100,
 519         .reserve        = integrator_reserve,
 520         .map_io         = intcp_map_io_atag,
 521         .init_early     = intcp_init_early,
 522         .init_irq       = intcp_init_irq,
 523         .handle_irq     = fpga_handle_irq,
 524         .init_time      = cp_timer_init,
 525         .init_machine   = intcp_init,
 526         .restart        = integrator_restart,
 527 MACHINE_END
 528
 529 #endif