| blob | 62a392bd0b57e778c0b0d64a5640d139c8e72fa3 |
1 /*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #undef DEBUG
15 #include <linux/kernel.h>
16 #include <linux/io.h>
29 /* Used by omap3_ctrl_save_padconf() */
30 #define START_PADCONF_SAVE 0x2
31 #define PADCONF_SAVE_DONE 0x1
36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
38 u32 boot_config_ptr;
39 u32 public_restore_ptr;
40 u32 secure_ram_restore_ptr;
41 u32 sdrc_module_semaphore;
42 u32 prcm_block_offset;
43 u32 sdrc_block_offset;
44 };
47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel;
49 u32 cm_clksel_core;
50 u32 cm_clksel_wkup;
51 u32 cm_clken_pll;
52 u32 cm_autoidle_pll;
53 u32 cm_clksel1_pll;
54 u32 cm_clksel2_pll;
55 u32 cm_clksel3_pll;
56 u32 cm_clken_pll_mpu;
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
60 u32 prcm_block_size;
61 };
64 u16 sysconfig;
65 u16 cs_cfg;
66 u16 sharing;
67 u16 err_type;
68 u32 dll_a_ctrl;
69 u32 dll_b_ctrl;
70 u32 power;
71 u32 cs_0;
72 u32 mcfg_0;
73 u16 mr_0;
74 u16 emr_1_0;
75 u16 emr_2_0;
76 u16 emr_3_0;
77 u32 actim_ctrla_0;
78 u32 actim_ctrlb_0;
79 u32 rfr_ctrl_0;
80 u32 cs_1;
81 u32 mcfg_1;
82 u16 mr_1;
83 u16 emr_1_1;
84 u16 emr_2_1;
85 u16 emr_3_1;
86 u32 actim_ctrla_1;
87 u32 actim_ctrlb_1;
88 u32 rfr_ctrl_1;
89 u16 dcdl_1_ctrl;
90 u16 dcdl_2_ctrl;
91 u32 flags;
92 u32 block_size;
93 };
97 /*
98 * This is used to store ARM registers in SDRAM before attempting
99 * an MPU OFF. The save and restore happens from the SRAM sleep code.
100 * The address is stored in scratchpad, so that it can be used
101 * during the restore path.
102 */
106 u32 sysconfig;
107 u32 devconf0;
108 u32 mem_dftrw0;
109 u32 mem_dftrw1;
110 u32 msuspendmux_0;
111 u32 msuspendmux_1;
112 u32 msuspendmux_2;
113 u32 msuspendmux_3;
114 u32 msuspendmux_4;
115 u32 msuspendmux_5;
116 u32 sec_ctrl;
117 u32 devconf1;
118 u32 csirxfe;
119 u32 iva2_bootaddr;
120 u32 iva2_bootmod;
121 u32 debobs_0;
122 u32 debobs_1;
123 u32 debobs_2;
124 u32 debobs_3;
125 u32 debobs_4;
126 u32 debobs_5;
127 u32 debobs_6;
128 u32 debobs_7;
129 u32 debobs_8;
130 u32 prog_io0;
131 u32 prog_io1;
132 u32 dss_dpll_spreading;
133 u32 core_dpll_spreading;
134 u32 per_dpll_spreading;
135 u32 usbhost_dpll_spreading;
136 u32 pbias_lite;
137 u32 temp_sensor;
138 u32 sramldo4;
139 u32 sramldo5;
140 u32 csi;
141 u32 padconf_sys_nirq;
142 };
147 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
148 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
152 {
155 }
158 {
160 }
163 {
165 }
168 {
170 }
173 {
175 }
178 {
180 }
183 {
185 }
188 {
190 }
192 /*
193 * On OMAP4 control pad are not addressable from control
194 * core base. So the common omap_ctrl_read/write APIs breaks
195 * Hence export separate APIs to manage the omap4 pad control
196 * registers. This APIs will work only for OMAP4
197 */
200 {
202 }
205 {
207 }
209 #ifdef CONFIG_ARCH_OMAP3
211 /**
212 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
213 * @bootmode: 8-bit value to pass to some boot code
214 *
215 * Set the bootmode in the scratchpad RAM. This is used after the
216 * system restarts. Not sure what actually uses this - it may be the
217 * bootloader, rather than the boot ROM - contrary to the preserved
218 * comment below. No return value.
219 */
221 {
222 u32 l;
226 /*
227 * Reserve the first word in scratchpad for communicating
228 * with the boot ROM. A pointer to a data structure
229 * describing the boot process can be stored there,
230 * cf. OMAP34xx TRM, Initialization / Software Booting
231 * Configuration.
232 *
233 * XXX This should use some omap_ctrl_writel()-type function
234 */
236 }
238 #endif
240 /**
241 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
242 * @bootaddr: physical address of the boot loader
243 *
244 * Set boot address for the boot loader of a supported processor
245 * when a power ON sequence occurs.
246 */
248 {
258 }
261 }
263 /**
264 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
265 * @bootmode: 8-bit value to pass to some boot code
266 *
267 * Sets boot mode for the boot loader of a supported processor
268 * when a power ON sequence occurs.
269 */
271 {
279 }
282 }
284 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
285 /*
286 * Clears the scratchpad contents in case of cold boot-
287 * called during bootup
288 */
290 {
296 OMAP3430_GLOBAL_COLD_RST_MASK) {
300 OMAP3430_GR_MOD,
301 OMAP3_PRM_RSTST_OFFSET);
302 }
303 }
305 /* Populate the scratchpad structure with restore structure */
307 {
309 u32 arm_context_addr;
314 /*
315 * Populate the Scratchpad contents
316 *
317 * The "get_*restore_pointer" functions are used to provide a
318 * physical restore address where the ROM code jumps while waking
319 * up from MPU OFF/OSWR state.
320 * The restore pointer is stored into the scratchpad.
321 */
331 else
337 else
344 /* Populate the PRCM block contents */
347 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
350 OMAP3_PRM_CLKSEL_OFFSET);
357 /*
358 * As per erratum i671, ROM code does not respect the PER DPLL
359 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
360 * Then, in anycase, clear these bits to avoid extra latencies.
361 */
381 /* Populate the SDRC block contents */
392 /*
393 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
394 * be programed to issue automatic self refresh on timeout
395 * of AUTO_CNT = 1 prior to any transition to OFF mode.
396 */
401 SDRC_POWER_CLKCTRL_MASK)) |
403 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
404 else
438 /* Copy all the contents to the scratchpad location */
442 /* Scratchpad contents being 32 bits, a divide by 4 done here */
449 /*
450 * Copies the address of the location in SDRAM where ARM
451 * registers get saved during a MPU OFF transition.
452 */
456 }
459 {
514 }
517 {
521 OMAP343X_CONTROL_MEM_DFTRW0);
523 OMAP343X_CONTROL_MEM_DFTRW1);
525 OMAP2_CONTROL_MSUSPENDMUX_0);
527 OMAP2_CONTROL_MSUSPENDMUX_1);
529 OMAP2_CONTROL_MSUSPENDMUX_2);
531 OMAP2_CONTROL_MSUSPENDMUX_3);
533 OMAP2_CONTROL_MSUSPENDMUX_4);
535 OMAP2_CONTROL_MSUSPENDMUX_5);
540 OMAP343X_CONTROL_IVA2_BOOTADDR);
542 OMAP343X_CONTROL_IVA2_BOOTMOD);
555 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
557 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
559 OMAP343X_CONTROL_PER_DPLL_SPREADING);
561 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
563 OMAP343X_CONTROL_PBIAS_LITE);
565 OMAP343X_CONTROL_TEMP_SENSOR);
570 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
572 }
575 {
579 }
581 /**
582 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
583 *
584 * Tell the SCM to start saving the padconf registers, then wait for
585 * the process to complete. Returns 0 unconditionally, although it
586 * should also eventually be able to return -ETIMEDOUT, if the save
587 * does not complete.
588 *
589 * XXX This function is missing a timeout. What should it be?
590 */
592 {
593 u32 cpo;
595 /* Save the padconf registers */
600 /* wait for the save to complete */
606 }