2 * arch/arm/mach-orion5x/pci.c
4 * PCI and PCIe functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/mbus.h>
17 #include <video/vga.h>
19 #include <asm/mach/pci.h>
20 #include <plat/pcie.h>
21 #include <plat/addr-map.h>
22 #include <mach/orion5x.h>
25 /*****************************************************************************
26 * Orion has one PCIe controller and one PCI controller.
28 * Note1: The local PCIe bus number is '0'. The local PCI bus number
29 * follows the scanned PCIe bridged busses, if any.
31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
33 * device bus, Orion registers, etc. However this code only enable the
34 * access to DDR banks.
35 ****************************************************************************/
38 /*****************************************************************************
40 ****************************************************************************/
41 #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
43 void __init
orion5x_pcie_id(u32
*dev
, u32
*rev
)
45 *dev
= orion_pcie_dev_id(PCIE_BASE
);
46 *rev
= orion_pcie_rev(PCIE_BASE
);
49 static int pcie_valid_config(int bus
, int dev
)
52 * Don't go out when trying to access --
53 * 1. nonexisting device on local bus
54 * 2. where there's no device connected (no link)
56 if (bus
== 0 && dev
== 0)
59 if (!orion_pcie_link_up(PCIE_BASE
))
62 if (bus
== 0 && dev
!= 1)
70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
71 * and then reading the PCIE_CONF_DATA register. Need to make sure these
72 * transactions are atomic.
74 static DEFINE_SPINLOCK(orion5x_pcie_lock
);
76 static int pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
82 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
84 return PCIBIOS_DEVICE_NOT_FOUND
;
87 spin_lock_irqsave(&orion5x_pcie_lock
, flags
);
88 ret
= orion_pcie_rd_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
89 spin_unlock_irqrestore(&orion5x_pcie_lock
, flags
);
94 static int pcie_rd_conf_wa(struct pci_bus
*bus
, u32 devfn
,
95 int where
, int size
, u32
*val
)
99 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0) {
101 return PCIBIOS_DEVICE_NOT_FOUND
;
105 * We only support access to the non-extended configuration
106 * space when using the WA access method (or we would have to
107 * sacrifice 256M of CPU virtual address space.)
109 if (where
>= 0x100) {
111 return PCIBIOS_DEVICE_NOT_FOUND
;
114 ret
= orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE
,
115 bus
, devfn
, where
, size
, val
);
120 static int pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
121 int where
, int size
, u32 val
)
126 if (pcie_valid_config(bus
->number
, PCI_SLOT(devfn
)) == 0)
127 return PCIBIOS_DEVICE_NOT_FOUND
;
129 spin_lock_irqsave(&orion5x_pcie_lock
, flags
);
130 ret
= orion_pcie_wr_conf(PCIE_BASE
, bus
, devfn
, where
, size
, val
);
131 spin_unlock_irqrestore(&orion5x_pcie_lock
, flags
);
136 static struct pci_ops pcie_ops
= {
137 .read
= pcie_rd_conf
,
138 .write
= pcie_wr_conf
,
142 static int __init
pcie_setup(struct pci_sys_data
*sys
)
144 struct resource
*res
;
148 * Generic PCIe unit setup.
150 orion_pcie_setup(PCIE_BASE
);
153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
156 dev
= orion_pcie_dev_id(PCIE_BASE
);
157 if (dev
== MV88F5181_DEV_ID
|| dev
== MV88F5182_DEV_ID
) {
158 printk(KERN_NOTICE
"Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
160 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET
,
161 ORION_MBUS_PCIE_WA_ATTR
,
162 ORION5X_PCIE_WA_PHYS_BASE
,
163 ORION5X_PCIE_WA_SIZE
);
164 pcie_ops
.read
= pcie_rd_conf_wa
;
167 pci_ioremap_io(sys
->busnr
* SZ_64K
, ORION5X_PCIE_IO_PHYS_BASE
);
172 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
174 panic("pcie_setup unable to alloc resources");
179 res
->name
= "PCIe Memory Space";
180 res
->flags
= IORESOURCE_MEM
;
181 res
->start
= ORION5X_PCIE_MEM_PHYS_BASE
;
182 res
->end
= res
->start
+ ORION5X_PCIE_MEM_SIZE
- 1;
183 if (request_resource(&iomem_resource
, res
))
184 panic("Request PCIe Memory resource failed\n");
185 pci_add_resource_offset(&sys
->resources
, res
, sys
->mem_offset
);
190 /*****************************************************************************
192 ****************************************************************************/
193 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
194 #define PCI_MODE ORION5X_PCI_REG(0xd00)
195 #define PCI_CMD ORION5X_PCI_REG(0xc00)
196 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
197 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
198 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
203 #define PCI_MODE_64BIT (1 << 2)
204 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
209 #define PCI_CMD_HOST_REORDER (1 << 29)
214 #define PCI_P2P_BUS_OFFS 16
215 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
216 #define PCI_P2P_DEV_OFFS 24
217 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
222 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
223 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
224 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
225 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
226 #define PCI_CONF_ADDR_EN (1 << 31)
229 * Internal configuration space
231 #define PCI_CONF_FUNC_STAT_CMD 0
232 #define PCI_CONF_REG_STAT_CMD 4
233 #define PCIX_STAT 0x64
234 #define PCIX_STAT_BUS_OFFS 8
235 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
238 * PCI Address Decode Windows registers
240 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
241 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
242 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
243 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
244 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
245 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
246 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
247 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
248 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
249 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
252 * PCI configuration helpers for BAR settings
254 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
255 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
256 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
259 * PCI config cycles are done by programming the PCI_CONF_ADDR register
260 * and then reading the PCI_CONF_DATA register. Need to make sure these
261 * transactions are atomic.
263 static DEFINE_SPINLOCK(orion5x_pci_lock
);
265 static int orion5x_pci_cardbus_mode
;
267 static int orion5x_pci_local_bus_nr(void)
269 u32 conf
= readl(PCI_P2P_CONF
);
270 return((conf
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
);
273 static int orion5x_pci_hw_rd_conf(int bus
, int dev
, u32 func
,
274 u32 where
, u32 size
, u32
*val
)
277 spin_lock_irqsave(&orion5x_pci_lock
, flags
);
279 writel(PCI_CONF_BUS(bus
) |
280 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
281 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
, PCI_CONF_ADDR
);
283 *val
= readl(PCI_CONF_DATA
);
286 *val
= (*val
>> (8*(where
& 0x3))) & 0xff;
288 *val
= (*val
>> (8*(where
& 0x3))) & 0xffff;
290 spin_unlock_irqrestore(&orion5x_pci_lock
, flags
);
292 return PCIBIOS_SUCCESSFUL
;
295 static int orion5x_pci_hw_wr_conf(int bus
, int dev
, u32 func
,
296 u32 where
, u32 size
, u32 val
)
299 int ret
= PCIBIOS_SUCCESSFUL
;
301 spin_lock_irqsave(&orion5x_pci_lock
, flags
);
303 writel(PCI_CONF_BUS(bus
) |
304 PCI_CONF_DEV(dev
) | PCI_CONF_REG(where
) |
305 PCI_CONF_FUNC(func
) | PCI_CONF_ADDR_EN
, PCI_CONF_ADDR
);
308 __raw_writel(val
, PCI_CONF_DATA
);
309 } else if (size
== 2) {
310 __raw_writew(val
, PCI_CONF_DATA
+ (where
& 0x3));
311 } else if (size
== 1) {
312 __raw_writeb(val
, PCI_CONF_DATA
+ (where
& 0x3));
314 ret
= PCIBIOS_BAD_REGISTER_NUMBER
;
317 spin_unlock_irqrestore(&orion5x_pci_lock
, flags
);
322 static int orion5x_pci_valid_config(int bus
, u32 devfn
)
324 if (bus
== orion5x_pci_local_bus_nr()) {
326 * Don't go out for local device
328 if (PCI_SLOT(devfn
) == 0 && PCI_FUNC(devfn
) != 0)
332 * When the PCI signals are directly connected to a
333 * Cardbus slot, ignore all but device IDs 0 and 1.
335 if (orion5x_pci_cardbus_mode
&& PCI_SLOT(devfn
) > 1)
342 static int orion5x_pci_rd_conf(struct pci_bus
*bus
, u32 devfn
,
343 int where
, int size
, u32
*val
)
345 if (!orion5x_pci_valid_config(bus
->number
, devfn
)) {
347 return PCIBIOS_DEVICE_NOT_FOUND
;
350 return orion5x_pci_hw_rd_conf(bus
->number
, PCI_SLOT(devfn
),
351 PCI_FUNC(devfn
), where
, size
, val
);
354 static int orion5x_pci_wr_conf(struct pci_bus
*bus
, u32 devfn
,
355 int where
, int size
, u32 val
)
357 if (!orion5x_pci_valid_config(bus
->number
, devfn
))
358 return PCIBIOS_DEVICE_NOT_FOUND
;
360 return orion5x_pci_hw_wr_conf(bus
->number
, PCI_SLOT(devfn
),
361 PCI_FUNC(devfn
), where
, size
, val
);
364 static struct pci_ops pci_ops
= {
365 .read
= orion5x_pci_rd_conf
,
366 .write
= orion5x_pci_wr_conf
,
369 static void __init
orion5x_pci_set_bus_nr(int nr
)
371 u32 p2p
= readl(PCI_P2P_CONF
);
373 if (readl(PCI_MODE
) & PCI_MODE_PCIX
) {
377 u32 pcix_status
, bus
, dev
;
378 bus
= (p2p
& PCI_P2P_BUS_MASK
) >> PCI_P2P_BUS_OFFS
;
379 dev
= (p2p
& PCI_P2P_DEV_MASK
) >> PCI_P2P_DEV_OFFS
;
380 orion5x_pci_hw_rd_conf(bus
, dev
, 0, PCIX_STAT
, 4, &pcix_status
);
381 pcix_status
&= ~PCIX_STAT_BUS_MASK
;
382 pcix_status
|= (nr
<< PCIX_STAT_BUS_OFFS
);
383 orion5x_pci_hw_wr_conf(bus
, dev
, 0, PCIX_STAT
, 4, pcix_status
);
386 * PCI Conventional mode
388 p2p
&= ~PCI_P2P_BUS_MASK
;
389 p2p
|= (nr
<< PCI_P2P_BUS_OFFS
);
390 writel(p2p
, PCI_P2P_CONF
);
394 static void __init
orion5x_pci_master_slave_enable(void)
396 int bus_nr
, func
, reg
;
399 bus_nr
= orion5x_pci_local_bus_nr();
400 func
= PCI_CONF_FUNC_STAT_CMD
;
401 reg
= PCI_CONF_REG_STAT_CMD
;
402 orion5x_pci_hw_rd_conf(bus_nr
, 0, func
, reg
, 4, &val
);
403 val
|= (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
404 orion5x_pci_hw_wr_conf(bus_nr
, 0, func
, reg
, 4, val
| 0x7);
407 static void __init
orion5x_setup_pci_wins(void)
409 const struct mbus_dram_target_info
*dram
= mv_mbus_dram_info();
415 * First, disable windows.
417 win_enable
= 0xffffffff;
418 writel(win_enable
, PCI_BAR_ENABLE
);
421 * Setup windows for DDR banks.
423 bus
= orion5x_pci_local_bus_nr();
425 for (i
= 0; i
< dram
->num_cs
; i
++) {
426 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
427 u32 func
= PCI_CONF_FUNC_BAR_CS(cs
->cs_index
);
432 * Write DRAM bank base address register.
434 reg
= PCI_CONF_REG_BAR_LO_CS(cs
->cs_index
);
435 orion5x_pci_hw_rd_conf(bus
, 0, func
, reg
, 4, &val
);
436 val
= (cs
->base
& 0xfffff000) | (val
& 0xfff);
437 orion5x_pci_hw_wr_conf(bus
, 0, func
, reg
, 4, val
);
440 * Write DRAM bank size register.
442 reg
= PCI_CONF_REG_BAR_HI_CS(cs
->cs_index
);
443 orion5x_pci_hw_wr_conf(bus
, 0, func
, reg
, 4, 0);
444 writel((cs
->size
- 1) & 0xfffff000,
445 PCI_BAR_SIZE_DDR_CS(cs
->cs_index
));
446 writel(cs
->base
& 0xfffff000,
447 PCI_BAR_REMAP_DDR_CS(cs
->cs_index
));
450 * Enable decode window for this chip select.
452 win_enable
&= ~(1 << cs
->cs_index
);
456 * Re-enable decode windows.
458 writel(win_enable
, PCI_BAR_ENABLE
);
461 * Disable automatic update of address remapping when writing to BARs.
463 orion5x_setbits(PCI_ADDR_DECODE_CTRL
, 1);
466 static int __init
pci_setup(struct pci_sys_data
*sys
)
468 struct resource
*res
;
471 * Point PCI unit MBUS decode windows to DRAM space.
473 orion5x_setup_pci_wins();
476 * Master + Slave enable
478 orion5x_pci_master_slave_enable();
483 orion5x_setbits(PCI_CMD
, PCI_CMD_HOST_REORDER
);
485 pci_ioremap_io(sys
->busnr
* SZ_64K
, ORION5X_PCI_IO_PHYS_BASE
);
490 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
492 panic("pci_setup unable to alloc resources");
497 res
->name
= "PCI Memory Space";
498 res
->flags
= IORESOURCE_MEM
;
499 res
->start
= ORION5X_PCI_MEM_PHYS_BASE
;
500 res
->end
= res
->start
+ ORION5X_PCI_MEM_SIZE
- 1;
501 if (request_resource(&iomem_resource
, res
))
502 panic("Request PCI Memory resource failed\n");
503 pci_add_resource_offset(&sys
->resources
, res
, sys
->mem_offset
);
509 /*****************************************************************************
511 ****************************************************************************/
512 static void rc_pci_fixup(struct pci_dev
*dev
)
515 * Prevent enumeration of root complex.
517 if (dev
->bus
->parent
== NULL
&& dev
->devfn
== 0) {
520 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
521 dev
->resource
[i
].start
= 0;
522 dev
->resource
[i
].end
= 0;
523 dev
->resource
[i
].flags
= 0;
527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL
, PCI_ANY_ID
, rc_pci_fixup
);
529 static int orion5x_pci_disabled __initdata
;
531 void __init
orion5x_pci_disable(void)
533 orion5x_pci_disabled
= 1;
536 void __init
orion5x_pci_set_cardbus_mode(void)
538 orion5x_pci_cardbus_mode
= 1;
541 int __init
orion5x_pci_sys_setup(int nr
, struct pci_sys_data
*sys
)
545 vga_base
= ORION5X_PCIE_MEM_PHYS_BASE
;
548 orion_pcie_set_local_bus_nr(PCIE_BASE
, sys
->busnr
);
549 ret
= pcie_setup(sys
);
550 } else if (nr
== 1 && !orion5x_pci_disabled
) {
551 orion5x_pci_set_bus_nr(sys
->busnr
);
552 ret
= pci_setup(sys
);
558 struct pci_bus __init
*orion5x_pci_sys_scan_bus(int nr
, struct pci_sys_data
*sys
)
563 bus
= pci_scan_root_bus(NULL
, sys
->busnr
, &pcie_ops
, sys
,
565 } else if (nr
== 1 && !orion5x_pci_disabled
) {
566 bus
= pci_scan_root_bus(NULL
, sys
->busnr
, &pci_ops
, sys
,
576 int __init
orion5x_pci_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
578 int bus
= dev
->bus
->number
;
583 if (orion5x_pci_disabled
|| bus
< orion5x_pci_local_bus_nr())
584 return IRQ_ORION5X_PCIE0_INT
;