2 * power management entry for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/kernel.h>
10 #include <linux/suspend.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/of_platform.h>
18 #include <linux/rtc/sirfsoc_rtciobrg.h>
19 #include <asm/suspend.h>
20 #include <asm/hardware/cache-l2x0.h>
25 * suspend asm codes will access these to make DRAM become self-refresh and
28 u32 sirfsoc_pwrc_base
;
29 void __iomem
*sirfsoc_memc_base
;
31 static void sirfsoc_set_wakeup_source(void)
33 u32 pwr_trigger_en_reg
;
34 pwr_trigger_en_reg
= sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base
+
35 SIRFSOC_PWRC_TRIGGER_EN
);
36 #define X_ON_KEY_B (1 << 0)
37 #define RTC_ALARM0_B (1 << 2)
38 #define RTC_ALARM1_B (1 << 3)
39 sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg
| X_ON_KEY_B
|
40 RTC_ALARM0_B
| RTC_ALARM1_B
,
41 sirfsoc_pwrc_base
+ SIRFSOC_PWRC_TRIGGER_EN
);
44 static void sirfsoc_set_sleep_mode(u32 mode
)
46 u32 sleep_mode
= sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base
+
47 SIRFSOC_PWRC_PDN_CTRL
);
48 sleep_mode
&= ~(SIRFSOC_SLEEP_MODE_MASK
<< 1);
49 sleep_mode
|= mode
<< 1;
50 sirfsoc_rtc_iobrg_writel(sleep_mode
, sirfsoc_pwrc_base
+
51 SIRFSOC_PWRC_PDN_CTRL
);
54 static int sirfsoc_pre_suspend_power_off(void)
56 u32 wakeup_entry
= virt_to_phys(cpu_resume
);
58 sirfsoc_rtc_iobrg_writel(wakeup_entry
, sirfsoc_pwrc_base
+
59 SIRFSOC_PWRC_SCRATCH_PAD1
);
61 sirfsoc_set_wakeup_source();
63 sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE
);
68 static int sirfsoc_pm_enter(suspend_state_t state
)
72 sirfsoc_pre_suspend_power_off();
77 cpu_suspend(0, sirfsoc_finish_suspend
);
86 static const struct platform_suspend_ops sirfsoc_pm_ops
= {
87 .enter
= sirfsoc_pm_enter
,
88 .valid
= suspend_valid_only_mem
,
91 static const struct of_device_id pwrc_ids
[] = {
92 { .compatible
= "sirf,prima2-pwrc" },
96 static int __init
sirfsoc_of_pwrc_init(void)
98 struct device_node
*np
;
100 np
= of_find_matching_node(NULL
, pwrc_ids
);
102 pr_err("unable to find compatible sirf pwrc node in dtb\n");
107 * pwrc behind rtciobrg is not located in memory space
108 * though the property is named reg. reg only means base
109 * offset for pwrc. then of_iomap is not suitable here.
111 if (of_property_read_u32(np
, "reg", &sirfsoc_pwrc_base
))
112 panic("unable to find base address of pwrc node in dtb\n");
119 static const struct of_device_id memc_ids
[] = {
120 { .compatible
= "sirf,prima2-memc" },
124 static int sirfsoc_memc_probe(struct platform_device
*op
)
126 struct device_node
*np
= op
->dev
.of_node
;
128 sirfsoc_memc_base
= of_iomap(np
, 0);
129 if (!sirfsoc_memc_base
)
130 panic("unable to map memc registers\n");
135 static struct platform_driver sirfsoc_memc_driver
= {
136 .probe
= sirfsoc_memc_probe
,
138 .name
= "sirfsoc-memc",
139 .owner
= THIS_MODULE
,
140 .of_match_table
= memc_ids
,
144 static int __init
sirfsoc_memc_init(void)
146 return platform_driver_register(&sirfsoc_memc_driver
);
149 int __init
sirfsoc_pm_init(void)
151 sirfsoc_of_pwrc_init();
153 suspend_set_ops(&sirfsoc_pm_ops
);