x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-realview / realview_pb1176.c
blobc5eade76461be3cf2faa4d6dffbb9becc7cbb872
1 /*
2 * linux/arch/arm/mach-realview/realview_pb1176.c
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/device.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl061.h>
27 #include <linux/amba/mmci.h>
28 #include <linux/amba/pl022.h>
29 #include <linux/mtd/physmap.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/io.h>
32 #include <linux/irqchip/arm-gic.h>
33 #include <linux/platform_data/clk-realview.h>
34 #include <linux/reboot.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/pgtable.h>
40 #include <asm/hardware/cache-l2x0.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/time.h>
47 #include <mach/board-pb1176.h>
48 #include <mach/irqs.h>
50 #include "core.h"
52 static struct map_desc realview_pb1176_io_desc[] __initdata = {
54 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
55 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
60 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
65 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
76 .length = SZ_4K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
80 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
85 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
90 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
95 .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
96 .length = SZ_8K,
97 .type = MT_DEVICE,
99 #ifdef CONFIG_DEBUG_LL
101 .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
102 .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
106 #endif
109 static void __init realview_pb1176_map_io(void)
111 iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
114 static struct pl061_platform_data gpio0_plat_data = {
115 .gpio_base = 0,
118 static struct pl061_platform_data gpio1_plat_data = {
119 .gpio_base = 8,
122 static struct pl061_platform_data gpio2_plat_data = {
123 .gpio_base = 16,
126 static struct pl022_ssp_controller ssp0_plat_data = {
127 .bus_id = 0,
128 .enable_dma = 0,
129 .num_chipselect = 1,
133 * RealView PB1176 AMBA devices
135 #define GPIO2_IRQ { IRQ_PB1176_GPIO2 }
136 #define GPIO3_IRQ { IRQ_PB1176_GPIO3 }
137 #define AACI_IRQ { IRQ_PB1176_AACI }
138 #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
139 #define KMI0_IRQ { IRQ_PB1176_KMI0 }
140 #define KMI1_IRQ { IRQ_PB1176_KMI1 }
141 #define PB1176_SMC_IRQ { }
142 #define MPMC_IRQ { }
143 #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
144 #define SCTL_IRQ { }
145 #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG }
146 #define PB1176_GPIO0_IRQ { IRQ_DC1176_GPIO0 }
147 #define GPIO1_IRQ { IRQ_PB1176_GPIO1 }
148 #define PB1176_RTC_IRQ { IRQ_DC1176_RTC }
149 #define SCI_IRQ { IRQ_PB1176_SCI }
150 #define PB1176_UART0_IRQ { IRQ_DC1176_UART0 }
151 #define PB1176_UART1_IRQ { IRQ_DC1176_UART1 }
152 #define PB1176_UART2_IRQ { IRQ_DC1176_UART2 }
153 #define PB1176_UART3_IRQ { IRQ_DC1176_UART3 }
154 #define PB1176_UART4_IRQ { IRQ_PB1176_UART4 }
155 #define PB1176_SSP_IRQ { IRQ_DC1176_SSP }
157 /* FPGA Primecells */
158 APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
159 APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
160 APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
161 APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
162 APB_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL);
164 /* DevChip Primecells */
165 AHB_DEVICE(smc, "dev:smc", PB1176_SMC, NULL);
166 AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
167 APB_DEVICE(wdog, "dev:wdog", PB1176_WATCHDOG, NULL);
168 APB_DEVICE(gpio0, "dev:gpio0", PB1176_GPIO0, &gpio0_plat_data);
169 APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
170 APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
171 APB_DEVICE(rtc, "dev:rtc", PB1176_RTC, NULL);
172 APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
173 APB_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL);
174 APB_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL);
175 APB_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL);
176 APB_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL);
177 APB_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data);
178 AHB_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data);
180 static struct amba_device *amba_devs[] __initdata = {
181 &uart0_device,
182 &uart1_device,
183 &uart2_device,
184 &uart3_device,
185 &uart4_device,
186 &smc_device,
187 &clcd_device,
188 &sctl_device,
189 &wdog_device,
190 &gpio0_device,
191 &gpio1_device,
192 &gpio2_device,
193 &rtc_device,
194 &sci0_device,
195 &ssp0_device,
196 &aaci_device,
197 &mmc0_device,
198 &kmi0_device,
199 &kmi1_device,
203 * RealView PB1176 platform devices
205 static struct resource realview_pb1176_flash_resources[] = {
207 .start = REALVIEW_PB1176_FLASH_BASE,
208 .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
209 .flags = IORESOURCE_MEM,
211 #ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH
213 .start = REALVIEW_PB1176_SEC_FLASH_BASE,
214 .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1,
215 .flags = IORESOURCE_MEM,
217 #endif
220 static struct physmap_flash_data pb1176_rom_pdata = {
221 .probe_type = "map_rom",
222 .width = 4,
223 .nr_parts = 0,
226 static struct resource pb1176_rom_resources[] = {
228 * This exposes the PB1176 DevChip ROM as an MTD ROM mapping.
229 * The reference manual states that this is actually a pseudo-ROM
230 * programmed in NVRAM.
233 .start = REALVIEW_DC1176_ROM_BASE,
234 .end = REALVIEW_DC1176_ROM_BASE + SZ_16K - 1,
235 .flags = IORESOURCE_MEM,
239 static struct platform_device pb1176_rom_device = {
240 .name = "physmap-flash",
241 .id = -1,
242 .num_resources = ARRAY_SIZE(pb1176_rom_resources),
243 .resource = pb1176_rom_resources,
244 .dev = {
245 .platform_data = &pb1176_rom_pdata,
249 static struct resource realview_pb1176_smsc911x_resources[] = {
250 [0] = {
251 .start = REALVIEW_PB1176_ETH_BASE,
252 .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
253 .flags = IORESOURCE_MEM,
255 [1] = {
256 .start = IRQ_PB1176_ETH,
257 .end = IRQ_PB1176_ETH,
258 .flags = IORESOURCE_IRQ,
262 static struct resource realview_pb1176_isp1761_resources[] = {
263 [0] = {
264 .start = REALVIEW_PB1176_USB_BASE,
265 .end = REALVIEW_PB1176_USB_BASE + SZ_128K - 1,
266 .flags = IORESOURCE_MEM,
268 [1] = {
269 .start = IRQ_PB1176_USB,
270 .end = IRQ_PB1176_USB,
271 .flags = IORESOURCE_IRQ,
275 static struct resource pmu_resource = {
276 .start = IRQ_DC1176_CORE_PMU,
277 .end = IRQ_DC1176_CORE_PMU,
278 .flags = IORESOURCE_IRQ,
281 static struct platform_device pmu_device = {
282 .name = "arm-pmu",
283 .id = -1,
284 .num_resources = 1,
285 .resource = &pmu_resource,
288 static struct resource char_lcd_resources[] = {
290 .start = REALVIEW_CHAR_LCD_BASE,
291 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
292 .flags = IORESOURCE_MEM,
295 .start = IRQ_PB1176_CHARLCD,
296 .end = IRQ_PB1176_CHARLCD,
297 .flags = IORESOURCE_IRQ,
301 static struct platform_device char_lcd_device = {
302 .name = "arm-charlcd",
303 .id = -1,
304 .num_resources = ARRAY_SIZE(char_lcd_resources),
305 .resource = char_lcd_resources,
308 static void __init gic_init_irq(void)
310 /* ARM1176 DevChip GIC, primary */
311 gic_init(0, IRQ_DC1176_GIC_START,
312 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
313 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
315 /* board GIC, secondary */
316 gic_init(1, IRQ_PB1176_GIC_START,
317 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
318 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
319 gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
322 static void __init realview_pb1176_timer_init(void)
324 timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
325 timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
326 timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
327 timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
329 realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
330 realview_timer_init(IRQ_DC1176_TIMER0);
333 static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
335 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
336 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
337 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
338 __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl);
339 dsb();
342 static void realview_pb1176_fixup(struct tag *tags, char **from,
343 struct meminfo *meminfo)
346 * RealView PB1176 only has 128MB of RAM mapped at 0.
348 meminfo->bank[0].start = 0;
349 meminfo->bank[0].size = SZ_128M;
350 meminfo->nr_banks = 1;
353 static void __init realview_pb1176_init(void)
355 int i;
357 #ifdef CONFIG_CACHE_L2X0
358 /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
359 l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
360 #endif
362 realview_flash_register(realview_pb1176_flash_resources,
363 ARRAY_SIZE(realview_pb1176_flash_resources));
364 platform_device_register(&pb1176_rom_device);
365 realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
366 platform_device_register(&realview_i2c_device);
367 realview_usb_register(realview_pb1176_isp1761_resources);
368 platform_device_register(&pmu_device);
369 platform_device_register(&char_lcd_device);
371 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
372 struct amba_device *d = amba_devs[i];
373 amba_device_register(d, &iomem_resource);
377 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
378 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
379 .atag_offset = 0x100,
380 .fixup = realview_pb1176_fixup,
381 .map_io = realview_pb1176_map_io,
382 .init_early = realview_init_early,
383 .init_irq = gic_init_irq,
384 .init_time = realview_pb1176_timer_init,
385 .init_machine = realview_pb1176_init,
386 #ifdef CONFIG_ZONE_DMA
387 .dma_zone_size = SZ_256M,
388 #endif
389 .restart = realview_pb1176_restart,
390 MACHINE_END