arch/arm/mach-s3c24xx/common.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Common code for S3C24XX machines
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <clocksource/samsung_pwm.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include <mach/hardware.h>
  36 #include <mach/regs-clock.h>
  37 #include <asm/irq.h>
  38 #include <asm/cacheflush.h>
  39 #include <asm/system_info.h>
  40 #include <asm/system_misc.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/map.h>
  44
  45 #include <mach/regs-gpio.h>
  46 #include <plat/regs-serial.h>
  47
  48 #include <plat/cpu.h>
  49 #include <plat/devs.h>
  50 #include <plat/clock.h>
  51 #include <plat/cpu-freq.h>
  52 #include <plat/pll.h>
  53 #include <plat/pwm-core.h>
  54
  55 #include "common.h"
  56
  57 /* table of supported CPUs */
  58
  59 static const char name_s3c2410[]  = "S3C2410";
  60 static const char name_s3c2412[]  = "S3C2412";
  61 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  62 static const char name_s3c2440[]  = "S3C2440";
  63 static const char name_s3c2442[]  = "S3C2442";
  64 static const char name_s3c2442b[]  = "S3C2442B";
  65 static const char name_s3c2443[]  = "S3C2443";
  66 static const char name_s3c2410a[] = "S3C2410A";
  67 static const char name_s3c2440a[] = "S3C2440A";
  68
  69 static struct cpu_table cpu_ids[] __initdata = {
  70         {
  71                 .idcode         = 0x32410000,
  72                 .idmask         = 0xffffffff,
  73                 .map_io         = s3c2410_map_io,
  74                 .init_clocks    = s3c2410_init_clocks,
  75                 .init_uarts     = s3c2410_init_uarts,
  76                 .init           = s3c2410_init,
  77                 .name           = name_s3c2410
  78         },
  79         {
  80                 .idcode         = 0x32410002,
  81                 .idmask         = 0xffffffff,
  82                 .map_io         = s3c2410_map_io,
  83                 .init_clocks    = s3c2410_init_clocks,
  84                 .init_uarts     = s3c2410_init_uarts,
  85                 .init           = s3c2410a_init,
  86                 .name           = name_s3c2410a
  87         },
  88         {
  89                 .idcode         = 0x32440000,
  90                 .idmask         = 0xffffffff,
  91                 .map_io         = s3c2440_map_io,
  92                 .init_clocks    = s3c244x_init_clocks,
  93                 .init_uarts     = s3c244x_init_uarts,
  94                 .init           = s3c2440_init,
  95                 .name           = name_s3c2440
  96         },
  97         {
  98                 .idcode         = 0x32440001,
  99                 .idmask         = 0xffffffff,
 100                 .map_io         = s3c2440_map_io,
 101                 .init_clocks    = s3c244x_init_clocks,
 102                 .init_uarts     = s3c244x_init_uarts,
 103                 .init           = s3c2440_init,
 104                 .name           = name_s3c2440a
 105         },
 106         {
 107                 .idcode         = 0x32440aaa,
 108                 .idmask         = 0xffffffff,
 109                 .map_io         = s3c2442_map_io,
 110                 .init_clocks    = s3c244x_init_clocks,
 111                 .init_uarts     = s3c244x_init_uarts,
 112                 .init           = s3c2442_init,
 113                 .name           = name_s3c2442
 114         },
 115         {
 116                 .idcode         = 0x32440aab,
 117                 .idmask         = 0xffffffff,
 118                 .map_io         = s3c2442_map_io,
 119                 .init_clocks    = s3c244x_init_clocks,
 120                 .init_uarts     = s3c244x_init_uarts,
 121                 .init           = s3c2442_init,
 122                 .name           = name_s3c2442b
 123         },
 124         {
 125                 .idcode         = 0x32412001,
 126                 .idmask         = 0xffffffff,
 127                 .map_io         = s3c2412_map_io,
 128                 .init_clocks    = s3c2412_init_clocks,
 129                 .init_uarts     = s3c2412_init_uarts,
 130                 .init           = s3c2412_init,
 131                 .name           = name_s3c2412,
 132         },
 133         {                       /* a newer version of the s3c2412 */
 134                 .idcode         = 0x32412003,
 135                 .idmask         = 0xffffffff,
 136                 .map_io         = s3c2412_map_io,
 137                 .init_clocks    = s3c2412_init_clocks,
 138                 .init_uarts     = s3c2412_init_uarts,
 139                 .init           = s3c2412_init,
 140                 .name           = name_s3c2412,
 141         },
 142         {                       /* a strange version of the s3c2416 */
 143                 .idcode         = 0x32450003,
 144                 .idmask         = 0xffffffff,
 145                 .map_io         = s3c2416_map_io,
 146                 .init_clocks    = s3c2416_init_clocks,
 147                 .init_uarts     = s3c2416_init_uarts,
 148                 .init           = s3c2416_init,
 149                 .name           = name_s3c2416,
 150         },
 151         {
 152                 .idcode         = 0x32443001,
 153                 .idmask         = 0xffffffff,
 154                 .map_io         = s3c2443_map_io,
 155                 .init_clocks    = s3c2443_init_clocks,
 156                 .init_uarts     = s3c2443_init_uarts,
 157                 .init           = s3c2443_init,
 158                 .name           = name_s3c2443,
 159         },
 160 };
 161
 162 /* minimal IO mapping */
 163
 164 static struct map_desc s3c_iodesc[] __initdata = {
 165         IODESC_ENT(GPIO),
 166         IODESC_ENT(IRQ),
 167         IODESC_ENT(MEMCTRL),
 168         IODESC_ENT(UART)
 169 };
 170
 171 /* read cpu identificaiton code */
 172
 173 static unsigned long s3c24xx_read_idcode_v5(void)
 174 {
 175 #if defined(CONFIG_CPU_S3C2416)
 176         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 177
 178         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 179
 180         /* test for s3c2416 or similar device */
 181         if ((gs >> 16) == 0x3245)
 182                 return gs;
 183 #endif
 184
 185 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 186         return __raw_readl(S3C2412_GSTATUS1);
 187 #else
 188         return 1UL;     /* don't look like an 2400 */
 189 #endif
 190 }
 191
 192 static unsigned long s3c24xx_read_idcode_v4(void)
 193 {
 194         return __raw_readl(S3C2410_GSTATUS1);
 195 }
 196
 197 static void s3c24xx_default_idle(void)
 198 {
 199         unsigned long tmp = 0;
 200         int i;
 201
 202         /* idle the system by using the idle mode which will wait for an
 203          * interrupt to happen before restarting the system.
 204          */
 205
 206         /* Warning: going into idle state upsets jtag scanning */
 207
 208         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 209                      S3C2410_CLKCON);
 210
 211         /* the samsung port seems to do a loop and then unset idle.. */
 212         for (i = 0; i < 50; i++)
 213                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 214
 215         /* this bit is not cleared on re-start... */
 216
 217         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 218                      S3C2410_CLKCON);
 219 }
 220
 221 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
 222         .bits           = 16,
 223         .div_base       = 1,
 224         .has_tint_cstat = false,
 225         .tclk_mask      = (1 << 4),
 226 };
 227
 228 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 229 {
 230         arm_pm_idle = s3c24xx_default_idle;
 231
 232         /* initialise the io descriptors we need for initialisation */
 233         iotable_init(mach_desc, size);
 234         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 235
 236         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 237                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 238         } else {
 239                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 240         }
 241         s3c24xx_init_cpu();
 242
 243         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 244
 245         samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
 246 }
 247
 248 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 249 {
 250         s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 251         s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 252 }
 253
 254 void __init samsung_timer_init(void)
 255 {
 256         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 257                 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
 258         };
 259
 260         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 261                                         timer_irqs, &s3c24xx_pwm_variant);
 262 }
 263
 264 /* Serial port registrations */
 265
 266 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 267 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 268 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
 269 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 270
 271 static struct resource s3c2410_uart0_resource[] = {
 272         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 273         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 274                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 275                         NULL, IORESOURCE_IRQ)
 276 };
 277
 278 static struct resource s3c2410_uart1_resource[] = {
 279         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 280         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 281                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 282                         NULL, IORESOURCE_IRQ)
 283 };
 284
 285 static struct resource s3c2410_uart2_resource[] = {
 286         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 287         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 288                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 289                         NULL, IORESOURCE_IRQ)
 290 };
 291
 292 static struct resource s3c2410_uart3_resource[] = {
 293         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 294         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 295                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 296                         NULL, IORESOURCE_IRQ)
 297 };
 298
 299 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 300         [0] = {
 301                 .resources      = s3c2410_uart0_resource,
 302                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 303         },
 304         [1] = {
 305                 .resources      = s3c2410_uart1_resource,
 306                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 307         },
 308         [2] = {
 309                 .resources      = s3c2410_uart2_resource,
 310                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 311         },
 312         [3] = {
 313                 .resources      = s3c2410_uart3_resource,
 314                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 315         },
 316 };
 317
 318 /* initialise all the clocks */
 319
 320 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
 321                                            unsigned long hclk,
 322                                            unsigned long pclk)
 323 {
 324         clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
 325                                         clk_xtal.rate);
 326
 327         clk_mpll.rate = fclk;
 328         clk_h.rate = hclk;
 329         clk_p.rate = pclk;
 330         clk_f.rate = fclk;
 331 }