x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-s3c64xx / common.c
blob73d79cf5e14118b1e99861c5bd79d6ffc9517164
1 /*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * Common Codes for S3C64XX machines
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
24 #include <linux/reboot.h>
25 #include <linux/io.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
29 #include <linux/irqchip/arm-vic.h>
30 #include <clocksource/samsung_pwm.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/system_misc.h>
36 #include <mach/map.h>
37 #include <mach/hardware.h>
38 #include <mach/regs-gpio.h>
40 #include <plat/cpu.h>
41 #include <plat/clock.h>
42 #include <plat/devs.h>
43 #include <plat/pm.h>
44 #include <plat/gpio-cfg.h>
45 #include <plat/irq-uart.h>
46 #include <plat/pwm-core.h>
47 #include <plat/regs-irqtype.h>
48 #include <plat/regs-serial.h>
49 #include <plat/watchdog-reset.h>
51 #include "common.h"
53 /* uart registration process */
55 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
57 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
60 /* table of supported CPUs */
62 static const char name_s3c6400[] = "S3C6400";
63 static const char name_s3c6410[] = "S3C6410";
65 static struct cpu_table cpu_ids[] __initdata = {
67 .idcode = S3C6400_CPU_ID,
68 .idmask = S3C64XX_CPU_MASK,
69 .map_io = s3c6400_map_io,
70 .init_clocks = s3c6400_init_clocks,
71 .init_uarts = s3c64xx_init_uarts,
72 .init = s3c6400_init,
73 .name = name_s3c6400,
74 }, {
75 .idcode = S3C6410_CPU_ID,
76 .idmask = S3C64XX_CPU_MASK,
77 .map_io = s3c6410_map_io,
78 .init_clocks = s3c6410_init_clocks,
79 .init_uarts = s3c64xx_init_uarts,
80 .init = s3c6410_init,
81 .name = name_s3c6410,
85 /* minimal IO mapping */
87 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
88 #define UART_OFFS (S3C_PA_UART & 0xfffff)
90 static struct map_desc s3c_iodesc[] __initdata = {
92 .virtual = (unsigned long)S3C_VA_SYS,
93 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
94 .length = SZ_4K,
95 .type = MT_DEVICE,
96 }, {
97 .virtual = (unsigned long)S3C_VA_MEM,
98 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
99 .length = SZ_4K,
100 .type = MT_DEVICE,
101 }, {
102 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
103 .pfn = __phys_to_pfn(S3C_PA_UART),
104 .length = SZ_4K,
105 .type = MT_DEVICE,
106 }, {
107 .virtual = (unsigned long)VA_VIC0,
108 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
109 .length = SZ_16K,
110 .type = MT_DEVICE,
111 }, {
112 .virtual = (unsigned long)VA_VIC1,
113 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
114 .length = SZ_16K,
115 .type = MT_DEVICE,
116 }, {
117 .virtual = (unsigned long)S3C_VA_TIMER,
118 .pfn = __phys_to_pfn(S3C_PA_TIMER),
119 .length = SZ_16K,
120 .type = MT_DEVICE,
121 }, {
122 .virtual = (unsigned long)S3C64XX_VA_GPIO,
123 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
124 .length = SZ_4K,
125 .type = MT_DEVICE,
126 }, {
127 .virtual = (unsigned long)S3C64XX_VA_MODEM,
128 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
129 .length = SZ_4K,
130 .type = MT_DEVICE,
131 }, {
132 .virtual = (unsigned long)S3C_VA_WATCHDOG,
133 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
134 .length = SZ_4K,
135 .type = MT_DEVICE,
136 }, {
137 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
138 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
139 .length = SZ_1K,
140 .type = MT_DEVICE,
144 static struct bus_type s3c64xx_subsys = {
145 .name = "s3c64xx-core",
146 .dev_name = "s3c64xx-core",
149 static struct device s3c64xx_dev = {
150 .bus = &s3c64xx_subsys,
153 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
154 .bits = 32,
155 .div_base = 0,
156 .has_tint_cstat = true,
157 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
160 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
162 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
163 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
166 void __init samsung_timer_init(void)
168 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
169 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
170 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
173 samsung_pwm_clocksource_init(S3C_VA_TIMER,
174 timer_irqs, &s3c64xx_pwm_variant);
177 /* read cpu identification code */
179 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
181 /* initialise the io descriptors we need for initialisation */
182 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
183 iotable_init(mach_desc, size);
185 /* detect cpu id */
186 s3c64xx_init_cpu();
188 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
190 samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
193 static __init int s3c64xx_dev_init(void)
195 subsys_system_register(&s3c64xx_subsys, NULL);
196 return device_register(&s3c64xx_dev);
198 core_initcall(s3c64xx_dev_init);
201 * setup the sources the vic should advertise resume
202 * for, even though it is not doing the wake
203 * (set_irq_wake needs to be valid)
205 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
206 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
207 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
208 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
209 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
210 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
212 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
215 * FIXME: there is no better place to put this at the moment
216 * (samsung_wdt_reset_init needs clocks)
218 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
220 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
222 /* initialise the pair of VICs */
223 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
224 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
227 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
228 #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
230 static inline void s3c_irq_eint_mask(struct irq_data *data)
232 u32 mask;
234 mask = __raw_readl(S3C64XX_EINT0MASK);
235 mask |= (u32)data->chip_data;
236 __raw_writel(mask, S3C64XX_EINT0MASK);
239 static void s3c_irq_eint_unmask(struct irq_data *data)
241 u32 mask;
243 mask = __raw_readl(S3C64XX_EINT0MASK);
244 mask &= ~((u32)data->chip_data);
245 __raw_writel(mask, S3C64XX_EINT0MASK);
248 static inline void s3c_irq_eint_ack(struct irq_data *data)
250 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
253 static void s3c_irq_eint_maskack(struct irq_data *data)
255 /* compiler should in-line these */
256 s3c_irq_eint_mask(data);
257 s3c_irq_eint_ack(data);
260 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
262 int offs = eint_offset(data->irq);
263 int pin, pin_val;
264 int shift;
265 u32 ctrl, mask;
266 u32 newvalue = 0;
267 void __iomem *reg;
269 if (offs > 27)
270 return -EINVAL;
272 if (offs <= 15)
273 reg = S3C64XX_EINT0CON0;
274 else
275 reg = S3C64XX_EINT0CON1;
277 switch (type) {
278 case IRQ_TYPE_NONE:
279 printk(KERN_WARNING "No edge setting!\n");
280 break;
282 case IRQ_TYPE_EDGE_RISING:
283 newvalue = S3C2410_EXTINT_RISEEDGE;
284 break;
286 case IRQ_TYPE_EDGE_FALLING:
287 newvalue = S3C2410_EXTINT_FALLEDGE;
288 break;
290 case IRQ_TYPE_EDGE_BOTH:
291 newvalue = S3C2410_EXTINT_BOTHEDGE;
292 break;
294 case IRQ_TYPE_LEVEL_LOW:
295 newvalue = S3C2410_EXTINT_LOWLEV;
296 break;
298 case IRQ_TYPE_LEVEL_HIGH:
299 newvalue = S3C2410_EXTINT_HILEV;
300 break;
302 default:
303 printk(KERN_ERR "No such irq type %d", type);
304 return -1;
307 if (offs <= 15)
308 shift = (offs / 2) * 4;
309 else
310 shift = ((offs - 16) / 2) * 4;
311 mask = 0x7 << shift;
313 ctrl = __raw_readl(reg);
314 ctrl &= ~mask;
315 ctrl |= newvalue << shift;
316 __raw_writel(ctrl, reg);
318 /* set the GPIO pin appropriately */
320 if (offs < 16) {
321 pin = S3C64XX_GPN(offs);
322 pin_val = S3C_GPIO_SFN(2);
323 } else if (offs < 23) {
324 pin = S3C64XX_GPL(offs + 8 - 16);
325 pin_val = S3C_GPIO_SFN(3);
326 } else {
327 pin = S3C64XX_GPM(offs - 23);
328 pin_val = S3C_GPIO_SFN(3);
331 s3c_gpio_cfgpin(pin, pin_val);
333 return 0;
336 static struct irq_chip s3c_irq_eint = {
337 .name = "s3c-eint",
338 .irq_mask = s3c_irq_eint_mask,
339 .irq_unmask = s3c_irq_eint_unmask,
340 .irq_mask_ack = s3c_irq_eint_maskack,
341 .irq_ack = s3c_irq_eint_ack,
342 .irq_set_type = s3c_irq_eint_set_type,
343 .irq_set_wake = s3c_irqext_wake,
346 /* s3c_irq_demux_eint
348 * This function demuxes the IRQ from the group0 external interrupts,
349 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
350 * the specific handlers s3c_irq_demux_eintX_Y.
352 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
354 u32 status = __raw_readl(S3C64XX_EINT0PEND);
355 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
356 unsigned int irq;
358 status &= ~mask;
359 status >>= start;
360 status &= (1 << (end - start + 1)) - 1;
362 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
363 if (status & 1)
364 generic_handle_irq(irq);
366 status >>= 1;
370 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
372 s3c_irq_demux_eint(0, 3);
375 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
377 s3c_irq_demux_eint(4, 11);
380 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
382 s3c_irq_demux_eint(12, 19);
385 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
387 s3c_irq_demux_eint(20, 27);
390 static int __init s3c64xx_init_irq_eint(void)
392 int irq;
394 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
395 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
396 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
397 set_irq_flags(irq, IRQF_VALID);
400 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
401 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
402 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
403 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
405 return 0;
407 arch_initcall(s3c64xx_init_irq_eint);
409 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
411 if (mode != REBOOT_SOFT)
412 samsung_wdt_reset();
414 /* if all else fails, or mode was for soft, jump to 0 */
415 soft_restart(0);
418 void __init s3c64xx_init_late(void)
420 s3c64xx_pm_late_initcall();