2 * r8a73a4 clock framework support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/clock.h>
26 #include <mach/common.h>
28 #define CPG_BASE 0xe6150000
31 #define SMSTPCR2 0xe6150138
32 #define SMSTPCR3 0xe615013c
33 #define SMSTPCR4 0xe6150140
34 #define SMSTPCR5 0xe6150144
36 #define FRQCRA 0xE6150000
37 #define FRQCRB 0xE6150004
38 #define FRQCRC 0xE61500E0
39 #define VCLKCR1 0xE6150008
40 #define VCLKCR2 0xE615000C
41 #define VCLKCR3 0xE615001C
42 #define VCLKCR4 0xE6150014
43 #define VCLKCR5 0xE6150034
44 #define ZBCKCR 0xE6150010
45 #define SD0CKCR 0xE6150074
46 #define SD1CKCR 0xE6150078
47 #define SD2CKCR 0xE615007C
48 #define MMC0CKCR 0xE6150240
49 #define MMC1CKCR 0xE6150244
50 #define FSIACKCR 0xE6150018
51 #define FSIBCKCR 0xE6150090
52 #define MPCKCR 0xe6150080
53 #define SPUVCKCR 0xE6150094
54 #define HSICKCR 0xE615026C
55 #define M4CKCR 0xE6150098
56 #define PLLECR 0xE61500D0
57 #define PLL0CR 0xE61500D8
58 #define PLL1CR 0xE6150028
59 #define PLL2CR 0xE615002C
60 #define PLL2SCR 0xE61501F4
61 #define PLL2HCR 0xE61501E4
62 #define CKSCR 0xE61500C0
64 #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
66 static struct clk_mapping cpg_mapping
= {
71 static struct clk extalr_clk
= {
73 .mapping
= &cpg_mapping
,
76 static struct clk extal1_clk
= {
78 .mapping
= &cpg_mapping
,
81 static struct clk extal2_clk
= {
83 .mapping
= &cpg_mapping
,
86 static struct sh_clk_ops followparent_clk_ops
= {
87 .recalc
= followparent_recalc
,
90 static struct clk main_clk
= {
91 /* .parent will be set r8a73a4_clock_init */
92 .ops
= &followparent_clk_ops
,
95 SH_CLK_RATIO(div2
, 1, 2);
96 SH_CLK_RATIO(div4
, 1, 4);
98 SH_FIXED_RATIO_CLK(main_div2_clk
, main_clk
, div2
);
99 SH_FIXED_RATIO_CLK(extal1_div2_clk
, extal1_clk
, div2
);
100 SH_FIXED_RATIO_CLK(extal2_div2_clk
, extal2_clk
, div2
);
101 SH_FIXED_RATIO_CLK(extal2_div4_clk
, extal2_clk
, div4
);
103 /* External FSIACK/FSIBCK clock */
104 static struct clk fsiack_clk
= {
107 static struct clk fsibck_clk
= {
113 static struct clk
*pll_parent_main
[] = {
118 static struct clk
*pll_parent_main_extal
[8] = {
119 [0] = &main_div2_clk
,
120 [1] = &extal2_div2_clk
,
121 [3] = &extal2_div4_clk
,
126 static unsigned long pll_recalc(struct clk
*clk
)
128 unsigned long mult
= 1;
130 if (ioread32(CPG_MAP(PLLECR
)) & (1 << clk
->enable_bit
))
131 mult
= (((ioread32(clk
->mapped_reg
) >> 24) & 0x7f) + 1);
133 return clk
->parent
->rate
* mult
;
136 static int pll_set_parent(struct clk
*clk
, struct clk
*parent
)
141 if (!clk
->parent_table
|| !clk
->parent_num
)
144 /* Search the parent */
145 for (i
= 0; i
< clk
->parent_num
; i
++)
146 if (clk
->parent_table
[i
] == parent
)
149 if (i
== clk
->parent_num
)
152 ret
= clk_reparent(clk
, parent
);
156 val
= ioread32(clk
->mapped_reg
) &
157 ~(((1 << clk
->src_width
) - 1) << clk
->src_shift
);
159 iowrite32(val
| i
<< clk
->src_shift
, clk
->mapped_reg
);
164 static struct sh_clk_ops pll_clk_ops
= {
165 .recalc
= pll_recalc
,
166 .set_parent
= pll_set_parent
,
169 #define PLL_CLOCK(name, p, pt, w, s, reg, e) \
170 static struct clk name = { \
171 .ops = &pll_clk_ops, \
172 .flags = CLK_ENABLE_ON_INIT, \
174 .parent_table = pt, \
175 .parent_num = ARRAY_SIZE(pt), \
178 .enable_reg = (void __iomem *)reg, \
180 .mapping = &cpg_mapping, \
183 PLL_CLOCK(pll0_clk
, &main_clk
, pll_parent_main
, 1, 20, PLL0CR
, 0);
184 PLL_CLOCK(pll1_clk
, &main_clk
, pll_parent_main
, 1, 7, PLL1CR
, 1);
185 PLL_CLOCK(pll2_clk
, &main_div2_clk
, pll_parent_main_extal
, 3, 5, PLL2CR
, 2);
186 PLL_CLOCK(pll2s_clk
, &main_div2_clk
, pll_parent_main_extal
, 3, 5, PLL2SCR
, 4);
187 PLL_CLOCK(pll2h_clk
, &main_div2_clk
, pll_parent_main_extal
, 3, 5, PLL2HCR
, 5);
189 SH_FIXED_RATIO_CLK(pll1_div2_clk
, pll1_clk
, div2
);
191 static atomic_t frqcr_lock
;
193 /* Several clocks need to access FRQCRB, have to lock */
194 static bool frqcr_kick_check(struct clk
*clk
)
196 return !(ioread32(CPG_MAP(FRQCRB
)) & BIT(31));
199 static int frqcr_kick_do(struct clk
*clk
)
203 /* set KICK bit in FRQCRB to update hardware setting, check success */
204 iowrite32(ioread32(CPG_MAP(FRQCRB
)) | BIT(31), CPG_MAP(FRQCRB
));
205 for (i
= 1000; i
; i
--)
206 if (ioread32(CPG_MAP(FRQCRB
)) & BIT(31))
214 static int zclk_set_rate(struct clk
*clk
, unsigned long rate
)
216 void __iomem
*frqcrc
;
218 unsigned long step
, p_rate
;
221 if (!clk
->parent
|| !__clk_get(clk
->parent
))
224 if (!atomic_inc_and_test(&frqcr_lock
) || !frqcr_kick_check(clk
)) {
230 * Users are supposed to first call clk_set_rate() only with
231 * clk_round_rate() results. So, we don't fix wrong rates here, but
232 * guard against them anyway
235 p_rate
= clk_get_rate(clk
->parent
);
236 if (rate
== p_rate
) {
239 step
= DIV_ROUND_CLOSEST(p_rate
, 32);
241 if (rate
> p_rate
|| rate
< step
) {
246 val
= 32 - rate
/ step
;
249 frqcrc
= clk
->mapped_reg
+ (FRQCRC
- (u32
)clk
->enable_reg
);
251 iowrite32((ioread32(frqcrc
) & ~(clk
->div_mask
<< clk
->enable_bit
)) |
252 (val
<< clk
->enable_bit
), frqcrc
);
254 ret
= frqcr_kick_do(clk
);
257 atomic_dec(&frqcr_lock
);
258 __clk_put(clk
->parent
);
262 static long zclk_round_rate(struct clk
*clk
, unsigned long rate
)
265 * theoretical rate = parent rate * multiplier / 32,
266 * where 1 <= multiplier <= 32. Therefore we should do
267 * multiplier = rate * 32 / parent rate
268 * rounded rate = parent rate * multiplier / 32.
269 * However, multiplication before division won't fit in 32 bits, so
270 * we sacrifice some precision by first dividing and then multiplying.
271 * To find the nearest divisor we calculate both and pick up the best
272 * one. This avoids 64-bit arithmetics.
274 unsigned long step
, mul_min
, mul_max
, rate_min
, rate_max
;
276 rate_max
= clk_get_rate(clk
->parent
);
278 /* output freq <= parent */
279 if (rate
>= rate_max
)
282 step
= DIV_ROUND_CLOSEST(rate_max
, 32);
283 /* output freq >= parent / 32 */
287 mul_min
= rate
/ step
;
288 mul_max
= DIV_ROUND_UP(rate
, step
);
289 rate_min
= step
* mul_min
;
290 if (mul_max
== mul_min
)
293 rate_max
= step
* mul_max
;
295 if (rate_max
- rate
< rate
- rate_min
)
301 static unsigned long zclk_recalc(struct clk
*clk
)
303 void __iomem
*frqcrc
= FRQCRC
- (u32
)clk
->enable_reg
+ clk
->mapped_reg
;
304 unsigned int max
= clk
->div_mask
+ 1;
305 unsigned long val
= ((ioread32(frqcrc
) >> clk
->enable_bit
) &
308 return DIV_ROUND_CLOSEST(clk_get_rate(clk
->parent
), max
) *
312 static struct sh_clk_ops zclk_ops
= {
313 .recalc
= zclk_recalc
,
314 .set_rate
= zclk_set_rate
,
315 .round_rate
= zclk_round_rate
,
318 static struct clk z_clk
= {
322 /* We'll need to access FRQCRB and FRQCRC */
323 .enable_reg
= (void __iomem
*)FRQCRB
,
328 * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
329 * switching is only available in auto-DVFS mode
331 SH_FIXED_RATIO_CLK(pll0_div2_clk
, pll0_clk
, div2
);
333 static struct clk z2_clk
= {
334 .parent
= &pll0_div2_clk
,
337 /* We'll need to access FRQCRB and FRQCRC */
338 .enable_reg
= (void __iomem
*)FRQCRB
,
342 static struct clk
*main_clks
[] = {
365 static void div4_kick(struct clk
*clk
)
367 if (!WARN(!atomic_inc_and_test(&frqcr_lock
), "FRQCR* lock broken!\n"))
369 atomic_dec(&frqcr_lock
);
372 static int divisors
[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
374 static struct clk_div_mult_table div4_div_mult_table
= {
375 .divisors
= divisors
,
376 .nr_divisors
= ARRAY_SIZE(divisors
),
379 static struct clk_div4_table div4_table
= {
380 .div_mult_table
= &div4_div_mult_table
,
385 DIV4_I
, DIV4_M3
, DIV4_B
, DIV4_M1
, DIV4_M2
,
386 DIV4_ZX
, DIV4_ZS
, DIV4_HP
,
389 static struct clk div4_clks
[DIV4_NR
] = {
390 [DIV4_I
] = SH_CLK_DIV4(&pll1_clk
, FRQCRA
, 20, 0x0dff, CLK_ENABLE_ON_INIT
),
391 [DIV4_M3
] = SH_CLK_DIV4(&pll1_clk
, FRQCRA
, 12, 0x1dff, CLK_ENABLE_ON_INIT
),
392 [DIV4_B
] = SH_CLK_DIV4(&pll1_clk
, FRQCRA
, 8, 0x0dff, CLK_ENABLE_ON_INIT
),
393 [DIV4_M1
] = SH_CLK_DIV4(&pll1_clk
, FRQCRA
, 4, 0x1dff, 0),
394 [DIV4_M2
] = SH_CLK_DIV4(&pll1_clk
, FRQCRA
, 0, 0x1dff, 0),
395 [DIV4_ZX
] = SH_CLK_DIV4(&pll1_clk
, FRQCRB
, 12, 0x0dff, 0),
396 [DIV4_ZS
] = SH_CLK_DIV4(&pll1_clk
, FRQCRB
, 8, 0x0dff, 0),
397 [DIV4_HP
] = SH_CLK_DIV4(&pll1_clk
, FRQCRB
, 4, 0x0dff, 0),
402 DIV6_SDHI0
, DIV6_SDHI1
, DIV6_SDHI2
,
403 DIV6_MMC0
, DIV6_MMC1
,
404 DIV6_VCK1
, DIV6_VCK2
, DIV6_VCK3
, DIV6_VCK4
, DIV6_VCK5
,
405 DIV6_FSIA
, DIV6_FSIB
,
406 DIV6_MP
, DIV6_M4
, DIV6_HSI
, DIV6_SPUV
,
409 static struct clk
*div6_parents
[8] = {
410 [0] = &pll1_div2_clk
,
413 [4] = &main_div2_clk
,
417 static struct clk
*fsia_parents
[4] = {
418 [0] = &pll1_div2_clk
,
423 static struct clk
*fsib_parents
[4] = {
424 [0] = &pll1_div2_clk
,
429 static struct clk
*mp_parents
[4] = {
430 [0] = &pll1_div2_clk
,
436 static struct clk
*m4_parents
[2] = {
440 static struct clk
*hsi_parents
[4] = {
442 [1] = &pll1_div2_clk
,
447 * SH_CLK_DIV6_EXT() macro doesn't care .mapping
448 * but, it is necessary on R-Car (= ioremap() base CPG)
449 * The difference between
450 * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
453 #define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
454 _num_parents, _src_shift, _src_width) \
456 .enable_reg = (void __iomem *)_reg, \
457 .enable_bit = 0, /* unused */ \
458 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
459 .div_mask = SH_CLK_DIV6_MSK, \
460 .parent_table = _parents, \
461 .parent_num = _num_parents, \
462 .src_shift = _src_shift, \
463 .src_width = _src_width, \
464 .mapping = &cpg_mapping, \
467 static struct clk div6_clks
[DIV6_NR
] = {
468 [DIV6_ZB
] = SH_CLK_MAP_DIV6_EXT(ZBCKCR
, CLK_ENABLE_ON_INIT
,
469 div6_parents
, 2, 7, 1),
470 [DIV6_SDHI0
] = SH_CLK_MAP_DIV6_EXT(SD0CKCR
, 0,
471 div6_parents
, 2, 6, 2),
472 [DIV6_SDHI1
] = SH_CLK_MAP_DIV6_EXT(SD1CKCR
, 0,
473 div6_parents
, 2, 6, 2),
474 [DIV6_SDHI2
] = SH_CLK_MAP_DIV6_EXT(SD2CKCR
, 0,
475 div6_parents
, 2, 6, 2),
476 [DIV6_MMC0
] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR
, 0,
477 div6_parents
, 2, 6, 2),
478 [DIV6_MMC1
] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR
, 0,
479 div6_parents
, 2, 6, 2),
480 [DIV6_VCK1
] = SH_CLK_MAP_DIV6_EXT(VCLKCR1
, 0, /* didn't care bit[6-7] */
481 div6_parents
, ARRAY_SIZE(div6_parents
), 12, 3),
482 [DIV6_VCK2
] = SH_CLK_MAP_DIV6_EXT(VCLKCR2
, 0, /* didn't care bit[6-7] */
483 div6_parents
, ARRAY_SIZE(div6_parents
), 12, 3),
484 [DIV6_VCK3
] = SH_CLK_MAP_DIV6_EXT(VCLKCR3
, 0, /* didn't care bit[6-7] */
485 div6_parents
, ARRAY_SIZE(div6_parents
), 12, 3),
486 [DIV6_VCK4
] = SH_CLK_MAP_DIV6_EXT(VCLKCR4
, 0, /* didn't care bit[6-7] */
487 div6_parents
, ARRAY_SIZE(div6_parents
), 12, 3),
488 [DIV6_VCK5
] = SH_CLK_MAP_DIV6_EXT(VCLKCR5
, 0, /* didn't care bit[6-7] */
489 div6_parents
, ARRAY_SIZE(div6_parents
), 12, 3),
490 [DIV6_FSIA
] = SH_CLK_MAP_DIV6_EXT(FSIACKCR
, 0,
491 fsia_parents
, ARRAY_SIZE(fsia_parents
), 6, 2),
492 [DIV6_FSIB
] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR
, 0,
493 fsib_parents
, ARRAY_SIZE(fsib_parents
), 6, 2),
494 [DIV6_MP
] = SH_CLK_MAP_DIV6_EXT(MPCKCR
, 0, /* it needs bit[9-11] control */
495 mp_parents
, ARRAY_SIZE(mp_parents
), 6, 2),
496 /* pll2s will be selected always for M4 */
497 [DIV6_M4
] = SH_CLK_MAP_DIV6_EXT(M4CKCR
, 0, /* it needs bit[9] control */
498 m4_parents
, ARRAY_SIZE(m4_parents
), 6, 1),
499 [DIV6_HSI
] = SH_CLK_MAP_DIV6_EXT(HSICKCR
, 0, /* it needs bit[9] control */
500 hsi_parents
, ARRAY_SIZE(hsi_parents
), 6, 2),
501 [DIV6_SPUV
] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR
, 0,
502 mp_parents
, ARRAY_SIZE(mp_parents
), 6, 2),
507 MSTP217
, MSTP216
, MSTP207
, MSTP206
, MSTP204
, MSTP203
,
508 MSTP329
, MSTP323
, MSTP318
, MSTP317
, MSTP316
,
509 MSTP315
, MSTP314
, MSTP313
, MSTP312
, MSTP305
, MSTP300
,
510 MSTP411
, MSTP410
, MSTP409
,
515 static struct clk mstp_clks
[MSTP_NR
] = {
516 [MSTP204
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 4, 0), /* SCIFA0 */
517 [MSTP203
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 3, 0), /* SCIFA1 */
518 [MSTP206
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 6, 0), /* SCIFB0 */
519 [MSTP207
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 7, 0), /* SCIFB1 */
520 [MSTP216
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 16, 0), /* SCIFB2 */
521 [MSTP217
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MP
], SMSTPCR2
, 17, 0), /* SCIFB3 */
522 [MSTP300
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR3
, 0, 0), /* IIC2 */
523 [MSTP305
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MMC1
],SMSTPCR3
, 5, 0), /* MMCIF1 */
524 [MSTP312
] = SH_CLK_MSTP32(&div6_clks
[DIV6_SDHI2
],SMSTPCR3
, 12, 0), /* SDHI2 */
525 [MSTP313
] = SH_CLK_MSTP32(&div6_clks
[DIV6_SDHI1
],SMSTPCR3
, 13, 0), /* SDHI1 */
526 [MSTP314
] = SH_CLK_MSTP32(&div6_clks
[DIV6_SDHI0
],SMSTPCR3
, 14, 0), /* SDHI0 */
527 [MSTP315
] = SH_CLK_MSTP32(&div6_clks
[DIV6_MMC0
],SMSTPCR3
, 15, 0), /* MMCIF0 */
528 [MSTP316
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR3
, 16, 0), /* IIC6 */
529 [MSTP317
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR3
, 17, 0), /* IIC7 */
530 [MSTP318
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR3
, 18, 0), /* IIC0 */
531 [MSTP323
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR3
, 23, 0), /* IIC1 */
532 [MSTP329
] = SH_CLK_MSTP32(&extalr_clk
, SMSTPCR3
, 29, 0), /* CMT10 */
533 [MSTP409
] = SH_CLK_MSTP32(&main_div2_clk
, SMSTPCR4
, 9, 0), /* IIC5 */
534 [MSTP410
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR4
, 10, 0), /* IIC4 */
535 [MSTP411
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR4
, 11, 0), /* IIC3 */
536 [MSTP522
] = SH_CLK_MSTP32(&extal2_clk
, SMSTPCR5
, 22, 0), /* Thermal */
537 [MSTP515
] = SH_CLK_MSTP32(&div4_clks
[DIV4_HP
], SMSTPCR5
, 15, 0), /* IIC8 */
540 static struct clk_lookup lookups
[] = {
542 CLKDEV_CON_ID("extal1", &extal1_clk
),
543 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk
),
544 CLKDEV_CON_ID("extal2", &extal2_clk
),
545 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk
),
546 CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk
),
547 CLKDEV_CON_ID("fsiack", &fsiack_clk
),
548 CLKDEV_CON_ID("fsibck", &fsibck_clk
),
551 CLKDEV_CON_ID("pll1", &pll1_clk
),
552 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk
),
553 CLKDEV_CON_ID("pll2", &pll2_clk
),
554 CLKDEV_CON_ID("pll2s", &pll2s_clk
),
555 CLKDEV_CON_ID("pll2h", &pll2h_clk
),
558 CLKDEV_DEV_ID("cpu0", &z_clk
),
561 CLKDEV_CON_ID("zb", &div6_clks
[DIV6_ZB
]),
562 CLKDEV_CON_ID("vck1", &div6_clks
[DIV6_VCK1
]),
563 CLKDEV_CON_ID("vck2", &div6_clks
[DIV6_VCK2
]),
564 CLKDEV_CON_ID("vck3", &div6_clks
[DIV6_VCK3
]),
565 CLKDEV_CON_ID("vck4", &div6_clks
[DIV6_VCK4
]),
566 CLKDEV_CON_ID("vck5", &div6_clks
[DIV6_VCK5
]),
567 CLKDEV_CON_ID("fsia", &div6_clks
[DIV6_FSIA
]),
568 CLKDEV_CON_ID("fsib", &div6_clks
[DIV6_FSIB
]),
569 CLKDEV_CON_ID("mp", &div6_clks
[DIV6_MP
]),
570 CLKDEV_CON_ID("m4", &div6_clks
[DIV6_M4
]),
571 CLKDEV_CON_ID("hsi", &div6_clks
[DIV6_HSI
]),
572 CLKDEV_CON_ID("spuv", &div6_clks
[DIV6_SPUV
]),
575 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks
[MSTP204
]),
576 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks
[MSTP203
]),
577 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks
[MSTP206
]),
578 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks
[MSTP207
]),
579 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks
[MSTP216
]),
580 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks
[MSTP217
]),
581 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks
[MSTP522
]),
582 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks
[MSTP300
]),
583 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks
[MSTP305
]),
584 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks
[MSTP305
]),
585 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks
[MSTP312
]),
586 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks
[MSTP312
]),
587 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks
[MSTP313
]),
588 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks
[MSTP313
]),
589 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks
[MSTP314
]),
590 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks
[MSTP314
]),
591 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks
[MSTP315
]),
592 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks
[MSTP315
]),
593 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks
[MSTP316
]),
594 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks
[MSTP317
]),
595 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks
[MSTP318
]),
596 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks
[MSTP323
]),
597 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks
[MSTP329
]),
598 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks
[MSTP409
]),
599 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks
[MSTP410
]),
600 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks
[MSTP411
]),
601 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks
[MSTP515
]),
604 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks
[MSTP522
]),
607 void __init
r8a73a4_clock_init(void)
613 atomic_set(&frqcr_lock
, -1);
615 reg
= ioremap_nocache(CKSCR
, PAGE_SIZE
);
617 ckscr
= ioread32(reg
);
620 switch ((ckscr
>> 28) & 0x3) {
622 main_clk
.parent
= &extal1_clk
;
625 main_clk
.parent
= &extal1_div2_clk
;
628 main_clk
.parent
= &extal2_clk
;
631 main_clk
.parent
= &extal2_div2_clk
;
635 for (k
= 0; !ret
&& (k
< ARRAY_SIZE(main_clks
)); k
++)
636 ret
= clk_register(main_clks
[k
]);
639 ret
= sh_clk_div4_register(div4_clks
, DIV4_NR
, &div4_table
);
642 ret
= sh_clk_div6_reparent_register(div6_clks
, DIV6_NR
);
645 ret
= sh_clk_mstp_register(mstp_clks
, MSTP_NR
);
647 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
652 panic("failed to setup r8a73a4 clocks\n");