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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-shmobile / clock-r8a7790.c
blobfc36d3db0b4d9541d9b8ca08c47b4530a8891c29
1 /*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/clock.h>
26 #include <mach/common.h>
27 #include <mach/r8a7790.h>
28
29 /*
30 * MD EXTAL PLL0 PLL1 PLL3
31 * 14 13 19 (MHz) *1 *1
32 *---------------------------------------------------
33 * 0 0 0 15 x 1 x172/2 x208/2 x106
34 * 0 0 1 15 x 1 x172/2 x208/2 x88
35 * 0 1 0 20 x 1 x130/2 x156/2 x80
36 * 0 1 1 20 x 1 x130/2 x156/2 x66
37 * 1 0 0 26 / 2 x200/2 x240/2 x122
38 * 1 0 1 26 / 2 x200/2 x240/2 x102
39 * 1 1 0 30 / 2 x172/2 x208/2 x106
40 * 1 1 1 30 / 2 x172/2 x208/2 x88
41 *
42 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
44 */
45
46 #define CPG_BASE 0xe6150000
47 #define CPG_LEN 0x1000
48
49 #define SMSTPCR1 0xe6150134
50 #define SMSTPCR2 0xe6150138
51 #define SMSTPCR3 0xe615013c
52 #define SMSTPCR5 0xe6150144
53 #define SMSTPCR7 0xe615014c
54 #define SMSTPCR8 0xe6150990
55
56 #define SDCKCR 0xE6150074
57 #define SD2CKCR 0xE6150078
58 #define SD3CKCR 0xE615007C
59 #define MMC0CKCR 0xE6150240
60 #define MMC1CKCR 0xE6150244
61 #define SSPCKCR 0xE6150248
62 #define SSPRSCKCR 0xE615024C
63
64 static struct clk_mapping cpg_mapping = {
65 .phys = CPG_BASE,
66 .len = CPG_LEN,
67 };
68
69 static struct clk extal_clk = {
70 /* .rate will be updated on r8a7790_clock_init() */
71 .mapping = &cpg_mapping,
72 };
73
74 static struct sh_clk_ops followparent_clk_ops = {
75 .recalc = followparent_recalc,
76 };
77
78 static struct clk main_clk = {
79 /* .parent will be set r8a73a4_clock_init */
80 .ops = &followparent_clk_ops,
81 };
82
83 /*
84 * clock ratio of these clock will be updated
85 * on r8a7790_clock_init()
86 */
87 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
88 SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
89 SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
90 SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
91
92 /* fixed ratio clock */
93 SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
94 SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
95
96 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
97 SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
98 SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
99 SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
100 SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
101 SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
102 SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
103 SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104 SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
105 SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
106 SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
107 SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
108 SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
109
110 SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
111 SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
112 SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
113 SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
114
115 static struct clk *main_clks[] = {
116 &extal_clk,
117 &extal_div2_clk,
118 &main_clk,
119 &pll1_clk,
120 &pll1_div2_clk,
121 &pll3_clk,
122 &lb_clk,
123 &qspi_clk,
124 &zg_clk,
125 &zx_clk,
126 &zs_clk,
127 &hp_clk,
128 &i_clk,
129 &b_clk,
130 &p_clk,
131 &cl_clk,
132 &m2_clk,
133 &imp_clk,
134 &rclk_clk,
135 &oscclk_clk,
136 &zb3_clk,
137 &zb3d2_clk,
138 &ddr_clk,
139 &mp_clk,
140 &cp_clk,
141 };
142
143 /* SDHI (DIV4) clock */
144 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
145
146 static struct clk_div_mult_table div4_div_mult_table = {
147 .divisors = divisors,
148 .nr_divisors = ARRAY_SIZE(divisors),
149 };
150
151 static struct clk_div4_table div4_table = {
152 .div_mult_table = &div4_div_mult_table,
153 };
154
155 enum {
156 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
157 };
158
159 static struct clk div4_clks[DIV4_NR] = {
160 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
161 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
162 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
163 };
164
165 /* DIV6 clocks */
166 enum {
167 DIV6_SD2, DIV6_SD3,
168 DIV6_MMC0, DIV6_MMC1,
169 DIV6_SSP, DIV6_SSPRS,
170 DIV6_NR
171 };
172
173 static struct clk div6_clks[DIV6_NR] = {
174 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
175 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
176 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
177 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
178 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
179 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
180 };
181
182 /* MSTP */
183 enum {
184 MSTP813,
185 MSTP721, MSTP720,
186 MSTP717, MSTP716,
187 MSTP522,
188 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
189 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
190 MSTP124,
191 MSTP_NR
192 };
193
194 static struct clk mstp_clks[MSTP_NR] = {
195 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
196 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
197 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
198 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
199 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
200 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
201 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
202 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
203 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
204 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
205 [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
206 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
207 [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
208 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
209 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
210 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
211 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
212 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
213 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
214 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
215 };
216
217 static struct clk_lookup lookups[] = {
218
219 /* main clocks */
220 CLKDEV_CON_ID("extal", &extal_clk),
221 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
222 CLKDEV_CON_ID("main", &main_clk),
223 CLKDEV_CON_ID("pll1", &pll1_clk),
224 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
225 CLKDEV_CON_ID("pll3", &pll3_clk),
226 CLKDEV_CON_ID("zg", &zg_clk),
227 CLKDEV_CON_ID("zx", &zx_clk),
228 CLKDEV_CON_ID("zs", &zs_clk),
229 CLKDEV_CON_ID("hp", &hp_clk),
230 CLKDEV_CON_ID("i", &i_clk),
231 CLKDEV_CON_ID("b", &b_clk),
232 CLKDEV_CON_ID("lb", &lb_clk),
233 CLKDEV_CON_ID("p", &p_clk),
234 CLKDEV_CON_ID("cl", &cl_clk),
235 CLKDEV_CON_ID("m2", &m2_clk),
236 CLKDEV_CON_ID("imp", &imp_clk),
237 CLKDEV_CON_ID("rclk", &rclk_clk),
238 CLKDEV_CON_ID("oscclk", &oscclk_clk),
239 CLKDEV_CON_ID("zb3", &zb3_clk),
240 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
241 CLKDEV_CON_ID("ddr", &ddr_clk),
242 CLKDEV_CON_ID("mp", &mp_clk),
243 CLKDEV_CON_ID("qspi", &qspi_clk),
244 CLKDEV_CON_ID("cp", &cp_clk),
245
246 /* DIV4 */
247 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
248
249 /* DIV6 */
250 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
251 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
252
253 /* MSTP */
254 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
255 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
256 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
257 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
258 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
259 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
260 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
261 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
262 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
263 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
264 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
265 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
266 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
267 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
268 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
269 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
270 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
271 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
272 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
273 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
274 CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
275 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
276 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
277 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
278 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
279 };
280
281 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
282 extal_clk.rate = e * 1000 * 1000; \
283 main_clk.parent = m; \
284 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
285 if (mode & MD(19)) \
286 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
287 else \
288 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
289
290
291 void __init r8a7790_clock_init(void)
292 {
293 u32 mode = r8a7790_read_mode_pins();
294 int k, ret = 0;
295
296 switch (mode & (MD(14) | MD(13))) {
297 case 0:
298 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
299 break;
300 case MD(13):
301 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
302 break;
303 case MD(14):
304 R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
305 break;
306 case MD(13) | MD(14):
307 R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
308 break;
309 }
310
311 if (mode & (MD(18)))
312 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
313 else
314 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
315
316 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
317 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
318 else
319 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
320
321 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
322 ret = clk_register(main_clks[k]);
323
324 if (!ret)
325 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
326
327 if (!ret)
328 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
329
330 if (!ret)
331 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
332
333 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
334
335 if (!ret)
336 shmobile_clk_init();
337 else
338 panic("failed to setup r8a7790 clocks\n");
339 }
Linux with added FPC-III support