x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-shmobile / setup-r8a7790.c
blobd0f5c9f9349a186412da1f912fc9dbcac0e851d0
1 /*
2 * r8a7790 processor support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/clocksource.h>
22 #include <linux/irq.h>
23 #include <linux/kernel.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_data/gpio-rcar.h>
26 #include <linux/platform_data/irq-renesas-irqc.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_timer.h>
29 #include <mach/common.h>
30 #include <mach/irqs.h>
31 #include <mach/r8a7790.h>
32 #include <asm/mach/arch.h>
34 static struct resource pfc_resources[] __initdata = {
35 DEFINE_RES_MEM(0xe6060000, 0x250),
38 #define R8A7790_GPIO(idx) \
39 static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
40 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
41 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
42 }; \
44 static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
45 .gpio_base = 32 * (idx), \
46 .irq_base = 0, \
47 .number_of_pins = 32, \
48 .pctl_name = "pfc-r8a7790", \
49 .has_both_edge_trigger = 1, \
50 }; \
52 R8A7790_GPIO(0);
53 R8A7790_GPIO(1);
54 R8A7790_GPIO(2);
55 R8A7790_GPIO(3);
56 R8A7790_GPIO(4);
57 R8A7790_GPIO(5);
59 #define r8a7790_register_gpio(idx) \
60 platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
61 r8a7790_gpio##idx##_resources, \
62 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
63 &r8a7790_gpio##idx##_platform_data, \
64 sizeof(r8a7790_gpio##idx##_platform_data))
66 void __init r8a7790_pinmux_init(void)
68 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
69 ARRAY_SIZE(pfc_resources));
70 r8a7790_register_gpio(0);
71 r8a7790_register_gpio(1);
72 r8a7790_register_gpio(2);
73 r8a7790_register_gpio(3);
74 r8a7790_register_gpio(4);
75 r8a7790_register_gpio(5);
78 #define SCIF_COMMON(scif_type, baseaddr, irq) \
79 .type = scif_type, \
80 .mapbase = baseaddr, \
81 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
82 .irqs = SCIx_IRQ_MUXED(irq)
84 #define SCIFA_DATA(index, baseaddr, irq) \
85 [index] = { \
86 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
87 .scbrr_algo_id = SCBRR_ALGO_4, \
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
91 #define SCIFB_DATA(index, baseaddr, irq) \
92 [index] = { \
93 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
94 .scbrr_algo_id = SCBRR_ALGO_4, \
95 .scscr = SCSCR_RE | SCSCR_TE, \
98 #define SCIF_DATA(index, baseaddr, irq) \
99 [index] = { \
100 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
101 .scbrr_algo_id = SCBRR_ALGO_2, \
102 .scscr = SCSCR_RE | SCSCR_TE, \
105 #define HSCIF_DATA(index, baseaddr, irq) \
106 [index] = { \
107 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
108 .scbrr_algo_id = SCBRR_ALGO_6, \
109 .scscr = SCSCR_RE | SCSCR_TE, \
112 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
113 HSCIF0, HSCIF1 };
115 static struct plat_sci_port scif[] __initdata = {
116 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
117 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
118 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
119 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
120 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
121 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
122 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
123 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
124 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
125 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
128 static inline void r8a7790_register_scif(int idx)
130 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
131 sizeof(struct plat_sci_port));
134 static struct renesas_irqc_config irqc0_data __initdata = {
135 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
138 static struct resource irqc0_resources[] __initdata = {
139 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
140 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
141 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
142 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
143 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
146 #define r8a7790_register_irqc(idx) \
147 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
148 idx, irqc##idx##_resources, \
149 ARRAY_SIZE(irqc##idx##_resources), \
150 &irqc##idx##_data, \
151 sizeof(struct renesas_irqc_config))
153 static struct resource thermal_resources[] __initdata = {
154 DEFINE_RES_MEM(0xe61f0000, 0x14),
155 DEFINE_RES_MEM(0xe61f0100, 0x38),
156 DEFINE_RES_IRQ(gic_spi(69)),
159 #define r8a7790_register_thermal() \
160 platform_device_register_simple("rcar_thermal", -1, \
161 thermal_resources, \
162 ARRAY_SIZE(thermal_resources))
164 static struct sh_timer_config cmt00_platform_data __initdata = {
165 .name = "CMT00",
166 .timer_bit = 0,
167 .clockevent_rating = 80,
170 static struct resource cmt00_resources[] __initdata = {
171 DEFINE_RES_MEM(0xffca0510, 0x0c),
172 DEFINE_RES_MEM(0xffca0500, 0x04),
173 DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
176 #define r8a7790_register_cmt(idx) \
177 platform_device_register_resndata(&platform_bus, "sh_cmt", \
178 idx, cmt##idx##_resources, \
179 ARRAY_SIZE(cmt##idx##_resources), \
180 &cmt##idx##_platform_data, \
181 sizeof(struct sh_timer_config))
183 void __init r8a7790_add_dt_devices(void)
185 r8a7790_register_scif(SCIFA0);
186 r8a7790_register_scif(SCIFA1);
187 r8a7790_register_scif(SCIFB0);
188 r8a7790_register_scif(SCIFB1);
189 r8a7790_register_scif(SCIFB2);
190 r8a7790_register_scif(SCIFA2);
191 r8a7790_register_scif(SCIF0);
192 r8a7790_register_scif(SCIF1);
193 r8a7790_register_scif(HSCIF0);
194 r8a7790_register_scif(HSCIF1);
195 r8a7790_register_cmt(00);
198 void __init r8a7790_add_standard_devices(void)
200 r8a7790_add_dt_devices();
201 r8a7790_register_irqc(0);
202 r8a7790_register_thermal();
205 #define MODEMR 0xe6160060
207 u32 __init r8a7790_read_mode_pins(void)
209 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
210 u32 mode;
212 BUG_ON(!modemr);
213 mode = ioread32(modemr);
214 iounmap(modemr);
216 return mode;
219 #define CNTCR 0
220 #define CNTFID0 0x20
222 void __init r8a7790_timer_init(void)
224 #ifdef CONFIG_ARM_ARCH_TIMER
225 u32 mode = r8a7790_read_mode_pins();
226 void __iomem *base;
227 int extal_mhz = 0;
228 u32 freq;
230 /* At Linux boot time the r8a7790 arch timer comes up
231 * with the counter disabled. Moreover, it may also report
232 * a potentially incorrect fixed 13 MHz frequency. To be
233 * correct these registers need to be updated to use the
234 * frequency EXTAL / 2 which can be determined by the MD pins.
237 switch (mode & (MD(14) | MD(13))) {
238 case 0:
239 extal_mhz = 15;
240 break;
241 case MD(13):
242 extal_mhz = 20;
243 break;
244 case MD(14):
245 extal_mhz = 26;
246 break;
247 case MD(13) | MD(14):
248 extal_mhz = 30;
249 break;
252 /* The arch timer frequency equals EXTAL / 2 */
253 freq = extal_mhz * (1000000 / 2);
255 /* Remap "armgcnt address map" space */
256 base = ioremap(0xe6080000, PAGE_SIZE);
258 /* Update registers with correct frequency */
259 iowrite32(freq, base + CNTFID0);
260 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
262 /* make sure arch timer is started by setting bit 0 of CNTCR */
263 iowrite32(1, base + CNTCR);
264 iounmap(base);
265 #endif /* CONFIG_ARM_ARCH_TIMER */
267 clocksource_of_init();
270 void __init r8a7790_init_delay(void)
272 #ifndef CONFIG_ARM_ARCH_TIMER
273 shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
274 #endif
277 #ifdef CONFIG_USE_OF
279 static const char *r8a7790_boards_compat_dt[] __initdata = {
280 "renesas,r8a7790",
281 NULL,
284 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
285 .init_early = r8a7790_init_delay,
286 .init_time = r8a7790_timer_init,
287 .dt_compat = r8a7790_boards_compat_dt,
288 MACHINE_END
289 #endif /* CONFIG_USE_OF */