arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_data/sh_ipmmu.h>
  37 #include <mach/dma-register.h>
  38 #include <mach/irqs.h>
  39 #include <mach/sh7372.h>
  40 #include <mach/common.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45
  46 static struct map_desc sh7372_io_desc[] __initdata = {
  47         /* create a 1:1 entity map for 0xe6xxxxxx
  48          * used by CPGA, INTC and PFC.
  49          */
  50         {
  51                 .virtual        = 0xe6000000,
  52                 .pfn            = __phys_to_pfn(0xe6000000),
  53                 .length         = 256 << 20,
  54                 .type           = MT_DEVICE_NONSHARED
  55         },
  56 };
  57
  58 void __init sh7372_map_io(void)
  59 {
  60         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  61 }
  62
  63 /* PFC */
  64 static struct resource sh7372_pfc_resources[] = {
  65         [0] = {
  66                 .start  = 0xe6050000,
  67                 .end    = 0xe6057fff,
  68                 .flags  = IORESOURCE_MEM,
  69         },
  70         [1] = {
  71                 .start  = 0xe605800c,
  72                 .end    = 0xe6058027,
  73                 .flags  = IORESOURCE_MEM,
  74         }
  75 };
  76
  77 static struct platform_device sh7372_pfc_device = {
  78         .name           = "pfc-sh7372",
  79         .id             = -1,
  80         .resource       = sh7372_pfc_resources,
  81         .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
  82 };
  83
  84 void __init sh7372_pinmux_init(void)
  85 {
  86         platform_device_register(&sh7372_pfc_device);
  87 }
  88
  89 /* SCIFA0 */
  90 static struct plat_sci_port scif0_platform_data = {
  91         .mapbase        = 0xe6c40000,
  92         .flags          = UPF_BOOT_AUTOCONF,
  93         .scscr          = SCSCR_RE | SCSCR_TE,
  94         .scbrr_algo_id  = SCBRR_ALGO_4,
  95         .type           = PORT_SCIFA,
  96         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  97                             evt2irq(0x0c00), evt2irq(0x0c00) },
  98 };
  99
 100 static struct platform_device scif0_device = {
 101         .name           = "sh-sci",
 102         .id             = 0,
 103         .dev            = {
 104                 .platform_data  = &scif0_platform_data,
 105         },
 106 };
 107
 108 /* SCIFA1 */
 109 static struct plat_sci_port scif1_platform_data = {
 110         .mapbase        = 0xe6c50000,
 111         .flags          = UPF_BOOT_AUTOCONF,
 112         .scscr          = SCSCR_RE | SCSCR_TE,
 113         .scbrr_algo_id  = SCBRR_ALGO_4,
 114         .type           = PORT_SCIFA,
 115         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
 116                             evt2irq(0x0c20), evt2irq(0x0c20) },
 117 };
 118
 119 static struct platform_device scif1_device = {
 120         .name           = "sh-sci",
 121         .id             = 1,
 122         .dev            = {
 123                 .platform_data  = &scif1_platform_data,
 124         },
 125 };
 126
 127 /* SCIFA2 */
 128 static struct plat_sci_port scif2_platform_data = {
 129         .mapbase        = 0xe6c60000,
 130         .flags          = UPF_BOOT_AUTOCONF,
 131         .scscr          = SCSCR_RE | SCSCR_TE,
 132         .scbrr_algo_id  = SCBRR_ALGO_4,
 133         .type           = PORT_SCIFA,
 134         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 135                             evt2irq(0x0c40), evt2irq(0x0c40) },
 136 };
 137
 138 static struct platform_device scif2_device = {
 139         .name           = "sh-sci",
 140         .id             = 2,
 141         .dev            = {
 142                 .platform_data  = &scif2_platform_data,
 143         },
 144 };
 145
 146 /* SCIFA3 */
 147 static struct plat_sci_port scif3_platform_data = {
 148         .mapbase        = 0xe6c70000,
 149         .flags          = UPF_BOOT_AUTOCONF,
 150         .scscr          = SCSCR_RE | SCSCR_TE,
 151         .scbrr_algo_id  = SCBRR_ALGO_4,
 152         .type           = PORT_SCIFA,
 153         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 154                             evt2irq(0x0c60), evt2irq(0x0c60) },
 155 };
 156
 157 static struct platform_device scif3_device = {
 158         .name           = "sh-sci",
 159         .id             = 3,
 160         .dev            = {
 161                 .platform_data  = &scif3_platform_data,
 162         },
 163 };
 164
 165 /* SCIFA4 */
 166 static struct plat_sci_port scif4_platform_data = {
 167         .mapbase        = 0xe6c80000,
 168         .flags          = UPF_BOOT_AUTOCONF,
 169         .scscr          = SCSCR_RE | SCSCR_TE,
 170         .scbrr_algo_id  = SCBRR_ALGO_4,
 171         .type           = PORT_SCIFA,
 172         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 173                             evt2irq(0x0d20), evt2irq(0x0d20) },
 174 };
 175
 176 static struct platform_device scif4_device = {
 177         .name           = "sh-sci",
 178         .id             = 4,
 179         .dev            = {
 180                 .platform_data  = &scif4_platform_data,
 181         },
 182 };
 183
 184 /* SCIFA5 */
 185 static struct plat_sci_port scif5_platform_data = {
 186         .mapbase        = 0xe6cb0000,
 187         .flags          = UPF_BOOT_AUTOCONF,
 188         .scscr          = SCSCR_RE | SCSCR_TE,
 189         .scbrr_algo_id  = SCBRR_ALGO_4,
 190         .type           = PORT_SCIFA,
 191         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 192                             evt2irq(0x0d40), evt2irq(0x0d40) },
 193 };
 194
 195 static struct platform_device scif5_device = {
 196         .name           = "sh-sci",
 197         .id             = 5,
 198         .dev            = {
 199                 .platform_data  = &scif5_platform_data,
 200         },
 201 };
 202
 203 /* SCIFB */
 204 static struct plat_sci_port scif6_platform_data = {
 205         .mapbase        = 0xe6c30000,
 206         .flags          = UPF_BOOT_AUTOCONF,
 207         .scscr          = SCSCR_RE | SCSCR_TE,
 208         .scbrr_algo_id  = SCBRR_ALGO_4,
 209         .type           = PORT_SCIFB,
 210         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 211                             evt2irq(0x0d60), evt2irq(0x0d60) },
 212 };
 213
 214 static struct platform_device scif6_device = {
 215         .name           = "sh-sci",
 216         .id             = 6,
 217         .dev            = {
 218                 .platform_data  = &scif6_platform_data,
 219         },
 220 };
 221
 222 /* CMT */
 223 static struct sh_timer_config cmt2_platform_data = {
 224         .name = "CMT2",
 225         .channel_offset = 0x40,
 226         .timer_bit = 5,
 227         .clockevent_rating = 125,
 228         .clocksource_rating = 125,
 229 };
 230
 231 static struct resource cmt2_resources[] = {
 232         [0] = {
 233                 .name   = "CMT2",
 234                 .start  = 0xe6130040,
 235                 .end    = 0xe613004b,
 236                 .flags  = IORESOURCE_MEM,
 237         },
 238         [1] = {
 239                 .start  = evt2irq(0x0b80), /* CMT2 */
 240                 .flags  = IORESOURCE_IRQ,
 241         },
 242 };
 243
 244 static struct platform_device cmt2_device = {
 245         .name           = "sh_cmt",
 246         .id             = 2,
 247         .dev = {
 248                 .platform_data  = &cmt2_platform_data,
 249         },
 250         .resource       = cmt2_resources,
 251         .num_resources  = ARRAY_SIZE(cmt2_resources),
 252 };
 253
 254 /* TMU */
 255 static struct sh_timer_config tmu00_platform_data = {
 256         .name = "TMU00",
 257         .channel_offset = 0x4,
 258         .timer_bit = 0,
 259         .clockevent_rating = 200,
 260 };
 261
 262 static struct resource tmu00_resources[] = {
 263         [0] = {
 264                 .name   = "TMU00",
 265                 .start  = 0xfff60008,
 266                 .end    = 0xfff60013,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         [1] = {
 270                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device tmu00_device = {
 276         .name           = "sh_tmu",
 277         .id             = 0,
 278         .dev = {
 279                 .platform_data  = &tmu00_platform_data,
 280         },
 281         .resource       = tmu00_resources,
 282         .num_resources  = ARRAY_SIZE(tmu00_resources),
 283 };
 284
 285 static struct sh_timer_config tmu01_platform_data = {
 286         .name = "TMU01",
 287         .channel_offset = 0x10,
 288         .timer_bit = 1,
 289         .clocksource_rating = 200,
 290 };
 291
 292 static struct resource tmu01_resources[] = {
 293         [0] = {
 294                 .name   = "TMU01",
 295                 .start  = 0xfff60014,
 296                 .end    = 0xfff6001f,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device tmu01_device = {
 306         .name           = "sh_tmu",
 307         .id             = 1,
 308         .dev = {
 309                 .platform_data  = &tmu01_platform_data,
 310         },
 311         .resource       = tmu01_resources,
 312         .num_resources  = ARRAY_SIZE(tmu01_resources),
 313 };
 314
 315 /* I2C */
 316 static struct resource iic0_resources[] = {
 317         [0] = {
 318                 .name   = "IIC0",
 319                 .start  = 0xFFF20000,
 320                 .end    = 0xFFF20425 - 1,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 325                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 static struct platform_device iic0_device = {
 331         .name           = "i2c-sh_mobile",
 332         .id             = 0, /* "i2c0" clock */
 333         .num_resources  = ARRAY_SIZE(iic0_resources),
 334         .resource       = iic0_resources,
 335 };
 336
 337 static struct resource iic1_resources[] = {
 338         [0] = {
 339                 .name   = "IIC1",
 340                 .start  = 0xE6C20000,
 341                 .end    = 0xE6C20425 - 1,
 342                 .flags  = IORESOURCE_MEM,
 343         },
 344         [1] = {
 345                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 346                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 347                 .flags  = IORESOURCE_IRQ,
 348         },
 349 };
 350
 351 static struct platform_device iic1_device = {
 352         .name           = "i2c-sh_mobile",
 353         .id             = 1, /* "i2c1" clock */
 354         .num_resources  = ARRAY_SIZE(iic1_resources),
 355         .resource       = iic1_resources,
 356 };
 357
 358 /* DMA */
 359 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 360         {
 361                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 362                 .addr           = 0xe6c40020,
 363                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 364                 .mid_rid        = 0x21,
 365         }, {
 366                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 367                 .addr           = 0xe6c40024,
 368                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 369                 .mid_rid        = 0x22,
 370         }, {
 371                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 372                 .addr           = 0xe6c50020,
 373                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 374                 .mid_rid        = 0x25,
 375         }, {
 376                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 377                 .addr           = 0xe6c50024,
 378                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 379                 .mid_rid        = 0x26,
 380         }, {
 381                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 382                 .addr           = 0xe6c60020,
 383                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 384                 .mid_rid        = 0x29,
 385         }, {
 386                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 387                 .addr           = 0xe6c60024,
 388                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 389                 .mid_rid        = 0x2a,
 390         }, {
 391                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 392                 .addr           = 0xe6c70020,
 393                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 394                 .mid_rid        = 0x2d,
 395         }, {
 396                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 397                 .addr           = 0xe6c70024,
 398                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 399                 .mid_rid        = 0x2e,
 400         }, {
 401                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 402                 .addr           = 0xe6c80020,
 403                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 404                 .mid_rid        = 0x39,
 405         }, {
 406                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 407                 .addr           = 0xe6c80024,
 408                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 409                 .mid_rid        = 0x3a,
 410         }, {
 411                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 412                 .addr           = 0xe6cb0020,
 413                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 414                 .mid_rid        = 0x35,
 415         }, {
 416                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 417                 .addr           = 0xe6cb0024,
 418                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 419                 .mid_rid        = 0x36,
 420         }, {
 421                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 422                 .addr           = 0xe6c30040,
 423                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 424                 .mid_rid        = 0x3d,
 425         }, {
 426                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 427                 .addr           = 0xe6c30060,
 428                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 429                 .mid_rid        = 0x3e,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 432                 .addr           = 0xe6a30050,
 433                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 434                 .mid_rid        = 0x83,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 437                 .addr           = 0xe6a30050,
 438                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 439                 .mid_rid        = 0x83,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 442                 .addr           = 0xe6a30060,
 443                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 444                 .mid_rid        = 0x87,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 447                 .addr           = 0xe6a30060,
 448                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 449                 .mid_rid        = 0x87,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 452                 .addr           = 0xe6850030,
 453                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 454                 .mid_rid        = 0xc1,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 457                 .addr           = 0xe6850030,
 458                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 459                 .mid_rid        = 0xc2,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 462                 .addr           = 0xe6860030,
 463                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 464                 .mid_rid        = 0xc9,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 467                 .addr           = 0xe6860030,
 468                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 469                 .mid_rid        = 0xca,
 470         }, {
 471                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 472                 .addr           = 0xe6870030,
 473                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 474                 .mid_rid        = 0xcd,
 475         }, {
 476                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 477                 .addr           = 0xe6870030,
 478                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 479                 .mid_rid        = 0xce,
 480         }, {
 481                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 482                 .addr           = 0xfe1f0024,
 483                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 484                 .mid_rid        = 0xb1,
 485         }, {
 486                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 487                 .addr           = 0xfe1f0020,
 488                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 489                 .mid_rid        = 0xb2,
 490         }, {
 491                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 492                 .addr           = 0xe6bd0034,
 493                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 494                 .mid_rid        = 0xd1,
 495         }, {
 496                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 497                 .addr           = 0xe6bd0034,
 498                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 499                 .mid_rid        = 0xd2,
 500         },
 501 };
 502
 503 #define SH7372_CHCLR (0x220 - 0x20)
 504
 505 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 506         {
 507                 .offset = 0,
 508                 .dmars = 0,
 509                 .dmars_bit = 0,
 510                 .chclr_offset = SH7372_CHCLR + 0,
 511         }, {
 512                 .offset = 0x10,
 513                 .dmars = 0,
 514                 .dmars_bit = 8,
 515                 .chclr_offset = SH7372_CHCLR + 0x10,
 516         }, {
 517                 .offset = 0x20,
 518                 .dmars = 4,
 519                 .dmars_bit = 0,
 520                 .chclr_offset = SH7372_CHCLR + 0x20,
 521         }, {
 522                 .offset = 0x30,
 523                 .dmars = 4,
 524                 .dmars_bit = 8,
 525                 .chclr_offset = SH7372_CHCLR + 0x30,
 526         }, {
 527                 .offset = 0x50,
 528                 .dmars = 8,
 529                 .dmars_bit = 0,
 530                 .chclr_offset = SH7372_CHCLR + 0x50,
 531         }, {
 532                 .offset = 0x60,
 533                 .dmars = 8,
 534                 .dmars_bit = 8,
 535                 .chclr_offset = SH7372_CHCLR + 0x60,
 536         }
 537 };
 538
 539 static struct sh_dmae_pdata dma_platform_data = {
 540         .slave          = sh7372_dmae_slaves,
 541         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 542         .channel        = sh7372_dmae_channels,
 543         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 544         .ts_low_shift   = TS_LOW_SHIFT,
 545         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 546         .ts_high_shift  = TS_HI_SHIFT,
 547         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 548         .ts_shift       = dma_ts_shift,
 549         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 550         .dmaor_init     = DMAOR_DME,
 551         .chclr_present  = 1,
 552 };
 553
 554 /* Resource order important! */
 555 static struct resource sh7372_dmae0_resources[] = {
 556         {
 557                 /* Channel registers and DMAOR */
 558                 .start  = 0xfe008020,
 559                 .end    = 0xfe00828f,
 560                 .flags  = IORESOURCE_MEM,
 561         },
 562         {
 563                 /* DMARSx */
 564                 .start  = 0xfe009000,
 565                 .end    = 0xfe00900b,
 566                 .flags  = IORESOURCE_MEM,
 567         },
 568         {
 569                 .name   = "error_irq",
 570                 .start  = evt2irq(0x20c0),
 571                 .end    = evt2irq(0x20c0),
 572                 .flags  = IORESOURCE_IRQ,
 573         },
 574         {
 575                 /* IRQ for channels 0-5 */
 576                 .start  = evt2irq(0x2000),
 577                 .end    = evt2irq(0x20a0),
 578                 .flags  = IORESOURCE_IRQ,
 579         },
 580 };
 581
 582 /* Resource order important! */
 583 static struct resource sh7372_dmae1_resources[] = {
 584         {
 585                 /* Channel registers and DMAOR */
 586                 .start  = 0xfe018020,
 587                 .end    = 0xfe01828f,
 588                 .flags  = IORESOURCE_MEM,
 589         },
 590         {
 591                 /* DMARSx */
 592                 .start  = 0xfe019000,
 593                 .end    = 0xfe01900b,
 594                 .flags  = IORESOURCE_MEM,
 595         },
 596         {
 597                 .name   = "error_irq",
 598                 .start  = evt2irq(0x21c0),
 599                 .end    = evt2irq(0x21c0),
 600                 .flags  = IORESOURCE_IRQ,
 601         },
 602         {
 603                 /* IRQ for channels 0-5 */
 604                 .start  = evt2irq(0x2100),
 605                 .end    = evt2irq(0x21a0),
 606                 .flags  = IORESOURCE_IRQ,
 607         },
 608 };
 609
 610 /* Resource order important! */
 611 static struct resource sh7372_dmae2_resources[] = {
 612         {
 613                 /* Channel registers and DMAOR */
 614                 .start  = 0xfe028020,
 615                 .end    = 0xfe02828f,
 616                 .flags  = IORESOURCE_MEM,
 617         },
 618         {
 619                 /* DMARSx */
 620                 .start  = 0xfe029000,
 621                 .end    = 0xfe02900b,
 622                 .flags  = IORESOURCE_MEM,
 623         },
 624         {
 625                 .name   = "error_irq",
 626                 .start  = evt2irq(0x22c0),
 627                 .end    = evt2irq(0x22c0),
 628                 .flags  = IORESOURCE_IRQ,
 629         },
 630         {
 631                 /* IRQ for channels 0-5 */
 632                 .start  = evt2irq(0x2200),
 633                 .end    = evt2irq(0x22a0),
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636 };
 637
 638 static struct platform_device dma0_device = {
 639         .name           = "sh-dma-engine",
 640         .id             = 0,
 641         .resource       = sh7372_dmae0_resources,
 642         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 643         .dev            = {
 644                 .platform_data  = &dma_platform_data,
 645         },
 646 };
 647
 648 static struct platform_device dma1_device = {
 649         .name           = "sh-dma-engine",
 650         .id             = 1,
 651         .resource       = sh7372_dmae1_resources,
 652         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 653         .dev            = {
 654                 .platform_data  = &dma_platform_data,
 655         },
 656 };
 657
 658 static struct platform_device dma2_device = {
 659         .name           = "sh-dma-engine",
 660         .id             = 2,
 661         .resource       = sh7372_dmae2_resources,
 662         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 663         .dev            = {
 664                 .platform_data  = &dma_platform_data,
 665         },
 666 };
 667
 668 /*
 669  * USB-DMAC
 670  */
 671 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 672         {
 673                 .offset = 0,
 674         }, {
 675                 .offset = 0x20,
 676         },
 677 };
 678
 679 /* USB DMAC0 */
 680 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 681         {
 682                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 683                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 684         }, {
 685                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 686                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 687         },
 688 };
 689
 690 static struct sh_dmae_pdata usb_dma0_platform_data = {
 691         .slave          = sh7372_usb_dmae0_slaves,
 692         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 693         .channel        = sh7372_usb_dmae_channels,
 694         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 695         .ts_low_shift   = USBTS_LOW_SHIFT,
 696         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 697         .ts_high_shift  = USBTS_HI_SHIFT,
 698         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 699         .ts_shift       = dma_usbts_shift,
 700         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 701         .dmaor_init     = DMAOR_DME,
 702         .chcr_offset    = 0x14,
 703         .chcr_ie_bit    = 1 << 5,
 704         .dmaor_is_32bit = 1,
 705         .needs_tend_set = 1,
 706         .no_dmars       = 1,
 707         .slave_only     = 1,
 708 };
 709
 710 static struct resource sh7372_usb_dmae0_resources[] = {
 711         {
 712                 /* Channel registers and DMAOR */
 713                 .start  = 0xe68a0020,
 714                 .end    = 0xe68a0064 - 1,
 715                 .flags  = IORESOURCE_MEM,
 716         },
 717         {
 718                 /* VCR/SWR/DMICR */
 719                 .start  = 0xe68a0000,
 720                 .end    = 0xe68a0014 - 1,
 721                 .flags  = IORESOURCE_MEM,
 722         },
 723         {
 724                 /* IRQ for channels */
 725                 .start  = evt2irq(0x0a00),
 726                 .end    = evt2irq(0x0a00),
 727                 .flags  = IORESOURCE_IRQ,
 728         },
 729 };
 730
 731 static struct platform_device usb_dma0_device = {
 732         .name           = "sh-dma-engine",
 733         .id             = 3,
 734         .resource       = sh7372_usb_dmae0_resources,
 735         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 736         .dev            = {
 737                 .platform_data  = &usb_dma0_platform_data,
 738         },
 739 };
 740
 741 /* USB DMAC1 */
 742 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 743         {
 744                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 745                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 746         }, {
 747                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 748                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 749         },
 750 };
 751
 752 static struct sh_dmae_pdata usb_dma1_platform_data = {
 753         .slave          = sh7372_usb_dmae1_slaves,
 754         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 755         .channel        = sh7372_usb_dmae_channels,
 756         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 757         .ts_low_shift   = USBTS_LOW_SHIFT,
 758         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 759         .ts_high_shift  = USBTS_HI_SHIFT,
 760         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 761         .ts_shift       = dma_usbts_shift,
 762         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 763         .dmaor_init     = DMAOR_DME,
 764         .chcr_offset    = 0x14,
 765         .chcr_ie_bit    = 1 << 5,
 766         .dmaor_is_32bit = 1,
 767         .needs_tend_set = 1,
 768         .no_dmars       = 1,
 769         .slave_only     = 1,
 770 };
 771
 772 static struct resource sh7372_usb_dmae1_resources[] = {
 773         {
 774                 /* Channel registers and DMAOR */
 775                 .start  = 0xe68c0020,
 776                 .end    = 0xe68c0064 - 1,
 777                 .flags  = IORESOURCE_MEM,
 778         },
 779         {
 780                 /* VCR/SWR/DMICR */
 781                 .start  = 0xe68c0000,
 782                 .end    = 0xe68c0014 - 1,
 783                 .flags  = IORESOURCE_MEM,
 784         },
 785         {
 786                 /* IRQ for channels */
 787                 .start  = evt2irq(0x1d00),
 788                 .end    = evt2irq(0x1d00),
 789                 .flags  = IORESOURCE_IRQ,
 790         },
 791 };
 792
 793 static struct platform_device usb_dma1_device = {
 794         .name           = "sh-dma-engine",
 795         .id             = 4,
 796         .resource       = sh7372_usb_dmae1_resources,
 797         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 798         .dev            = {
 799                 .platform_data  = &usb_dma1_platform_data,
 800         },
 801 };
 802
 803 /* VPU */
 804 static struct uio_info vpu_platform_data = {
 805         .name = "VPU5HG",
 806         .version = "0",
 807         .irq = intcs_evt2irq(0x980),
 808 };
 809
 810 static struct resource vpu_resources[] = {
 811         [0] = {
 812                 .name   = "VPU",
 813                 .start  = 0xfe900000,
 814                 .end    = 0xfe900157,
 815                 .flags  = IORESOURCE_MEM,
 816         },
 817 };
 818
 819 static struct platform_device vpu_device = {
 820         .name           = "uio_pdrv_genirq",
 821         .id             = 0,
 822         .dev = {
 823                 .platform_data  = &vpu_platform_data,
 824         },
 825         .resource       = vpu_resources,
 826         .num_resources  = ARRAY_SIZE(vpu_resources),
 827 };
 828
 829 /* VEU0 */
 830 static struct uio_info veu0_platform_data = {
 831         .name = "VEU0",
 832         .version = "0",
 833         .irq = intcs_evt2irq(0x700),
 834 };
 835
 836 static struct resource veu0_resources[] = {
 837         [0] = {
 838                 .name   = "VEU0",
 839                 .start  = 0xfe920000,
 840                 .end    = 0xfe9200cb,
 841                 .flags  = IORESOURCE_MEM,
 842         },
 843 };
 844
 845 static struct platform_device veu0_device = {
 846         .name           = "uio_pdrv_genirq",
 847         .id             = 1,
 848         .dev = {
 849                 .platform_data  = &veu0_platform_data,
 850         },
 851         .resource       = veu0_resources,
 852         .num_resources  = ARRAY_SIZE(veu0_resources),
 853 };
 854
 855 /* VEU1 */
 856 static struct uio_info veu1_platform_data = {
 857         .name = "VEU1",
 858         .version = "0",
 859         .irq = intcs_evt2irq(0x720),
 860 };
 861
 862 static struct resource veu1_resources[] = {
 863         [0] = {
 864                 .name   = "VEU1",
 865                 .start  = 0xfe924000,
 866                 .end    = 0xfe9240cb,
 867                 .flags  = IORESOURCE_MEM,
 868         },
 869 };
 870
 871 static struct platform_device veu1_device = {
 872         .name           = "uio_pdrv_genirq",
 873         .id             = 2,
 874         .dev = {
 875                 .platform_data  = &veu1_platform_data,
 876         },
 877         .resource       = veu1_resources,
 878         .num_resources  = ARRAY_SIZE(veu1_resources),
 879 };
 880
 881 /* VEU2 */
 882 static struct uio_info veu2_platform_data = {
 883         .name = "VEU2",
 884         .version = "0",
 885         .irq = intcs_evt2irq(0x740),
 886 };
 887
 888 static struct resource veu2_resources[] = {
 889         [0] = {
 890                 .name   = "VEU2",
 891                 .start  = 0xfe928000,
 892                 .end    = 0xfe928307,
 893                 .flags  = IORESOURCE_MEM,
 894         },
 895 };
 896
 897 static struct platform_device veu2_device = {
 898         .name           = "uio_pdrv_genirq",
 899         .id             = 3,
 900         .dev = {
 901                 .platform_data  = &veu2_platform_data,
 902         },
 903         .resource       = veu2_resources,
 904         .num_resources  = ARRAY_SIZE(veu2_resources),
 905 };
 906
 907 /* VEU3 */
 908 static struct uio_info veu3_platform_data = {
 909         .name = "VEU3",
 910         .version = "0",
 911         .irq = intcs_evt2irq(0x760),
 912 };
 913
 914 static struct resource veu3_resources[] = {
 915         [0] = {
 916                 .name   = "VEU3",
 917                 .start  = 0xfe92c000,
 918                 .end    = 0xfe92c307,
 919                 .flags  = IORESOURCE_MEM,
 920         },
 921 };
 922
 923 static struct platform_device veu3_device = {
 924         .name           = "uio_pdrv_genirq",
 925         .id             = 4,
 926         .dev = {
 927                 .platform_data  = &veu3_platform_data,
 928         },
 929         .resource       = veu3_resources,
 930         .num_resources  = ARRAY_SIZE(veu3_resources),
 931 };
 932
 933 /* JPU */
 934 static struct uio_info jpu_platform_data = {
 935         .name = "JPU",
 936         .version = "0",
 937         .irq = intcs_evt2irq(0x560),
 938 };
 939
 940 static struct resource jpu_resources[] = {
 941         [0] = {
 942                 .name   = "JPU",
 943                 .start  = 0xfe980000,
 944                 .end    = 0xfe9902d3,
 945                 .flags  = IORESOURCE_MEM,
 946         },
 947 };
 948
 949 static struct platform_device jpu_device = {
 950         .name           = "uio_pdrv_genirq",
 951         .id             = 5,
 952         .dev = {
 953                 .platform_data  = &jpu_platform_data,
 954         },
 955         .resource       = jpu_resources,
 956         .num_resources  = ARRAY_SIZE(jpu_resources),
 957 };
 958
 959 /* SPU2DSP0 */
 960 static struct uio_info spu0_platform_data = {
 961         .name = "SPU2DSP0",
 962         .version = "0",
 963         .irq = evt2irq(0x1800),
 964 };
 965
 966 static struct resource spu0_resources[] = {
 967         [0] = {
 968                 .name   = "SPU2DSP0",
 969                 .start  = 0xfe200000,
 970                 .end    = 0xfe2fffff,
 971                 .flags  = IORESOURCE_MEM,
 972         },
 973 };
 974
 975 static struct platform_device spu0_device = {
 976         .name           = "uio_pdrv_genirq",
 977         .id             = 6,
 978         .dev = {
 979                 .platform_data  = &spu0_platform_data,
 980         },
 981         .resource       = spu0_resources,
 982         .num_resources  = ARRAY_SIZE(spu0_resources),
 983 };
 984
 985 /* SPU2DSP1 */
 986 static struct uio_info spu1_platform_data = {
 987         .name = "SPU2DSP1",
 988         .version = "0",
 989         .irq = evt2irq(0x1820),
 990 };
 991
 992 static struct resource spu1_resources[] = {
 993         [0] = {
 994                 .name   = "SPU2DSP1",
 995                 .start  = 0xfe300000,
 996                 .end    = 0xfe3fffff,
 997                 .flags  = IORESOURCE_MEM,
 998         },
 999 };
1000
1001 static struct platform_device spu1_device = {
1002         .name           = "uio_pdrv_genirq",
1003         .id             = 7,
1004         .dev = {
1005                 .platform_data  = &spu1_platform_data,
1006         },
1007         .resource       = spu1_resources,
1008         .num_resources  = ARRAY_SIZE(spu1_resources),
1009 };
1010
1011 /* IPMMUI (an IPMMU module for ICB/LMB) */
1012 static struct resource ipmmu_resources[] = {
1013         [0] = {
1014                 .name   = "IPMMUI",
1015                 .start  = 0xfe951000,
1016                 .end    = 0xfe9510ff,
1017                 .flags  = IORESOURCE_MEM,
1018         },
1019 };
1020
1021 static const char * const ipmmu_dev_names[] = {
1022         "sh_mobile_lcdc_fb.0",
1023         "sh_mobile_lcdc_fb.1",
1024         "sh_mobile_ceu.0",
1025         "uio_pdrv_genirq.0",
1026         "uio_pdrv_genirq.1",
1027         "uio_pdrv_genirq.2",
1028         "uio_pdrv_genirq.3",
1029         "uio_pdrv_genirq.4",
1030         "uio_pdrv_genirq.5",
1031 };
1032
1033 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
1034         .dev_names = ipmmu_dev_names,
1035         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
1036 };
1037
1038 static struct platform_device ipmmu_device = {
1039         .name           = "ipmmu",
1040         .id             = -1,
1041         .dev = {
1042                 .platform_data = &ipmmu_platform_data,
1043         },
1044         .resource       = ipmmu_resources,
1045         .num_resources  = ARRAY_SIZE(ipmmu_resources),
1046 };
1047
1048 static struct platform_device *sh7372_early_devices[] __initdata = {
1049         &scif0_device,
1050         &scif1_device,
1051         &scif2_device,
1052         &scif3_device,
1053         &scif4_device,
1054         &scif5_device,
1055         &scif6_device,
1056         &cmt2_device,
1057         &tmu00_device,
1058         &tmu01_device,
1059         &ipmmu_device,
1060 };
1061
1062 static struct platform_device *sh7372_late_devices[] __initdata = {
1063         &iic0_device,
1064         &iic1_device,
1065         &dma0_device,
1066         &dma1_device,
1067         &dma2_device,
1068         &usb_dma0_device,
1069         &usb_dma1_device,
1070         &vpu_device,
1071         &veu0_device,
1072         &veu1_device,
1073         &veu2_device,
1074         &veu3_device,
1075         &jpu_device,
1076         &spu0_device,
1077         &spu1_device,
1078 };
1079
1080 void __init sh7372_add_standard_devices(void)
1081 {
1082         struct pm_domain_device domain_devices[] = {
1083                 { "A3RV", &vpu_device, },
1084                 { "A4MP", &spu0_device, },
1085                 { "A4MP", &spu1_device, },
1086                 { "A3SP", &scif0_device, },
1087                 { "A3SP", &scif1_device, },
1088                 { "A3SP", &scif2_device, },
1089                 { "A3SP", &scif3_device, },
1090                 { "A3SP", &scif4_device, },
1091                 { "A3SP", &scif5_device, },
1092                 { "A3SP", &scif6_device, },
1093                 { "A3SP", &iic1_device, },
1094                 { "A3SP", &dma0_device, },
1095                 { "A3SP", &dma1_device, },
1096                 { "A3SP", &dma2_device, },
1097                 { "A3SP", &usb_dma0_device, },
1098                 { "A3SP", &usb_dma1_device, },
1099                 { "A4R", &iic0_device, },
1100                 { "A4R", &veu0_device, },
1101                 { "A4R", &veu1_device, },
1102                 { "A4R", &veu2_device, },
1103                 { "A4R", &veu3_device, },
1104                 { "A4R", &jpu_device, },
1105                 { "A4R", &tmu00_device, },
1106                 { "A4R", &tmu01_device, },
1107         };
1108
1109         sh7372_init_pm_domains();
1110
1111         platform_add_devices(sh7372_early_devices,
1112                             ARRAY_SIZE(sh7372_early_devices));
1113
1114         platform_add_devices(sh7372_late_devices,
1115                             ARRAY_SIZE(sh7372_late_devices));
1116
1117         rmobile_add_devices_to_domains(domain_devices,
1118                                        ARRAY_SIZE(domain_devices));
1119 }
1120
1121 void __init sh7372_earlytimer_init(void)
1122 {
1123         sh7372_clock_init();
1124         shmobile_earlytimer_init();
1125 }
1126
1127 void __init sh7372_add_early_devices(void)
1128 {
1129         early_platform_add_devices(sh7372_early_devices,
1130                                    ARRAY_SIZE(sh7372_early_devices));
1131
1132         /* setup early console here as well */
1133         shmobile_setup_console();
1134 }
1135
1136 #ifdef CONFIG_USE_OF
1137
1138 void __init sh7372_add_early_devices_dt(void)
1139 {
1140         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1141
1142         early_platform_add_devices(sh7372_early_devices,
1143                                    ARRAY_SIZE(sh7372_early_devices));
1144
1145         /* setup early console here as well */
1146         shmobile_setup_console();
1147 }
1148
1149 void __init sh7372_add_standard_devices_dt(void)
1150 {
1151         /* clocks are setup late during boot in the case of DT */
1152         sh7372_clock_init();
1153
1154         platform_add_devices(sh7372_early_devices,
1155                             ARRAY_SIZE(sh7372_early_devices));
1156
1157         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1158 }
1159
1160 static const char *sh7372_boards_compat_dt[] __initdata = {
1161         "renesas,sh7372",
1162         NULL,
1163 };
1164
1165 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1166         .map_io         = sh7372_map_io,
1167         .init_early     = sh7372_add_early_devices_dt,
1168         .nr_irqs        = NR_IRQS_LEGACY,
1169         .init_irq       = sh7372_init_irq,
1170         .handle_irq     = shmobile_handle_irq_intc,
1171         .init_machine   = sh7372_add_standard_devices_dt,
1172         .dt_compat      = sh7372_boards_compat_dt,
1173 MACHINE_END
1174
1175 #endif /* CONFIG_USE_OF */