x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-sti / platsmp.c
blobdce50d983a8edc267c4157903952f07487a177c7
1 /*
2 * arch/arm/mach-sti/platsmp.c
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
7 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
9 * Copyright (C) 2002 ARM Ltd.
10 * All Rights Reserved
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/smp.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
28 #include "smp.h"
30 static void write_pen_release(int val)
32 pen_release = val;
33 smp_wmb();
34 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
35 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
38 static DEFINE_SPINLOCK(boot_lock);
40 void sti_secondary_init(unsigned int cpu)
42 trace_hardirqs_off();
45 * let the primary processor know we're out of the
46 * pen, then head off into the C entry point
48 write_pen_release(-1);
51 * Synchronise with the boot thread.
53 spin_lock(&boot_lock);
54 spin_unlock(&boot_lock);
57 int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
59 unsigned long timeout;
62 * set synchronisation state between this boot processor
63 * and the secondary one
65 spin_lock(&boot_lock);
68 * The secondary processor is waiting to be released from
69 * the holding pen - release it, then wait for it to flag
70 * that it has been released by resetting pen_release.
72 * Note that "pen_release" is the hardware CPU ID, whereas
73 * "cpu" is Linux's internal ID.
75 write_pen_release(cpu_logical_map(cpu));
78 * Send the secondary CPU a soft interrupt, thereby causing
79 * it to jump to the secondary entrypoint.
81 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
83 timeout = jiffies + (1 * HZ);
84 while (time_before(jiffies, timeout)) {
85 smp_rmb();
86 if (pen_release == -1)
87 break;
89 udelay(10);
93 * now the secondary core is starting up let it run its
94 * calibrations, then wait for it to finish
96 spin_unlock(&boot_lock);
98 return pen_release != -1 ? -ENOSYS : 0;
101 void __init sti_smp_prepare_cpus(unsigned int max_cpus)
103 void __iomem *scu_base = NULL;
104 struct device_node *np = of_find_compatible_node(
105 NULL, NULL, "arm,cortex-a9-scu");
106 if (np) {
107 scu_base = of_iomap(np, 0);
108 scu_enable(scu_base);
109 of_node_put(np);
113 struct smp_operations __initdata sti_smp_ops = {
114 .smp_prepare_cpus = sti_smp_prepare_cpus,
115 .smp_secondary_init = sti_secondary_init,
116 .smp_boot_secondary = sti_boot_secondary,