arch/arm/mach-tegra/pmc.c

   1 /*
   2  * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23
  24 #include "flowctrl.h"
  25 #include "fuse.h"
  26 #include "pm.h"
  27 #include "pmc.h"
  28 #include "sleep.h"
  29
  30 #define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
  31 #define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
  32 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
  33 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
  34 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
  35
  36 #define PMC_CTRL                        0x0
  37 #define PMC_CTRL_INTR_LOW               (1 << 17)
  38 #define PMC_PWRGATE_TOGGLE              0x30
  39 #define PMC_PWRGATE_TOGGLE_START        (1 << 8)
  40 #define PMC_REMOVE_CLAMPING             0x34
  41 #define PMC_PWRGATE_STATUS              0x38
  42
  43 #define PMC_CPUPWRGOOD_TIMER    0xc8
  44 #define PMC_CPUPWROFF_TIMER     0xcc
  45
  46 #define TEGRA_POWERGATE_PCIE    3
  47 #define TEGRA_POWERGATE_VDEC    4
  48 #define TEGRA_POWERGATE_CPU1    9
  49 #define TEGRA_POWERGATE_CPU2    10
  50 #define TEGRA_POWERGATE_CPU3    11
  51
  52 static u8 tegra_cpu_domains[] = {
  53         0xFF,                   /* not available for CPU0 */
  54         TEGRA_POWERGATE_CPU1,
  55         TEGRA_POWERGATE_CPU2,
  56         TEGRA_POWERGATE_CPU3,
  57 };
  58 static DEFINE_SPINLOCK(tegra_powergate_lock);
  59
  60 static void __iomem *tegra_pmc_base;
  61 static bool tegra_pmc_invert_interrupt;
  62 static struct clk *tegra_pclk;
  63
  64 struct pmc_pm_data {
  65         u32 cpu_good_time;      /* CPU power good time in uS */
  66         u32 cpu_off_time;       /* CPU power off time in uS */
  67         u32 core_osc_time;      /* Core power good osc time in uS */
  68         u32 core_pmu_time;      /* Core power good pmu time in uS */
  69         u32 core_off_time;      /* Core power off time in uS */
  70         bool corereq_high;      /* Core power request active-high */
  71         bool sysclkreq_high;    /* System clock request active-high */
  72         bool combined_req;      /* Combined pwr req for CPU & Core */
  73         bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
  74         u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
  75         u32 lp0_vec_size;       /* The size of LP0 warm boot code */
  76         enum tegra_suspend_mode suspend_mode;
  77 };
  78 static struct pmc_pm_data pmc_pm_data;
  79
  80 static inline u32 tegra_pmc_readl(u32 reg)
  81 {
  82         return readl(tegra_pmc_base + reg);
  83 }
  84
  85 static inline void tegra_pmc_writel(u32 val, u32 reg)
  86 {
  87         writel(val, tegra_pmc_base + reg);
  88 }
  89
  90 static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
  91 {
  92         if (cpuid <= 0 || cpuid >= num_possible_cpus())
  93                 return -EINVAL;
  94         return tegra_cpu_domains[cpuid];
  95 }
  96
  97 static bool tegra_pmc_powergate_is_powered(int id)
  98 {
  99         return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
 100 }
 101
 102 static int tegra_pmc_powergate_set(int id, bool new_state)
 103 {
 104         bool old_state;
 105         unsigned long flags;
 106
 107         spin_lock_irqsave(&tegra_powergate_lock, flags);
 108
 109         old_state = tegra_pmc_powergate_is_powered(id);
 110         WARN_ON(old_state == new_state);
 111
 112         tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
 113
 114         spin_unlock_irqrestore(&tegra_powergate_lock, flags);
 115
 116         return 0;
 117 }
 118
 119 static int tegra_pmc_powergate_remove_clamping(int id)
 120 {
 121         u32 mask;
 122
 123         /*
 124          * Tegra has a bug where PCIE and VDE clamping masks are
 125          * swapped relatively to the partition ids.
 126          */
 127         if (id ==  TEGRA_POWERGATE_VDEC)
 128                 mask = (1 << TEGRA_POWERGATE_PCIE);
 129         else if (id == TEGRA_POWERGATE_PCIE)
 130                 mask = (1 << TEGRA_POWERGATE_VDEC);
 131         else
 132                 mask = (1 << id);
 133
 134         tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
 135
 136         return 0;
 137 }
 138
 139 bool tegra_pmc_cpu_is_powered(int cpuid)
 140 {
 141         int id;
 142
 143         id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
 144         if (id < 0)
 145                 return false;
 146         return tegra_pmc_powergate_is_powered(id);
 147 }
 148
 149 int tegra_pmc_cpu_power_on(int cpuid)
 150 {
 151         int id;
 152
 153         id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
 154         if (id < 0)
 155                 return id;
 156         return tegra_pmc_powergate_set(id, true);
 157 }
 158
 159 int tegra_pmc_cpu_remove_clamping(int cpuid)
 160 {
 161         int id;
 162
 163         id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
 164         if (id < 0)
 165                 return id;
 166         return tegra_pmc_powergate_remove_clamping(id);
 167 }
 168
 169 #ifdef CONFIG_PM_SLEEP
 170 static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
 171 {
 172         unsigned long long ticks;
 173         unsigned long long pclk;
 174         static unsigned long tegra_last_pclk;
 175
 176         if (WARN_ON_ONCE(rate <= 0))
 177                 pclk = 100000000;
 178         else
 179                 pclk = rate;
 180
 181         if ((rate != tegra_last_pclk)) {
 182                 ticks = (us_on * pclk) + 999999ull;
 183                 do_div(ticks, 1000000);
 184                 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
 185
 186                 ticks = (us_off * pclk) + 999999ull;
 187                 do_div(ticks, 1000000);
 188                 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
 189                 wmb();
 190         }
 191         tegra_last_pclk = pclk;
 192 }
 193
 194 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
 195 {
 196         return pmc_pm_data.suspend_mode;
 197 }
 198
 199 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
 200 {
 201         if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
 202                 return;
 203
 204         pmc_pm_data.suspend_mode = mode;
 205 }
 206
 207 void tegra_pmc_suspend(void)
 208 {
 209         tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
 210 }
 211
 212 void tegra_pmc_resume(void)
 213 {
 214         tegra_pmc_writel(0x0, PMC_SCRATCH41);
 215 }
 216
 217 void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
 218 {
 219         u32 reg, csr_reg;
 220         unsigned long rate = 0;
 221
 222         reg = tegra_pmc_readl(PMC_CTRL);
 223         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
 224         reg &= ~TEGRA_POWER_EFFECT_LP0;
 225
 226         switch (tegra_chip_id) {
 227         case TEGRA20:
 228         case TEGRA30:
 229                 break;
 230         default:
 231                 /* Turn off CRAIL */
 232                 csr_reg = flowctrl_read_cpu_csr(0);
 233                 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
 234                 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
 235                 flowctrl_write_cpu_csr(0, csr_reg);
 236                 break;
 237         }
 238
 239         switch (mode) {
 240         case TEGRA_SUSPEND_LP1:
 241                 rate = 32768;
 242                 break;
 243         case TEGRA_SUSPEND_LP2:
 244                 rate = clk_get_rate(tegra_pclk);
 245                 break;
 246         default:
 247                 break;
 248         }
 249
 250         set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
 251                          rate);
 252
 253         tegra_pmc_writel(reg, PMC_CTRL);
 254 }
 255
 256 void tegra_pmc_suspend_init(void)
 257 {
 258         u32 reg;
 259
 260         /* Always enable CPU power request */
 261         reg = tegra_pmc_readl(PMC_CTRL);
 262         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
 263         tegra_pmc_writel(reg, PMC_CTRL);
 264
 265         reg = tegra_pmc_readl(PMC_CTRL);
 266
 267         if (!pmc_pm_data.sysclkreq_high)
 268                 reg |= TEGRA_POWER_SYSCLK_POLARITY;
 269         else
 270                 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
 271
 272         /* configure the output polarity while the request is tristated */
 273         tegra_pmc_writel(reg, PMC_CTRL);
 274
 275         /* now enable the request */
 276         reg |= TEGRA_POWER_SYSCLK_OE;
 277         tegra_pmc_writel(reg, PMC_CTRL);
 278 }
 279 #endif
 280
 281 static const struct of_device_id matches[] __initconst = {
 282         { .compatible = "nvidia,tegra114-pmc" },
 283         { .compatible = "nvidia,tegra30-pmc" },
 284         { .compatible = "nvidia,tegra20-pmc" },
 285         { }
 286 };
 287
 288 static void __init tegra_pmc_parse_dt(void)
 289 {
 290         struct device_node *np;
 291         u32 prop;
 292         enum tegra_suspend_mode suspend_mode;
 293         u32 core_good_time[2] = {0, 0};
 294         u32 lp0_vec[2] = {0, 0};
 295
 296         np = of_find_matching_node(NULL, matches);
 297         BUG_ON(!np);
 298
 299         tegra_pmc_base = of_iomap(np, 0);
 300
 301         tegra_pmc_invert_interrupt = of_property_read_bool(np,
 302                                      "nvidia,invert-interrupt");
 303         tegra_pclk = of_clk_get_by_name(np, "pclk");
 304         WARN_ON(IS_ERR(tegra_pclk));
 305
 306         /* Grabbing the power management configurations */
 307         if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
 308                 suspend_mode = TEGRA_SUSPEND_NONE;
 309         } else {
 310                 switch (prop) {
 311                 case 0:
 312                         suspend_mode = TEGRA_SUSPEND_LP0;
 313                         break;
 314                 case 1:
 315                         suspend_mode = TEGRA_SUSPEND_LP1;
 316                         break;
 317                 case 2:
 318                         suspend_mode = TEGRA_SUSPEND_LP2;
 319                         break;
 320                 default:
 321                         suspend_mode = TEGRA_SUSPEND_NONE;
 322                         break;
 323                 }
 324         }
 325         suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
 326
 327         if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
 328                 suspend_mode = TEGRA_SUSPEND_NONE;
 329         pmc_pm_data.cpu_good_time = prop;
 330
 331         if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
 332                 suspend_mode = TEGRA_SUSPEND_NONE;
 333         pmc_pm_data.cpu_off_time = prop;
 334
 335         if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
 336                         core_good_time, ARRAY_SIZE(core_good_time)))
 337                 suspend_mode = TEGRA_SUSPEND_NONE;
 338         pmc_pm_data.core_osc_time = core_good_time[0];
 339         pmc_pm_data.core_pmu_time = core_good_time[1];
 340
 341         if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
 342                                  &prop))
 343                 suspend_mode = TEGRA_SUSPEND_NONE;
 344         pmc_pm_data.core_off_time = prop;
 345
 346         pmc_pm_data.corereq_high = of_property_read_bool(np,
 347                                 "nvidia,core-power-req-active-high");
 348
 349         pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
 350                                 "nvidia,sys-clock-req-active-high");
 351
 352         pmc_pm_data.combined_req = of_property_read_bool(np,
 353                                 "nvidia,combined-power-req");
 354
 355         pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
 356                                 "nvidia,cpu-pwr-good-en");
 357
 358         if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
 359                                        ARRAY_SIZE(lp0_vec)))
 360                 if (suspend_mode == TEGRA_SUSPEND_LP0)
 361                         suspend_mode = TEGRA_SUSPEND_LP1;
 362
 363         pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
 364         pmc_pm_data.lp0_vec_size = lp0_vec[1];
 365
 366         pmc_pm_data.suspend_mode = suspend_mode;
 367 }
 368
 369 void __init tegra_pmc_init(void)
 370 {
 371         u32 val;
 372
 373         tegra_pmc_parse_dt();
 374
 375         val = tegra_pmc_readl(PMC_CTRL);
 376         if (tegra_pmc_invert_interrupt)
 377                 val |= PMC_CTRL_INTR_LOW;
 378         else
 379                 val &= ~PMC_CTRL_INTR_LOW;
 380         tegra_pmc_writel(val, PMC_CTRL);
 381 }