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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-versatile / core.c
blob3b0572f30d5608d7ffdafcb68f2777a0dab8afa1
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/io.h>
35 #include <linux/irqchip/arm-vic.h>
36 #include <linux/irqchip/versatile-fpga.h>
37 #include <linux/gfp.h>
38 #include <linux/clkdev.h>
39 #include <linux/mtd/physmap.h>
40 #include <linux/bitops.h>
41 #include <linux/reboot.h>
42
43 #include <asm/irq.h>
44 #include <asm/hardware/arm_timer.h>
45 #include <asm/hardware/icst.h>
46 #include <asm/mach-types.h>
47
48 #include <asm/mach/arch.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/map.h>
52 #include <mach/hardware.h>
53 #include <mach/platform.h>
54 #include <asm/hardware/timer-sp.h>
55
56 #include <plat/clcd.h>
57 #include <plat/sched_clock.h>
58
59 #include "core.h"
60
61 /*
62 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * is the (PA >> 12).
64 *
65 * Setup a VA for the Versatile Vectored Interrupt Controller.
66 */
67 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
68 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
69
70 /* These PIC IRQs are valid in each configuration */
71 #define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
72 BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
73 BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
74 BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
75 BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
76 BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
77 BIT(SIC_INT_PCI3)
78 #if 1
79 #define IRQ_MMCI0A IRQ_VICSOURCE22
80 #define IRQ_AACI IRQ_VICSOURCE24
81 #define IRQ_ETH IRQ_VICSOURCE25
82 #define PIC_MASK 0xFFD00000
83 #define PIC_VALID PIC_VALID_ALL
84 #else
85 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
86 #define IRQ_AACI IRQ_SIC_AACI
87 #define IRQ_ETH IRQ_SIC_ETH
88 #define PIC_MASK 0
89 #define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
90 BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
91 BIT(SIC_INT_ETH)
92 #endif
93
94 /* Lookup table for finding a DT node that represents the vic instance */
95 static const struct of_device_id vic_of_match[] __initconst = {
96 { .compatible = "arm,versatile-vic", },
97 {}
98 };
99
100 static const struct of_device_id sic_of_match[] __initconst = {
101 { .compatible = "arm,versatile-sic", },
102 {}
103 };
104
105 void __init versatile_init_irq(void)
106 {
107 struct device_node *np;
108
109 np = of_find_matching_node_by_address(NULL, vic_of_match,
110 VERSATILE_VIC_BASE);
111 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
112
113 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
114
115 np = of_find_matching_node_by_address(NULL, sic_of_match,
116 VERSATILE_SIC_BASE);
117
118 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
119 IRQ_VICSOURCE31, PIC_VALID, np);
120
121 /*
122 * Interrupts on secondary controller from 0 to 8 are routed to
123 * source 31 on PIC.
124 * Interrupts from 21 to 31 are routed directly to the VIC on
125 * the corresponding number on primary controller. This is controlled
126 * by setting PIC_ENABLEx.
127 */
128 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
129 }
130
131 static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
132 {
133 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
134 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
135 .length = SZ_4K,
136 .type = MT_DEVICE
137 }, {
138 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
139 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
140 .length = SZ_4K,
141 .type = MT_DEVICE
142 }, {
143 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
144 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
145 .length = SZ_4K,
146 .type = MT_DEVICE
147 }, {
148 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
150 .length = SZ_4K * 9,
151 .type = MT_DEVICE
152 },
153 #ifdef CONFIG_MACH_VERSATILE_AB
154 {
155 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
156 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
157 .length = SZ_64M,
158 .type = MT_DEVICE
159 },
160 #endif
161 #ifdef CONFIG_DEBUG_LL
162 {
163 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
164 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
165 .length = SZ_4K,
166 .type = MT_DEVICE
167 },
168 #endif
169 #ifdef CONFIG_PCI
170 {
171 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
172 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
173 .length = SZ_4K,
174 .type = MT_DEVICE
175 }, {
176 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
177 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
178 .length = VERSATILE_PCI_BASE_SIZE,
179 .type = MT_DEVICE
180 }, {
181 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
182 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
183 .length = VERSATILE_PCI_CFG_BASE_SIZE,
184 .type = MT_DEVICE
185 },
186 #endif
187 };
188
189 void __init versatile_map_io(void)
190 {
191 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
192 }
193
194
195 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
196
197 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
198 {
199 u32 val;
200
201 val = __raw_readl(VERSATILE_FLASHCTRL);
202 if (on)
203 val |= VERSATILE_FLASHPROG_FLVPPEN;
204 else
205 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
206 __raw_writel(val, VERSATILE_FLASHCTRL);
207 }
208
209 static struct physmap_flash_data versatile_flash_data = {
210 .width = 4,
211 .set_vpp = versatile_flash_set_vpp,
212 };
213
214 static struct resource versatile_flash_resource = {
215 .start = VERSATILE_FLASH_BASE,
216 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
217 .flags = IORESOURCE_MEM,
218 };
219
220 static struct platform_device versatile_flash_device = {
221 .name = "physmap-flash",
222 .id = 0,
223 .dev = {
224 .platform_data = &versatile_flash_data,
225 },
226 .num_resources = 1,
227 .resource = &versatile_flash_resource,
228 };
229
230 static struct resource smc91x_resources[] = {
231 [0] = {
232 .start = VERSATILE_ETH_BASE,
233 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_ETH,
238 .end = IRQ_ETH,
239 .flags = IORESOURCE_IRQ,
240 },
241 };
242
243 static struct platform_device smc91x_device = {
244 .name = "smc91x",
245 .id = 0,
246 .num_resources = ARRAY_SIZE(smc91x_resources),
247 .resource = smc91x_resources,
248 };
249
250 static struct resource versatile_i2c_resource = {
251 .start = VERSATILE_I2C_BASE,
252 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
253 .flags = IORESOURCE_MEM,
254 };
255
256 static struct platform_device versatile_i2c_device = {
257 .name = "versatile-i2c",
258 .id = 0,
259 .num_resources = 1,
260 .resource = &versatile_i2c_resource,
261 };
262
263 static struct i2c_board_info versatile_i2c_board_info[] = {
264 {
265 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
266 },
267 };
268
269 static int __init versatile_i2c_init(void)
270 {
271 return i2c_register_board_info(0, versatile_i2c_board_info,
272 ARRAY_SIZE(versatile_i2c_board_info));
273 }
274 arch_initcall(versatile_i2c_init);
275
276 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
277
278 unsigned int mmc_status(struct device *dev)
279 {
280 struct amba_device *adev = container_of(dev, struct amba_device, dev);
281 u32 mask;
282
283 if (adev->res.start == VERSATILE_MMCI0_BASE)
284 mask = 1;
285 else
286 mask = 2;
287
288 return readl(VERSATILE_SYSMCI) & mask;
289 }
290
291 static struct mmci_platform_data mmc0_plat_data = {
292 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
293 .status = mmc_status,
294 .gpio_wp = -1,
295 .gpio_cd = -1,
296 };
297
298 static struct resource char_lcd_resources[] = {
299 {
300 .start = VERSATILE_CHAR_LCD_BASE,
301 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
302 .flags = IORESOURCE_MEM,
303 },
304 };
305
306 static struct platform_device char_lcd_device = {
307 .name = "arm-charlcd",
308 .id = -1,
309 .num_resources = ARRAY_SIZE(char_lcd_resources),
310 .resource = char_lcd_resources,
311 };
312
313 /*
314 * Clock handling
315 */
316 static const struct icst_params versatile_oscvco_params = {
317 .ref = 24000000,
318 .vco_max = ICST307_VCO_MAX,
319 .vco_min = ICST307_VCO_MIN,
320 .vd_min = 4 + 8,
321 .vd_max = 511 + 8,
322 .rd_min = 1 + 2,
323 .rd_max = 127 + 2,
324 .s2div = icst307_s2div,
325 .idx2s = icst307_idx2s,
326 };
327
328 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
329 {
330 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
331 u32 val;
332
333 val = readl(clk->vcoreg) & ~0x7ffff;
334 val |= vco.v | (vco.r << 9) | (vco.s << 16);
335
336 writel(0xa05f, sys_lock);
337 writel(val, clk->vcoreg);
338 writel(0, sys_lock);
339 }
340
341 static const struct clk_ops osc4_clk_ops = {
342 .round = icst_clk_round,
343 .set = icst_clk_set,
344 .setvco = versatile_oscvco_set,
345 };
346
347 static struct clk osc4_clk = {
348 .ops = &osc4_clk_ops,
349 .params = &versatile_oscvco_params,
350 };
351
352 /*
353 * These are fixed clocks.
354 */
355 static struct clk ref24_clk = {
356 .rate = 24000000,
357 };
358
359 static struct clk sp804_clk = {
360 .rate = 1000000,
361 };
362
363 static struct clk dummy_apb_pclk;
364
365 static struct clk_lookup lookups[] = {
366 { /* AMBA bus clock */
367 .con_id = "apb_pclk",
368 .clk = &dummy_apb_pclk,
369 }, { /* UART0 */
370 .dev_id = "dev:f1",
371 .clk = &ref24_clk,
372 }, { /* UART1 */
373 .dev_id = "dev:f2",
374 .clk = &ref24_clk,
375 }, { /* UART2 */
376 .dev_id = "dev:f3",
377 .clk = &ref24_clk,
378 }, { /* UART3 */
379 .dev_id = "fpga:09",
380 .clk = &ref24_clk,
381 }, { /* KMI0 */
382 .dev_id = "fpga:06",
383 .clk = &ref24_clk,
384 }, { /* KMI1 */
385 .dev_id = "fpga:07",
386 .clk = &ref24_clk,
387 }, { /* MMC0 */
388 .dev_id = "fpga:05",
389 .clk = &ref24_clk,
390 }, { /* MMC1 */
391 .dev_id = "fpga:0b",
392 .clk = &ref24_clk,
393 }, { /* SSP */
394 .dev_id = "dev:f4",
395 .clk = &ref24_clk,
396 }, { /* CLCD */
397 .dev_id = "dev:20",
398 .clk = &osc4_clk,
399 }, { /* SP804 timers */
400 .dev_id = "sp804",
401 .clk = &sp804_clk,
402 },
403 };
404
405 /*
406 * CLCD support.
407 */
408 #define SYS_CLCD_MODE_MASK (3 << 0)
409 #define SYS_CLCD_MODE_888 (0 << 0)
410 #define SYS_CLCD_MODE_5551 (1 << 0)
411 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
412 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
413 #define SYS_CLCD_NLCDIOON (1 << 2)
414 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
415 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
416 #define SYS_CLCD_ID_MASK (0x1f << 8)
417 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
418 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
419 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
420 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
421 #define SYS_CLCD_ID_VGA (0x1f << 8)
422
423 static bool is_sanyo_2_5_lcd;
424
425 /*
426 * Disable all display connectors on the interface module.
427 */
428 static void versatile_clcd_disable(struct clcd_fb *fb)
429 {
430 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
431 u32 val;
432
433 val = readl(sys_clcd);
434 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
435 writel(val, sys_clcd);
436
437 #ifdef CONFIG_MACH_VERSATILE_AB
438 /*
439 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
440 */
441 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
442 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
443 unsigned long ctrl;
444
445 ctrl = readl(versatile_ib2_ctrl);
446 ctrl &= ~0x01;
447 writel(ctrl, versatile_ib2_ctrl);
448 }
449 #endif
450 }
451
452 /*
453 * Enable the relevant connector on the interface module.
454 */
455 static void versatile_clcd_enable(struct clcd_fb *fb)
456 {
457 struct fb_var_screeninfo *var = &fb->fb.var;
458 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
459 u32 val;
460
461 val = readl(sys_clcd);
462 val &= ~SYS_CLCD_MODE_MASK;
463
464 switch (var->green.length) {
465 case 5:
466 val |= SYS_CLCD_MODE_5551;
467 break;
468 case 6:
469 if (var->red.offset == 0)
470 val |= SYS_CLCD_MODE_565_RLSB;
471 else
472 val |= SYS_CLCD_MODE_565_BLSB;
473 break;
474 case 8:
475 val |= SYS_CLCD_MODE_888;
476 break;
477 }
478
479 /*
480 * Set the MUX
481 */
482 writel(val, sys_clcd);
483
484 /*
485 * And now enable the PSUs
486 */
487 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
488 writel(val, sys_clcd);
489
490 #ifdef CONFIG_MACH_VERSATILE_AB
491 /*
492 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
493 */
494 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
495 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
496 unsigned long ctrl;
497
498 ctrl = readl(versatile_ib2_ctrl);
499 ctrl |= 0x01;
500 writel(ctrl, versatile_ib2_ctrl);
501 }
502 #endif
503 }
504
505 /*
506 * Detect which LCD panel is connected, and return the appropriate
507 * clcd_panel structure. Note: we do not have any information on
508 * the required timings for the 8.4in panel, so we presently assume
509 * VGA timings.
510 */
511 static int versatile_clcd_setup(struct clcd_fb *fb)
512 {
513 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
514 const char *panel_name;
515 u32 val;
516
517 is_sanyo_2_5_lcd = false;
518
519 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
520 if (val == SYS_CLCD_ID_SANYO_3_8)
521 panel_name = "Sanyo TM38QV67A02A";
522 else if (val == SYS_CLCD_ID_SANYO_2_5) {
523 panel_name = "Sanyo QVGA Portrait";
524 is_sanyo_2_5_lcd = true;
525 } else if (val == SYS_CLCD_ID_EPSON_2_2)
526 panel_name = "Epson L2F50113T00";
527 else if (val == SYS_CLCD_ID_VGA)
528 panel_name = "VGA";
529 else {
530 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
531 val);
532 panel_name = "VGA";
533 }
534
535 fb->panel = versatile_clcd_get_panel(panel_name);
536 if (!fb->panel)
537 return -EINVAL;
538
539 return versatile_clcd_setup_dma(fb, SZ_1M);
540 }
541
542 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
543 {
544 clcdfb_decode(fb, regs);
545
546 /* Always clear BGR for RGB565: we do the routing externally */
547 if (fb->fb.var.green.length == 6)
548 regs->cntl &= ~CNTL_BGR;
549 }
550
551 static struct clcd_board clcd_plat_data = {
552 .name = "Versatile",
553 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
554 .check = clcdfb_check,
555 .decode = versatile_clcd_decode,
556 .disable = versatile_clcd_disable,
557 .enable = versatile_clcd_enable,
558 .setup = versatile_clcd_setup,
559 .mmap = versatile_clcd_mmap_dma,
560 .remove = versatile_clcd_remove_dma,
561 };
562
563 static struct pl061_platform_data gpio0_plat_data = {
564 .gpio_base = 0,
565 .irq_base = IRQ_GPIO0_START,
566 };
567
568 static struct pl061_platform_data gpio1_plat_data = {
569 .gpio_base = 8,
570 .irq_base = IRQ_GPIO1_START,
571 };
572
573 static struct pl022_ssp_controller ssp0_plat_data = {
574 .bus_id = 0,
575 .enable_dma = 0,
576 .num_chipselect = 1,
577 };
578
579 #define AACI_IRQ { IRQ_AACI }
580 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
581 #define KMI0_IRQ { IRQ_SIC_KMI0 }
582 #define KMI1_IRQ { IRQ_SIC_KMI1 }
583
584 /*
585 * These devices are connected directly to the multi-layer AHB switch
586 */
587 #define SMC_IRQ { }
588 #define MPMC_IRQ { }
589 #define CLCD_IRQ { IRQ_CLCDINT }
590 #define DMAC_IRQ { IRQ_DMAINT }
591
592 /*
593 * These devices are connected via the core APB bridge
594 */
595 #define SCTL_IRQ { }
596 #define WATCHDOG_IRQ { IRQ_WDOGINT }
597 #define GPIO0_IRQ { IRQ_GPIOINT0 }
598 #define GPIO1_IRQ { IRQ_GPIOINT1 }
599 #define RTC_IRQ { IRQ_RTCINT }
600
601 /*
602 * These devices are connected via the DMA APB bridge
603 */
604 #define SCI_IRQ { IRQ_SCIINT }
605 #define UART0_IRQ { IRQ_UARTINT0 }
606 #define UART1_IRQ { IRQ_UARTINT1 }
607 #define UART2_IRQ { IRQ_UARTINT2 }
608 #define SSP_IRQ { IRQ_SSPINT }
609
610 /* FPGA Primecells */
611 APB_DEVICE(aaci, "fpga:04", AACI, NULL);
612 APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
613 APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
614 APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
615
616 /* DevChip Primecells */
617 AHB_DEVICE(smc, "dev:00", SMC, NULL);
618 AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
619 AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
620 AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
621 APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
622 APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
623 APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
624 APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
625 APB_DEVICE(rtc, "dev:e8", RTC, NULL);
626 APB_DEVICE(sci0, "dev:f0", SCI, NULL);
627 APB_DEVICE(uart0, "dev:f1", UART0, NULL);
628 APB_DEVICE(uart1, "dev:f2", UART1, NULL);
629 APB_DEVICE(uart2, "dev:f3", UART2, NULL);
630 APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
631
632 static struct amba_device *amba_devs[] __initdata = {
633 &dmac_device,
634 &uart0_device,
635 &uart1_device,
636 &uart2_device,
637 &smc_device,
638 &mpmc_device,
639 &clcd_device,
640 &sctl_device,
641 &wdog_device,
642 &gpio0_device,
643 &gpio1_device,
644 &rtc_device,
645 &sci0_device,
646 &ssp0_device,
647 &aaci_device,
648 &mmc0_device,
649 &kmi0_device,
650 &kmi1_device,
651 };
652
653 #ifdef CONFIG_OF
654 /*
655 * Lookup table for attaching a specific name and platform_data pointer to
656 * devices as they get created by of_platform_populate(). Ideally this table
657 * would not exist, but the current clock implementation depends on some devices
658 * having a specific name.
659 */
660 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
661 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
662 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
663 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
664 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
665 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
666 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
667
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
673
674 #if 0
675 /*
676 * These entries are unnecessary because no clocks referencing
677 * them. I've left them in for now as place holders in case
678 * any of them need to be added back, but they should be
679 * removed before actually committing this patch. --gcl
680 */
681 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
682 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
683 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
684 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
685 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
686
687 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
691 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
695 #endif
696 {}
697 };
698 #endif
699
700 #ifdef CONFIG_LEDS
701 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
702
703 static void versatile_leds_event(led_event_t ledevt)
704 {
705 unsigned long flags;
706 u32 val;
707
708 local_irq_save(flags);
709 val = readl(VA_LEDS_BASE);
710
711 switch (ledevt) {
712 case led_idle_start:
713 val = val & ~VERSATILE_SYS_LED0;
714 break;
715
716 case led_idle_end:
717 val = val | VERSATILE_SYS_LED0;
718 break;
719
720 case led_timer:
721 val = val ^ VERSATILE_SYS_LED1;
722 break;
723
724 case led_halted:
725 val = 0;
726 break;
727
728 default:
729 break;
730 }
731
732 writel(val, VA_LEDS_BASE);
733 local_irq_restore(flags);
734 }
735 #endif /* CONFIG_LEDS */
736
737 void versatile_restart(enum reboot_mode mode, const char *cmd)
738 {
739 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
740 u32 val;
741
742 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
743 val |= 0x105;
744
745 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
746 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
747 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
748 }
749
750 /* Early initializations */
751 void __init versatile_init_early(void)
752 {
753 u32 val;
754 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
755
756 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
757 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
758
759 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
760
761 /*
762 * set clock frequency:
763 * VERSATILE_REFCLK is 32KHz
764 * VERSATILE_TIMCLK is 1MHz
765 */
766 val = readl(__io_address(VERSATILE_SCTL_BASE));
767 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
768 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
769 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
770 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
771 __io_address(VERSATILE_SCTL_BASE));
772 }
773
774 void __init versatile_init(void)
775 {
776 int i;
777
778 platform_device_register(&versatile_flash_device);
779 platform_device_register(&versatile_i2c_device);
780 platform_device_register(&smc91x_device);
781 platform_device_register(&char_lcd_device);
782
783 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
784 struct amba_device *d = amba_devs[i];
785 amba_device_register(d, &iomem_resource);
786 }
787 }
788
789 /*
790 * Where is the timer (VA)?
791 */
792 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
793 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
794 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
795 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
796
797 /*
798 * Set up timer interrupt, and return the current time in seconds.
799 */
800 void __init versatile_timer_init(void)
801 {
802
803 /*
804 * Initialise to a known state (all timers off)
805 */
806 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
807 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
808 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
809 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
810
811 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
812 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
813 }
Linux with added FPC-III support