arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #define pr_fmt(fmt) "hw perfevents: " fmt
  22
  23 #include <linux/bitmap.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/export.h>
  27 #include <linux/perf_event.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/uaccess.h>
  31
  32 #include <asm/cputype.h>
  33 #include <asm/irq.h>
  34 #include <asm/irq_regs.h>
  35 #include <asm/pmu.h>
  36 #include <asm/stacktrace.h>
  37
  38 /*
  39  * ARMv8 supports a maximum of 32 events.
  40  * The cycle counter is included in this total.
  41  */
  42 #define ARMPMU_MAX_HWEVENTS             32
  43
  44 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
  45 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
  46 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
  47
  48 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
  49
  50 /* Set at runtime when we know what CPU type we are. */
  51 static struct arm_pmu *cpu_pmu;
  52
  53 int
  54 armpmu_get_max_events(void)
  55 {
  56         int max_events = 0;
  57
  58         if (cpu_pmu != NULL)
  59                 max_events = cpu_pmu->num_events;
  60
  61         return max_events;
  62 }
  63 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
  64
  65 int perf_num_counters(void)
  66 {
  67         return armpmu_get_max_events();
  68 }
  69 EXPORT_SYMBOL_GPL(perf_num_counters);
  70
  71 #define HW_OP_UNSUPPORTED               0xFFFF
  72
  73 #define C(_x) \
  74         PERF_COUNT_HW_CACHE_##_x
  75
  76 #define CACHE_OP_UNSUPPORTED            0xFFFF
  77
  78 static int
  79 armpmu_map_cache_event(const unsigned (*cache_map)
  80                                       [PERF_COUNT_HW_CACHE_MAX]
  81                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  82                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  83                        u64 config)
  84 {
  85         unsigned int cache_type, cache_op, cache_result, ret;
  86
  87         cache_type = (config >>  0) & 0xff;
  88         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  89                 return -EINVAL;
  90
  91         cache_op = (config >>  8) & 0xff;
  92         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  93                 return -EINVAL;
  94
  95         cache_result = (config >> 16) & 0xff;
  96         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  97                 return -EINVAL;
  98
  99         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 100
 101         if (ret == CACHE_OP_UNSUPPORTED)
 102                 return -ENOENT;
 103
 104         return ret;
 105 }
 106
 107 static int
 108 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 109 {
 110         int mapping;
 111
 112         if (config >= PERF_COUNT_HW_MAX)
 113                 return -EINVAL;
 114
 115         mapping = (*event_map)[config];
 116         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 117 }
 118
 119 static int
 120 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 121 {
 122         return (int)(config & raw_event_mask);
 123 }
 124
 125 static int map_cpu_event(struct perf_event *event,
 126                          const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 127                          const unsigned (*cache_map)
 128                                         [PERF_COUNT_HW_CACHE_MAX]
 129                                         [PERF_COUNT_HW_CACHE_OP_MAX]
 130                                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
 131                          u32 raw_event_mask)
 132 {
 133         u64 config = event->attr.config;
 134
 135         switch (event->attr.type) {
 136         case PERF_TYPE_HARDWARE:
 137                 return armpmu_map_event(event_map, config);
 138         case PERF_TYPE_HW_CACHE:
 139                 return armpmu_map_cache_event(cache_map, config);
 140         case PERF_TYPE_RAW:
 141                 return armpmu_map_raw_event(raw_event_mask, config);
 142         }
 143
 144         return -ENOENT;
 145 }
 146
 147 int
 148 armpmu_event_set_period(struct perf_event *event,
 149                         struct hw_perf_event *hwc,
 150                         int idx)
 151 {
 152         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 153         s64 left = local64_read(&hwc->period_left);
 154         s64 period = hwc->sample_period;
 155         int ret = 0;
 156
 157         if (unlikely(left <= -period)) {
 158                 left = period;
 159                 local64_set(&hwc->period_left, left);
 160                 hwc->last_period = period;
 161                 ret = 1;
 162         }
 163
 164         if (unlikely(left <= 0)) {
 165                 left += period;
 166                 local64_set(&hwc->period_left, left);
 167                 hwc->last_period = period;
 168                 ret = 1;
 169         }
 170
 171         if (left > (s64)armpmu->max_period)
 172                 left = armpmu->max_period;
 173
 174         local64_set(&hwc->prev_count, (u64)-left);
 175
 176         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 177
 178         perf_event_update_userpage(event);
 179
 180         return ret;
 181 }
 182
 183 u64
 184 armpmu_event_update(struct perf_event *event,
 185                     struct hw_perf_event *hwc,
 186                     int idx)
 187 {
 188         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 189         u64 delta, prev_raw_count, new_raw_count;
 190
 191 again:
 192         prev_raw_count = local64_read(&hwc->prev_count);
 193         new_raw_count = armpmu->read_counter(idx);
 194
 195         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 196                              new_raw_count) != prev_raw_count)
 197                 goto again;
 198
 199         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 200
 201         local64_add(delta, &event->count);
 202         local64_sub(delta, &hwc->period_left);
 203
 204         return new_raw_count;
 205 }
 206
 207 static void
 208 armpmu_read(struct perf_event *event)
 209 {
 210         struct hw_perf_event *hwc = &event->hw;
 211
 212         /* Don't read disabled counters! */
 213         if (hwc->idx < 0)
 214                 return;
 215
 216         armpmu_event_update(event, hwc, hwc->idx);
 217 }
 218
 219 static void
 220 armpmu_stop(struct perf_event *event, int flags)
 221 {
 222         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 223         struct hw_perf_event *hwc = &event->hw;
 224
 225         /*
 226          * ARM pmu always has to update the counter, so ignore
 227          * PERF_EF_UPDATE, see comments in armpmu_start().
 228          */
 229         if (!(hwc->state & PERF_HES_STOPPED)) {
 230                 armpmu->disable(hwc, hwc->idx);
 231                 barrier(); /* why? */
 232                 armpmu_event_update(event, hwc, hwc->idx);
 233                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 234         }
 235 }
 236
 237 static void
 238 armpmu_start(struct perf_event *event, int flags)
 239 {
 240         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 241         struct hw_perf_event *hwc = &event->hw;
 242
 243         /*
 244          * ARM pmu always has to reprogram the period, so ignore
 245          * PERF_EF_RELOAD, see the comment below.
 246          */
 247         if (flags & PERF_EF_RELOAD)
 248                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 249
 250         hwc->state = 0;
 251         /*
 252          * Set the period again. Some counters can't be stopped, so when we
 253          * were stopped we simply disabled the IRQ source and the counter
 254          * may have been left counting. If we don't do this step then we may
 255          * get an interrupt too soon or *way* too late if the overflow has
 256          * happened since disabling.
 257          */
 258         armpmu_event_set_period(event, hwc, hwc->idx);
 259         armpmu->enable(hwc, hwc->idx);
 260 }
 261
 262 static void
 263 armpmu_del(struct perf_event *event, int flags)
 264 {
 265         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 266         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 267         struct hw_perf_event *hwc = &event->hw;
 268         int idx = hwc->idx;
 269
 270         WARN_ON(idx < 0);
 271
 272         armpmu_stop(event, PERF_EF_UPDATE);
 273         hw_events->events[idx] = NULL;
 274         clear_bit(idx, hw_events->used_mask);
 275
 276         perf_event_update_userpage(event);
 277 }
 278
 279 static int
 280 armpmu_add(struct perf_event *event, int flags)
 281 {
 282         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 283         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 284         struct hw_perf_event *hwc = &event->hw;
 285         int idx;
 286         int err = 0;
 287
 288         perf_pmu_disable(event->pmu);
 289
 290         /* If we don't have a space for the counter then finish early. */
 291         idx = armpmu->get_event_idx(hw_events, hwc);
 292         if (idx < 0) {
 293                 err = idx;
 294                 goto out;
 295         }
 296
 297         /*
 298          * If there is an event in the counter we are going to use then make
 299          * sure it is disabled.
 300          */
 301         event->hw.idx = idx;
 302         armpmu->disable(hwc, idx);
 303         hw_events->events[idx] = event;
 304
 305         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 306         if (flags & PERF_EF_START)
 307                 armpmu_start(event, PERF_EF_RELOAD);
 308
 309         /* Propagate our changes to the userspace mapping. */
 310         perf_event_update_userpage(event);
 311
 312 out:
 313         perf_pmu_enable(event->pmu);
 314         return err;
 315 }
 316
 317 static int
 318 validate_event(struct pmu_hw_events *hw_events,
 319                struct perf_event *event)
 320 {
 321         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 322         struct hw_perf_event fake_event = event->hw;
 323         struct pmu *leader_pmu = event->group_leader->pmu;
 324
 325         if (is_software_event(event))
 326                 return 1;
 327
 328         if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
 329                 return 1;
 330
 331         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 332                 return 1;
 333
 334         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 335 }
 336
 337 static int
 338 validate_group(struct perf_event *event)
 339 {
 340         struct perf_event *sibling, *leader = event->group_leader;
 341         struct pmu_hw_events fake_pmu;
 342         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 343
 344         /*
 345          * Initialise the fake PMU. We only need to populate the
 346          * used_mask for the purposes of validation.
 347          */
 348         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 349         fake_pmu.used_mask = fake_used_mask;
 350
 351         if (!validate_event(&fake_pmu, leader))
 352                 return -EINVAL;
 353
 354         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 355                 if (!validate_event(&fake_pmu, sibling))
 356                         return -EINVAL;
 357         }
 358
 359         if (!validate_event(&fake_pmu, event))
 360                 return -EINVAL;
 361
 362         return 0;
 363 }
 364
 365 static void
 366 armpmu_release_hardware(struct arm_pmu *armpmu)
 367 {
 368         int i, irq, irqs;
 369         struct platform_device *pmu_device = armpmu->plat_device;
 370
 371         irqs = min(pmu_device->num_resources, num_possible_cpus());
 372
 373         for (i = 0; i < irqs; ++i) {
 374                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 375                         continue;
 376                 irq = platform_get_irq(pmu_device, i);
 377                 if (irq >= 0)
 378                         free_irq(irq, armpmu);
 379         }
 380 }
 381
 382 static int
 383 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 384 {
 385         int i, err, irq, irqs;
 386         struct platform_device *pmu_device = armpmu->plat_device;
 387
 388         if (!pmu_device) {
 389                 pr_err("no PMU device registered\n");
 390                 return -ENODEV;
 391         }
 392
 393         irqs = min(pmu_device->num_resources, num_possible_cpus());
 394         if (irqs < 1) {
 395                 pr_err("no irqs for PMUs defined\n");
 396                 return -ENODEV;
 397         }
 398
 399         for (i = 0; i < irqs; ++i) {
 400                 err = 0;
 401                 irq = platform_get_irq(pmu_device, i);
 402                 if (irq < 0)
 403                         continue;
 404
 405                 /*
 406                  * If we have a single PMU interrupt that we can't shift,
 407                  * assume that we're running on a uniprocessor machine and
 408                  * continue. Otherwise, continue without this interrupt.
 409                  */
 410                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 411                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 412                                     irq, i);
 413                         continue;
 414                 }
 415
 416                 err = request_irq(irq, armpmu->handle_irq,
 417                                   IRQF_NOBALANCING,
 418                                   "arm-pmu", armpmu);
 419                 if (err) {
 420                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 421                                 irq);
 422                         armpmu_release_hardware(armpmu);
 423                         return err;
 424                 }
 425
 426                 cpumask_set_cpu(i, &armpmu->active_irqs);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static void
 433 hw_perf_event_destroy(struct perf_event *event)
 434 {
 435         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 436         atomic_t *active_events  = &armpmu->active_events;
 437         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 438
 439         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 440                 armpmu_release_hardware(armpmu);
 441                 mutex_unlock(pmu_reserve_mutex);
 442         }
 443 }
 444
 445 static int
 446 event_requires_mode_exclusion(struct perf_event_attr *attr)
 447 {
 448         return attr->exclude_idle || attr->exclude_user ||
 449                attr->exclude_kernel || attr->exclude_hv;
 450 }
 451
 452 static int
 453 __hw_perf_event_init(struct perf_event *event)
 454 {
 455         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 456         struct hw_perf_event *hwc = &event->hw;
 457         int mapping, err;
 458
 459         mapping = armpmu->map_event(event);
 460
 461         if (mapping < 0) {
 462                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 463                          event->attr.config);
 464                 return mapping;
 465         }
 466
 467         /*
 468          * We don't assign an index until we actually place the event onto
 469          * hardware. Use -1 to signify that we haven't decided where to put it
 470          * yet. For SMP systems, each core has it's own PMU so we can't do any
 471          * clever allocation or constraints checking at this point.
 472          */
 473         hwc->idx                = -1;
 474         hwc->config_base        = 0;
 475         hwc->config             = 0;
 476         hwc->event_base         = 0;
 477
 478         /*
 479          * Check whether we need to exclude the counter from certain modes.
 480          */
 481         if ((!armpmu->set_event_filter ||
 482              armpmu->set_event_filter(hwc, &event->attr)) &&
 483              event_requires_mode_exclusion(&event->attr)) {
 484                 pr_debug("ARM performance counters do not support mode exclusion\n");
 485                 return -EPERM;
 486         }
 487
 488         /*
 489          * Store the event encoding into the config_base field.
 490          */
 491         hwc->config_base            |= (unsigned long)mapping;
 492
 493         if (!hwc->sample_period) {
 494                 /*
 495                  * For non-sampling runs, limit the sample_period to half
 496                  * of the counter width. That way, the new counter value
 497                  * is far less likely to overtake the previous one unless
 498                  * you have some serious IRQ latency issues.
 499                  */
 500                 hwc->sample_period  = armpmu->max_period >> 1;
 501                 hwc->last_period    = hwc->sample_period;
 502                 local64_set(&hwc->period_left, hwc->sample_period);
 503         }
 504
 505         err = 0;
 506         if (event->group_leader != event) {
 507                 err = validate_group(event);
 508                 if (err)
 509                         return -EINVAL;
 510         }
 511
 512         return err;
 513 }
 514
 515 static int armpmu_event_init(struct perf_event *event)
 516 {
 517         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 518         int err = 0;
 519         atomic_t *active_events = &armpmu->active_events;
 520
 521         if (armpmu->map_event(event) == -ENOENT)
 522                 return -ENOENT;
 523
 524         event->destroy = hw_perf_event_destroy;
 525
 526         if (!atomic_inc_not_zero(active_events)) {
 527                 mutex_lock(&armpmu->reserve_mutex);
 528                 if (atomic_read(active_events) == 0)
 529                         err = armpmu_reserve_hardware(armpmu);
 530
 531                 if (!err)
 532                         atomic_inc(active_events);
 533                 mutex_unlock(&armpmu->reserve_mutex);
 534         }
 535
 536         if (err)
 537                 return err;
 538
 539         err = __hw_perf_event_init(event);
 540         if (err)
 541                 hw_perf_event_destroy(event);
 542
 543         return err;
 544 }
 545
 546 static void armpmu_enable(struct pmu *pmu)
 547 {
 548         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 549         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 550         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 551
 552         if (enabled)
 553                 armpmu->start();
 554 }
 555
 556 static void armpmu_disable(struct pmu *pmu)
 557 {
 558         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 559         armpmu->stop();
 560 }
 561
 562 static void __init armpmu_init(struct arm_pmu *armpmu)
 563 {
 564         atomic_set(&armpmu->active_events, 0);
 565         mutex_init(&armpmu->reserve_mutex);
 566
 567         armpmu->pmu = (struct pmu) {
 568                 .pmu_enable     = armpmu_enable,
 569                 .pmu_disable    = armpmu_disable,
 570                 .event_init     = armpmu_event_init,
 571                 .add            = armpmu_add,
 572                 .del            = armpmu_del,
 573                 .start          = armpmu_start,
 574                 .stop           = armpmu_stop,
 575                 .read           = armpmu_read,
 576         };
 577 }
 578
 579 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 580 {
 581         armpmu_init(armpmu);
 582         return perf_pmu_register(&armpmu->pmu, name, type);
 583 }
 584
 585 /*
 586  * ARMv8 PMUv3 Performance Events handling code.
 587  * Common event types.
 588  */
 589 enum armv8_pmuv3_perf_types {
 590         /* Required events. */
 591         ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR                        = 0x00,
 592         ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL                    = 0x03,
 593         ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS                    = 0x04,
 594         ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED                  = 0x10,
 595         ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES                        = 0x11,
 596         ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED                      = 0x12,
 597
 598         /* At least one of the following is required. */
 599         ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED                      = 0x08,
 600         ARMV8_PMUV3_PERFCTR_OP_SPEC                             = 0x1B,
 601
 602         /* Common architectural events. */
 603         ARMV8_PMUV3_PERFCTR_MEM_READ                            = 0x06,
 604         ARMV8_PMUV3_PERFCTR_MEM_WRITE                           = 0x07,
 605         ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           = 0x09,
 606         ARMV8_PMUV3_PERFCTR_EXC_EXECUTED                        = 0x0A,
 607         ARMV8_PMUV3_PERFCTR_CID_WRITE                           = 0x0B,
 608         ARMV8_PMUV3_PERFCTR_PC_WRITE                            = 0x0C,
 609         ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH                       = 0x0D,
 610         ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN                      = 0x0E,
 611         ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS                = 0x0F,
 612         ARMV8_PMUV3_PERFCTR_TTBR_WRITE                          = 0x1C,
 613
 614         /* Common microarchitectural events. */
 615         ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL                    = 0x01,
 616         ARMV8_PMUV3_PERFCTR_ITLB_REFILL                         = 0x02,
 617         ARMV8_PMUV3_PERFCTR_DTLB_REFILL                         = 0x05,
 618         ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          = 0x13,
 619         ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS                    = 0x14,
 620         ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB                        = 0x15,
 621         ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS                     = 0x16,
 622         ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL                     = 0x17,
 623         ARMV8_PMUV3_PERFCTR_L2_CACHE_WB                         = 0x18,
 624         ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          = 0x19,
 625         ARMV8_PMUV3_PERFCTR_MEM_ERROR                           = 0x1A,
 626         ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          = 0x1D,
 627 };
 628
 629 /* PMUv3 HW events mapping. */
 630 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 631         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 632         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 633         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 634         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 635         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = HW_OP_UNSUPPORTED,
 636         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 637         [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
 638         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
 639         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 640 };
 641
 642 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 643                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 644                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 645         [C(L1D)] = {
 646                 [C(OP_READ)] = {
 647                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 648                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 649                 },
 650                 [C(OP_WRITE)] = {
 651                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 652                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 653                 },
 654                 [C(OP_PREFETCH)] = {
 655                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 656                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 657                 },
 658         },
 659         [C(L1I)] = {
 660                 [C(OP_READ)] = {
 661                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 662                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 663                 },
 664                 [C(OP_WRITE)] = {
 665                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 666                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 667                 },
 668                 [C(OP_PREFETCH)] = {
 669                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 670                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 671                 },
 672         },
 673         [C(LL)] = {
 674                 [C(OP_READ)] = {
 675                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 676                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 677                 },
 678                 [C(OP_WRITE)] = {
 679                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 680                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 681                 },
 682                 [C(OP_PREFETCH)] = {
 683                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 684                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 685                 },
 686         },
 687         [C(DTLB)] = {
 688                 [C(OP_READ)] = {
 689                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 690                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 691                 },
 692                 [C(OP_WRITE)] = {
 693                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 694                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 695                 },
 696                 [C(OP_PREFETCH)] = {
 697                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 698                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 699                 },
 700         },
 701         [C(ITLB)] = {
 702                 [C(OP_READ)] = {
 703                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 704                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 705                 },
 706                 [C(OP_WRITE)] = {
 707                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 708                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 709                 },
 710                 [C(OP_PREFETCH)] = {
 711                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 712                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 713                 },
 714         },
 715         [C(BPU)] = {
 716                 [C(OP_READ)] = {
 717                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 718                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 719                 },
 720                 [C(OP_WRITE)] = {
 721                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 722                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 723                 },
 724                 [C(OP_PREFETCH)] = {
 725                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 726                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 727                 },
 728         },
 729         [C(NODE)] = {
 730                 [C(OP_READ)] = {
 731                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 732                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 733                 },
 734                 [C(OP_WRITE)] = {
 735                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 736                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 737                 },
 738                 [C(OP_PREFETCH)] = {
 739                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 740                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 741                 },
 742         },
 743 };
 744
 745 /*
 746  * Perf Events' indices
 747  */
 748 #define ARMV8_IDX_CYCLE_COUNTER 0
 749 #define ARMV8_IDX_COUNTER0      1
 750 #define ARMV8_IDX_COUNTER_LAST  (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 751
 752 #define ARMV8_MAX_COUNTERS      32
 753 #define ARMV8_COUNTER_MASK      (ARMV8_MAX_COUNTERS - 1)
 754
 755 /*
 756  * ARMv8 low level PMU access
 757  */
 758
 759 /*
 760  * Perf Event to low level counters mapping
 761  */
 762 #define ARMV8_IDX_TO_COUNTER(x) \
 763         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
 764
 765 /*
 766  * Per-CPU PMCR: config reg
 767  */
 768 #define ARMV8_PMCR_E            (1 << 0) /* Enable all counters */
 769 #define ARMV8_PMCR_P            (1 << 1) /* Reset all counters */
 770 #define ARMV8_PMCR_C            (1 << 2) /* Cycle counter reset */
 771 #define ARMV8_PMCR_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
 772 #define ARMV8_PMCR_X            (1 << 4) /* Export to ETM */
 773 #define ARMV8_PMCR_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
 774 #define ARMV8_PMCR_N_SHIFT      11       /* Number of counters supported */
 775 #define ARMV8_PMCR_N_MASK       0x1f
 776 #define ARMV8_PMCR_MASK         0x3f     /* Mask for writable bits */
 777
 778 /*
 779  * PMOVSR: counters overflow flag status reg
 780  */
 781 #define ARMV8_OVSR_MASK         0xffffffff      /* Mask for writable bits */
 782 #define ARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
 783
 784 /*
 785  * PMXEVTYPER: Event selection reg
 786  */
 787 #define ARMV8_EVTYPE_MASK       0xc80000ff      /* Mask for writable bits */
 788 #define ARMV8_EVTYPE_EVENT      0xff            /* Mask for EVENT bits */
 789
 790 /*
 791  * Event filters for PMUv3
 792  */
 793 #define ARMV8_EXCLUDE_EL1       (1 << 31)
 794 #define ARMV8_EXCLUDE_EL0       (1 << 30)
 795 #define ARMV8_INCLUDE_EL2       (1 << 27)
 796
 797 static inline u32 armv8pmu_pmcr_read(void)
 798 {
 799         u32 val;
 800         asm volatile("mrs %0, pmcr_el0" : "=r" (val));
 801         return val;
 802 }
 803
 804 static inline void armv8pmu_pmcr_write(u32 val)
 805 {
 806         val &= ARMV8_PMCR_MASK;
 807         isb();
 808         asm volatile("msr pmcr_el0, %0" :: "r" (val));
 809 }
 810
 811 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 812 {
 813         return pmovsr & ARMV8_OVERFLOWED_MASK;
 814 }
 815
 816 static inline int armv8pmu_counter_valid(int idx)
 817 {
 818         return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
 819 }
 820
 821 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 822 {
 823         int ret = 0;
 824         u32 counter;
 825
 826         if (!armv8pmu_counter_valid(idx)) {
 827                 pr_err("CPU%u checking wrong counter %d overflow status\n",
 828                         smp_processor_id(), idx);
 829         } else {
 830                 counter = ARMV8_IDX_TO_COUNTER(idx);
 831                 ret = pmnc & BIT(counter);
 832         }
 833
 834         return ret;
 835 }
 836
 837 static inline int armv8pmu_select_counter(int idx)
 838 {
 839         u32 counter;
 840
 841         if (!armv8pmu_counter_valid(idx)) {
 842                 pr_err("CPU%u selecting wrong PMNC counter %d\n",
 843                         smp_processor_id(), idx);
 844                 return -EINVAL;
 845         }
 846
 847         counter = ARMV8_IDX_TO_COUNTER(idx);
 848         asm volatile("msr pmselr_el0, %0" :: "r" (counter));
 849         isb();
 850
 851         return idx;
 852 }
 853
 854 static inline u32 armv8pmu_read_counter(int idx)
 855 {
 856         u32 value = 0;
 857
 858         if (!armv8pmu_counter_valid(idx))
 859                 pr_err("CPU%u reading wrong counter %d\n",
 860                         smp_processor_id(), idx);
 861         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 862                 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
 863         else if (armv8pmu_select_counter(idx) == idx)
 864                 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
 865
 866         return value;
 867 }
 868
 869 static inline void armv8pmu_write_counter(int idx, u32 value)
 870 {
 871         if (!armv8pmu_counter_valid(idx))
 872                 pr_err("CPU%u writing wrong counter %d\n",
 873                         smp_processor_id(), idx);
 874         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 875                 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
 876         else if (armv8pmu_select_counter(idx) == idx)
 877                 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
 878 }
 879
 880 static inline void armv8pmu_write_evtype(int idx, u32 val)
 881 {
 882         if (armv8pmu_select_counter(idx) == idx) {
 883                 val &= ARMV8_EVTYPE_MASK;
 884                 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
 885         }
 886 }
 887
 888 static inline int armv8pmu_enable_counter(int idx)
 889 {
 890         u32 counter;
 891
 892         if (!armv8pmu_counter_valid(idx)) {
 893                 pr_err("CPU%u enabling wrong PMNC counter %d\n",
 894                         smp_processor_id(), idx);
 895                 return -EINVAL;
 896         }
 897
 898         counter = ARMV8_IDX_TO_COUNTER(idx);
 899         asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
 900         return idx;
 901 }
 902
 903 static inline int armv8pmu_disable_counter(int idx)
 904 {
 905         u32 counter;
 906
 907         if (!armv8pmu_counter_valid(idx)) {
 908                 pr_err("CPU%u disabling wrong PMNC counter %d\n",
 909                         smp_processor_id(), idx);
 910                 return -EINVAL;
 911         }
 912
 913         counter = ARMV8_IDX_TO_COUNTER(idx);
 914         asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
 915         return idx;
 916 }
 917
 918 static inline int armv8pmu_enable_intens(int idx)
 919 {
 920         u32 counter;
 921
 922         if (!armv8pmu_counter_valid(idx)) {
 923                 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
 924                         smp_processor_id(), idx);
 925                 return -EINVAL;
 926         }
 927
 928         counter = ARMV8_IDX_TO_COUNTER(idx);
 929         asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
 930         return idx;
 931 }
 932
 933 static inline int armv8pmu_disable_intens(int idx)
 934 {
 935         u32 counter;
 936
 937         if (!armv8pmu_counter_valid(idx)) {
 938                 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
 939                         smp_processor_id(), idx);
 940                 return -EINVAL;
 941         }
 942
 943         counter = ARMV8_IDX_TO_COUNTER(idx);
 944         asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
 945         isb();
 946         /* Clear the overflow flag in case an interrupt is pending. */
 947         asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
 948         isb();
 949         return idx;
 950 }
 951
 952 static inline u32 armv8pmu_getreset_flags(void)
 953 {
 954         u32 value;
 955
 956         /* Read */
 957         asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
 958
 959         /* Write to clear flags */
 960         value &= ARMV8_OVSR_MASK;
 961         asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
 962
 963         return value;
 964 }
 965
 966 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
 967 {
 968         unsigned long flags;
 969         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 970
 971         /*
 972          * Enable counter and interrupt, and set the counter to count
 973          * the event that we're interested in.
 974          */
 975         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 976
 977         /*
 978          * Disable counter
 979          */
 980         armv8pmu_disable_counter(idx);
 981
 982         /*
 983          * Set event (if destined for PMNx counters).
 984          */
 985         armv8pmu_write_evtype(idx, hwc->config_base);
 986
 987         /*
 988          * Enable interrupt for this counter
 989          */
 990         armv8pmu_enable_intens(idx);
 991
 992         /*
 993          * Enable counter
 994          */
 995         armv8pmu_enable_counter(idx);
 996
 997         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 998 }
 999
1000 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
1001 {
1002         unsigned long flags;
1003         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1004
1005         /*
1006          * Disable counter and interrupt
1007          */
1008         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1009
1010         /*
1011          * Disable counter
1012          */
1013         armv8pmu_disable_counter(idx);
1014
1015         /*
1016          * Disable interrupt for this counter
1017          */
1018         armv8pmu_disable_intens(idx);
1019
1020         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1021 }
1022
1023 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
1024 {
1025         u32 pmovsr;
1026         struct perf_sample_data data;
1027         struct pmu_hw_events *cpuc;
1028         struct pt_regs *regs;
1029         int idx;
1030
1031         /*
1032          * Get and reset the IRQ flags
1033          */
1034         pmovsr = armv8pmu_getreset_flags();
1035
1036         /*
1037          * Did an overflow occur?
1038          */
1039         if (!armv8pmu_has_overflowed(pmovsr))
1040                 return IRQ_NONE;
1041
1042         /*
1043          * Handle the counter(s) overflow(s)
1044          */
1045         regs = get_irq_regs();
1046
1047         cpuc = &__get_cpu_var(cpu_hw_events);
1048         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1049                 struct perf_event *event = cpuc->events[idx];
1050                 struct hw_perf_event *hwc;
1051
1052                 /* Ignore if we don't have an event. */
1053                 if (!event)
1054                         continue;
1055
1056                 /*
1057                  * We have a single interrupt for all counters. Check that
1058                  * each counter has overflowed before we process it.
1059                  */
1060                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
1061                         continue;
1062
1063                 hwc = &event->hw;
1064                 armpmu_event_update(event, hwc, idx);
1065                 perf_sample_data_init(&data, 0, hwc->last_period);
1066                 if (!armpmu_event_set_period(event, hwc, idx))
1067                         continue;
1068
1069                 if (perf_event_overflow(event, &data, regs))
1070                         cpu_pmu->disable(hwc, idx);
1071         }
1072
1073         /*
1074          * Handle the pending perf events.
1075          *
1076          * Note: this call *must* be run with interrupts disabled. For
1077          * platforms that can have the PMU interrupts raised as an NMI, this
1078          * will not work.
1079          */
1080         irq_work_run();
1081
1082         return IRQ_HANDLED;
1083 }
1084
1085 static void armv8pmu_start(void)
1086 {
1087         unsigned long flags;
1088         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1089
1090         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1091         /* Enable all counters */
1092         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
1093         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1094 }
1095
1096 static void armv8pmu_stop(void)
1097 {
1098         unsigned long flags;
1099         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1100
1101         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1102         /* Disable all counters */
1103         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
1104         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1105 }
1106
1107 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1108                                   struct hw_perf_event *event)
1109 {
1110         int idx;
1111         unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1112
1113         /* Always place a cycle counter into the cycle counter. */
1114         if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1115                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1116                         return -EAGAIN;
1117
1118                 return ARMV8_IDX_CYCLE_COUNTER;
1119         }
1120
1121         /*
1122          * For anything other than a cycle counter, try and use
1123          * the events counters
1124          */
1125         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1126                 if (!test_and_set_bit(idx, cpuc->used_mask))
1127                         return idx;
1128         }
1129
1130         /* The counters are all in use. */
1131         return -EAGAIN;
1132 }
1133
1134 /*
1135  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1136  */
1137 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1138                                      struct perf_event_attr *attr)
1139 {
1140         unsigned long config_base = 0;
1141
1142         if (attr->exclude_idle)
1143                 return -EPERM;
1144         if (attr->exclude_user)
1145                 config_base |= ARMV8_EXCLUDE_EL0;
1146         if (attr->exclude_kernel)
1147                 config_base |= ARMV8_EXCLUDE_EL1;
1148         if (!attr->exclude_hv)
1149                 config_base |= ARMV8_INCLUDE_EL2;
1150
1151         /*
1152          * Install the filter into config_base as this is used to
1153          * construct the event type.
1154          */
1155         event->config_base = config_base;
1156
1157         return 0;
1158 }
1159
1160 static void armv8pmu_reset(void *info)
1161 {
1162         u32 idx, nb_cnt = cpu_pmu->num_events;
1163
1164         /* The counter and interrupt enable registers are unknown at reset. */
1165         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1166                 armv8pmu_disable_event(NULL, idx);
1167
1168         /* Initialize & Reset PMNC: C and P bits. */
1169         armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
1170
1171         /* Disable access from userspace. */
1172         asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
1173 }
1174
1175 static int armv8_pmuv3_map_event(struct perf_event *event)
1176 {
1177         return map_cpu_event(event, &armv8_pmuv3_perf_map,
1178                                 &armv8_pmuv3_perf_cache_map, 0xFF);
1179 }
1180
1181 static struct arm_pmu armv8pmu = {
1182         .handle_irq             = armv8pmu_handle_irq,
1183         .enable                 = armv8pmu_enable_event,
1184         .disable                = armv8pmu_disable_event,
1185         .read_counter           = armv8pmu_read_counter,
1186         .write_counter          = armv8pmu_write_counter,
1187         .get_event_idx          = armv8pmu_get_event_idx,
1188         .start                  = armv8pmu_start,
1189         .stop                   = armv8pmu_stop,
1190         .reset                  = armv8pmu_reset,
1191         .max_period             = (1LLU << 32) - 1,
1192 };
1193
1194 static u32 __init armv8pmu_read_num_pmnc_events(void)
1195 {
1196         u32 nb_cnt;
1197
1198         /* Read the nb of CNTx counters supported from PMNC */
1199         nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
1200
1201         /* Add the CPU cycles counter and return */
1202         return nb_cnt + 1;
1203 }
1204
1205 static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
1206 {
1207         armv8pmu.name                   = "arm/armv8-pmuv3";
1208         armv8pmu.map_event              = armv8_pmuv3_map_event;
1209         armv8pmu.num_events             = armv8pmu_read_num_pmnc_events();
1210         armv8pmu.set_event_filter       = armv8pmu_set_event_filter;
1211         return &armv8pmu;
1212 }
1213
1214 /*
1215  * Ensure the PMU has sane values out of reset.
1216  * This requires SMP to be available, so exists as a separate initcall.
1217  */
1218 static int __init
1219 cpu_pmu_reset(void)
1220 {
1221         if (cpu_pmu && cpu_pmu->reset)
1222                 return on_each_cpu(cpu_pmu->reset, NULL, 1);
1223         return 0;
1224 }
1225 arch_initcall(cpu_pmu_reset);
1226
1227 /*
1228  * PMU platform driver and devicetree bindings.
1229  */
1230 static struct of_device_id armpmu_of_device_ids[] = {
1231         {.compatible = "arm,armv8-pmuv3"},
1232         {},
1233 };
1234
1235 static int armpmu_device_probe(struct platform_device *pdev)
1236 {
1237         if (!cpu_pmu)
1238                 return -ENODEV;
1239
1240         cpu_pmu->plat_device = pdev;
1241         return 0;
1242 }
1243
1244 static struct platform_driver armpmu_driver = {
1245         .driver         = {
1246                 .name   = "arm-pmu",
1247                 .of_match_table = armpmu_of_device_ids,
1248         },
1249         .probe          = armpmu_device_probe,
1250 };
1251
1252 static int __init register_pmu_driver(void)
1253 {
1254         return platform_driver_register(&armpmu_driver);
1255 }
1256 device_initcall(register_pmu_driver);
1257
1258 static struct pmu_hw_events *armpmu_get_cpu_events(void)
1259 {
1260         return &__get_cpu_var(cpu_hw_events);
1261 }
1262
1263 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
1264 {
1265         int cpu;
1266         for_each_possible_cpu(cpu) {
1267                 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
1268                 events->events = per_cpu(hw_events, cpu);
1269                 events->used_mask = per_cpu(used_mask, cpu);
1270                 raw_spin_lock_init(&events->pmu_lock);
1271         }
1272         armpmu->get_hw_events = armpmu_get_cpu_events;
1273 }
1274
1275 static int __init init_hw_perf_events(void)
1276 {
1277         u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
1278
1279         switch ((dfr >> 8) & 0xf) {
1280         case 0x1:       /* PMUv3 */
1281                 cpu_pmu = armv8_pmuv3_pmu_init();
1282                 break;
1283         }
1284
1285         if (cpu_pmu) {
1286                 pr_info("enabled with %s PMU driver, %d counters available\n",
1287                         cpu_pmu->name, cpu_pmu->num_events);
1288                 cpu_pmu_init(cpu_pmu);
1289                 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
1290         } else {
1291                 pr_info("no hardware support available\n");
1292         }
1293
1294         return 0;
1295 }
1296 early_initcall(init_hw_perf_events);
1297
1298 /*
1299  * Callchain handling code.
1300  */
1301 struct frame_tail {
1302         struct frame_tail   __user *fp;
1303         unsigned long       lr;
1304 } __attribute__((packed));
1305
1306 /*
1307  * Get the return address for a single stackframe and return a pointer to the
1308  * next frame tail.
1309  */
1310 static struct frame_tail __user *
1311 user_backtrace(struct frame_tail __user *tail,
1312                struct perf_callchain_entry *entry)
1313 {
1314         struct frame_tail buftail;
1315         unsigned long err;
1316
1317         /* Also check accessibility of one struct frame_tail beyond */
1318         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1319                 return NULL;
1320
1321         pagefault_disable();
1322         err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1323         pagefault_enable();
1324
1325         if (err)
1326                 return NULL;
1327
1328         perf_callchain_store(entry, buftail.lr);
1329
1330         /*
1331          * Frame pointers should strictly progress back up the stack
1332          * (towards higher addresses).
1333          */
1334         if (tail >= buftail.fp)
1335                 return NULL;
1336
1337         return buftail.fp;
1338 }
1339
1340 void perf_callchain_user(struct perf_callchain_entry *entry,
1341                          struct pt_regs *regs)
1342 {
1343         struct frame_tail __user *tail;
1344
1345         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1346                 /* We don't support guest os callchain now */
1347                 return;
1348         }
1349
1350         perf_callchain_store(entry, regs->pc);
1351         tail = (struct frame_tail __user *)regs->regs[29];
1352
1353         while (entry->nr < PERF_MAX_STACK_DEPTH &&
1354                tail && !((unsigned long)tail & 0xf))
1355                 tail = user_backtrace(tail, entry);
1356 }
1357
1358 /*
1359  * Gets called by walk_stackframe() for every stackframe. This will be called
1360  * whist unwinding the stackframe and is like a subroutine return so we use
1361  * the PC.
1362  */
1363 static int callchain_trace(struct stackframe *frame, void *data)
1364 {
1365         struct perf_callchain_entry *entry = data;
1366         perf_callchain_store(entry, frame->pc);
1367         return 0;
1368 }
1369
1370 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1371                            struct pt_regs *regs)
1372 {
1373         struct stackframe frame;
1374
1375         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1376                 /* We don't support guest os callchain now */
1377                 return;
1378         }
1379
1380         frame.fp = regs->regs[29];
1381         frame.sp = regs->sp;
1382         frame.pc = regs->pc;
1383         walk_stackframe(&frame, callchain_trace, entry);
1384 }
1385
1386 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1387 {
1388         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1389                 return perf_guest_cbs->get_guest_ip();
1390
1391         return instruction_pointer(regs);
1392 }
1393
1394 unsigned long perf_misc_flags(struct pt_regs *regs)
1395 {
1396         int misc = 0;
1397
1398         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1399                 if (perf_guest_cbs->is_user_mode())
1400                         misc |= PERF_RECORD_MISC_GUEST_USER;
1401                 else
1402                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1403         } else {
1404                 if (user_mode(regs))
1405                         misc |= PERF_RECORD_MISC_USER;
1406                 else
1407                         misc |= PERF_RECORD_MISC_KERNEL;
1408         }
1409
1410         return misc;
1411 }