2 * Copyright 2008-2010 Analog Devices Inc.
4 * Licensed under the Clear BSD license or the GPL-2 (or later)
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
11 #include "defBF54x_base.h"
13 /* The following are the #defines needed by ADSP-BF547 that are not in the common header */
17 #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
18 #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
19 #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
20 #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
21 #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
22 #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
23 #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
24 #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
25 #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
26 #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
27 #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
28 #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
30 /* Timer Group of 3 Registers */
32 #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
33 #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
34 #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
36 /* SPORT0 Registers */
38 #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
39 #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
40 #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
41 #define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
42 #define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
43 #define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
44 #define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
45 #define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
46 #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
47 #define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
48 #define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
49 #define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
50 #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
51 #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
52 #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
53 #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
54 #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
55 #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
56 #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
57 #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
58 #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
59 #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
63 #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
64 #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
65 #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
66 #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
67 #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
68 #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
69 #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
70 #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
71 #define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
72 #define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
73 #define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
74 #define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
75 #define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
76 #define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
80 #define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
81 #define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
82 #define UART2_GCTL 0xffc02108 /* Global Control Register */
83 #define UART2_LCR 0xffc0210c /* Line Control Register */
84 #define UART2_MCR 0xffc02110 /* Modem Control Register */
85 #define UART2_LSR 0xffc02114 /* Line Status Register */
86 #define UART2_MSR 0xffc02118 /* Modem Status Register */
87 #define UART2_SCR 0xffc0211c /* Scratch Register */
88 #define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
89 #define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
90 #define UART2_RBR 0xffc0212c /* Receive Buffer Register */
92 /* Two Wire Interface Registers (TWI1) */
94 #define TWI1_REGBASE 0xffc02200
95 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
96 #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
97 #define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
98 #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
99 #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
100 #define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
101 #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
102 #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
103 #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
104 #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
105 #define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
106 #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
107 #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
108 #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
109 #define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
110 #define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
114 #define SPI2_REGBASE 0xffc02400
115 #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
116 #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
117 #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
118 #define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
119 #define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
120 #define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
121 #define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
123 /* ATAPI Registers */
125 #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
126 #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
127 #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
128 #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
129 #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
130 #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
131 #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
132 #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
133 #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
134 #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
135 #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
136 #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
137 #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
138 #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
139 #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
140 #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
141 #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
142 #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
143 #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
144 #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
145 #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
146 #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
147 #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
148 #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
149 #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
153 #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
154 #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
155 #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
156 #define SDH_COMMAND 0xffc0390c /* SDH Command */
157 #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
158 #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
159 #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
160 #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
161 #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
162 #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
163 #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
164 #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
165 #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
166 #define SDH_STATUS 0xffc03934 /* SDH Status */
167 #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
168 #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
169 #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
170 #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
171 #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
172 #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
173 #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
174 #define SDH_CFG 0xffc039c8 /* SDH Configuration */
175 #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
176 #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
177 #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
178 #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
179 #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
180 #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
181 #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
182 #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
183 #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
185 /* HOST Port Registers */
187 #define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
188 #define HOST_STATUS 0xffc03a04 /* HOST Status Register */
189 #define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
191 /* USB Control Registers */
193 #define USB_FADDR 0xffc03c00 /* Function address register */
194 #define USB_POWER 0xffc03c04 /* Power management register */
195 #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
196 #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
197 #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
198 #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
199 #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
200 #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
201 #define USB_FRAME 0xffc03c20 /* USB frame number */
202 #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
203 #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
204 #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
205 #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
207 /* USB Packet Control Registers */
209 #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
210 #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
211 #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
212 #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
213 #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
214 #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
215 #define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
216 #define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
217 #define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
218 #define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
219 #define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
220 #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
221 #define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
223 /* USB Endpoint FIFO Registers */
225 #define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
226 #define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
227 #define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
228 #define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
229 #define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
230 #define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
231 #define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
232 #define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
234 /* USB OTG Control Registers */
236 #define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
237 #define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
238 #define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
240 /* USB Phy Control Registers */
242 #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
243 #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
244 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
245 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
246 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
248 /* (APHY_CNTRL is for ADI usage only) */
250 #define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
252 /* (APHY_CALIB is for ADI usage only) */
254 #define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
255 #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
257 /* (PHY_TEST is for ADI usage only) */
259 #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
260 #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
261 #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
263 /* USB Endpoint 0 Control Registers */
265 #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
266 #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
267 #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
268 #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
269 #define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
270 #define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
271 #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
272 #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
273 #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
274 #define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
276 /* USB Endpoint 1 Control Registers */
278 #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
279 #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
280 #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
281 #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
282 #define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
283 #define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
284 #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
285 #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
286 #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
287 #define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
289 /* USB Endpoint 2 Control Registers */
291 #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
292 #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
293 #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
294 #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
295 #define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
296 #define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
297 #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
298 #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
299 #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
300 #define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
302 /* USB Endpoint 3 Control Registers */
304 #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
305 #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
306 #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
307 #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
308 #define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
309 #define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
310 #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
311 #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
312 #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
313 #define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
315 /* USB Endpoint 4 Control Registers */
317 #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
318 #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
319 #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
320 #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
321 #define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
322 #define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
323 #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
324 #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
325 #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
326 #define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
328 /* USB Endpoint 5 Control Registers */
330 #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
331 #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
332 #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
333 #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
334 #define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
335 #define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
336 #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
337 #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
338 #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
339 #define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
341 /* USB Endpoint 6 Control Registers */
343 #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
344 #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
345 #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
346 #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
347 #define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
348 #define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
349 #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
350 #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
351 #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
352 #define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
354 /* USB Endpoint 7 Control Registers */
356 #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
357 #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
358 #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
359 #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
360 #define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
361 #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
362 #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
363 #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
364 #define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
365 #define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
367 #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
369 /* USB Channel 0 Config Registers */
371 #define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
372 #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
373 #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
374 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
375 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
377 /* USB Channel 1 Config Registers */
379 #define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
380 #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
381 #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
382 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
383 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
385 /* USB Channel 2 Config Registers */
387 #define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
388 #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
389 #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
390 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
391 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
393 /* USB Channel 3 Config Registers */
395 #define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
396 #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
397 #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
398 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
399 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
401 /* USB Channel 4 Config Registers */
403 #define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
404 #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
405 #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
406 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
407 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
409 /* USB Channel 5 Config Registers */
411 #define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
412 #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
413 #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
414 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
415 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
417 /* USB Channel 6 Config Registers */
419 #define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
420 #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
421 #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
422 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
423 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
425 /* USB Channel 7 Config Registers */
427 #define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
428 #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
429 #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
430 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
431 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
433 /* Keypad Registers */
435 #define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
436 #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
437 #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
438 #define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
439 #define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
440 #define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
442 /* Pixel Compositor (PIXC) Registers */
444 #define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
445 #define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
446 #define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
447 #define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
448 #define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
449 #define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
450 #define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
451 #define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
452 #define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
453 #define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
454 #define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
455 #define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
456 #define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
457 #define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
458 #define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
459 #define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
460 #define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
461 #define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
462 #define PIXC_TC 0xffc04450 /* Holds the transparent color value */
464 /* Handshake MDMA 0 Registers */
466 #define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
467 #define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
468 #define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
469 #define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
470 #define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
471 #define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
472 #define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
474 /* Handshake MDMA 1 Registers */
476 #define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
477 #define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
478 #define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
479 #define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
480 #define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
481 #define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
482 #define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
485 /* ********************************************************** */
486 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
487 /* and MULTI BIT READ MACROS */
488 /* ********************************************************** */
490 /* Bit masks for PIXC_CTL */
492 #define PIXC_EN 0x1 /* Pixel Compositor Enable */
493 #define OVR_A_EN 0x2 /* Overlay A Enable */
494 #define OVR_B_EN 0x4 /* Overlay B Enable */
495 #define IMG_FORM 0x8 /* Image Data Format */
496 #define OVR_FORM 0x10 /* Overlay Data Format */
497 #define OUT_FORM 0x20 /* Output Data Format */
498 #define UDS_MOD 0x40 /* Resampling Mode */
499 #define TC_EN 0x80 /* Transparent Color Enable */
500 #define IMG_STAT 0x300 /* Image FIFO Status */
501 #define OVR_STAT 0xc00 /* Overlay FIFO Status */
502 #define WM_LVL 0x3000 /* FIFO Watermark Level */
504 /* Bit masks for PIXC_AHSTART */
506 #define A_HSTART 0xfff /* Horizontal Start Coordinates */
508 /* Bit masks for PIXC_AHEND */
510 #define A_HEND 0xfff /* Horizontal End Coordinates */
512 /* Bit masks for PIXC_AVSTART */
514 #define A_VSTART 0x3ff /* Vertical Start Coordinates */
516 /* Bit masks for PIXC_AVEND */
518 #define A_VEND 0x3ff /* Vertical End Coordinates */
520 /* Bit masks for PIXC_ATRANSP */
522 #define A_TRANSP 0xf /* Transparency Value */
524 /* Bit masks for PIXC_BHSTART */
526 #define B_HSTART 0xfff /* Horizontal Start Coordinates */
528 /* Bit masks for PIXC_BHEND */
530 #define B_HEND 0xfff /* Horizontal End Coordinates */
532 /* Bit masks for PIXC_BVSTART */
534 #define B_VSTART 0x3ff /* Vertical Start Coordinates */
536 /* Bit masks for PIXC_BVEND */
538 #define B_VEND 0x3ff /* Vertical End Coordinates */
540 /* Bit masks for PIXC_BTRANSP */
542 #define B_TRANSP 0xf /* Transparency Value */
544 /* Bit masks for PIXC_INTRSTAT */
546 #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
547 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
548 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
549 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
551 /* Bit masks for PIXC_RYCON */
553 #define A11 0x3ff /* A11 in the Coefficient Matrix */
554 #define A12 0xffc00 /* A12 in the Coefficient Matrix */
555 #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
556 #define RY_MULT4 0x40000000 /* Multiply Row by 4 */
558 /* Bit masks for PIXC_GUCON */
560 #define A21 0x3ff /* A21 in the Coefficient Matrix */
561 #define A22 0xffc00 /* A22 in the Coefficient Matrix */
562 #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
563 #define GU_MULT4 0x40000000 /* Multiply Row by 4 */
565 /* Bit masks for PIXC_BVCON */
567 #define A31 0x3ff /* A31 in the Coefficient Matrix */
568 #define A32 0xffc00 /* A32 in the Coefficient Matrix */
569 #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
570 #define BV_MULT4 0x40000000 /* Multiply Row by 4 */
572 /* Bit masks for PIXC_CCBIAS */
574 #define A14 0x3ff /* A14 in the Bias Vector */
575 #define A24 0xffc00 /* A24 in the Bias Vector */
576 #define A34 0x3ff00000 /* A34 in the Bias Vector */
578 /* Bit masks for PIXC_TC */
580 #define RY_TRANS 0xff /* Transparent Color - R/Y Component */
581 #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
582 #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
584 /* Bit masks for HOST_CONTROL */
586 #define HOST_EN 0x1 /* Host Enable */
587 #define HOST_END 0x2 /* Host Endianess */
588 #define DATA_SIZE 0x4 /* Data Size */
589 #define HOST_RST 0x8 /* Host Reset */
590 #define HRDY_OVR 0x20 /* Host Ready Override */
591 #define INT_MODE 0x40 /* Interrupt Mode */
592 #define BT_EN 0x80 /* Bus Timeout Enable */
593 #define EHW 0x100 /* Enable Host Write */
594 #define EHR 0x200 /* Enable Host Read */
595 #define BDR 0x400 /* Burst DMA Requests */
597 /* Bit masks for HOST_STATUS */
599 #define DMA_READY 0x1 /* DMA Ready */
600 #define FIFOFULL 0x2 /* FIFO Full */
601 #define FIFOEMPTY 0x4 /* FIFO Empty */
602 #define DMA_COMPLETE 0x8 /* DMA Complete */
603 #define HSHK 0x10 /* Host Handshake */
604 #define HSTIMEOUT 0x20 /* Host Timeout */
605 #define HIRQ 0x40 /* Host Interrupt Request */
606 #define ALLOW_CNFG 0x80 /* Allow New Configuration */
607 #define DMA_DIR 0x100 /* DMA Direction */
608 #define BTE 0x200 /* Bus Timeout Enabled */
610 /* Bit masks for HOST_TIMEOUT */
612 #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
614 /* Bit masks for KPAD_CTL */
616 #define KPAD_EN 0x1 /* Keypad Enable */
617 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
618 #define KPAD_ROWEN 0x1c00 /* Row Enable Width */
619 #define KPAD_COLEN 0xe000 /* Column Enable Width */
621 /* Bit masks for KPAD_PRESCALE */
623 #define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
625 /* Bit masks for KPAD_MSEL */
627 #define DBON_SCALE 0xff /* Debounce Scale Value */
628 #define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
630 /* Bit masks for KPAD_ROWCOL */
632 #define KPAD_ROW 0xff /* Rows Pressed */
633 #define KPAD_COL 0xff00 /* Columns Pressed */
635 /* Bit masks for KPAD_STAT */
637 #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
638 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
639 #define KPAD_PRESSED 0x8 /* Key press current status */
641 /* Bit masks for KPAD_SOFTEVAL */
643 #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
645 /* Bit masks for ATAPI_CONTROL */
647 #define PIO_START 0x1 /* Start PIO/Reg Op */
648 #define MULTI_START 0x2 /* Start Multi-DMA Op */
649 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
650 #define XFER_DIR 0x8 /* Transfer Direction */
651 #define IORDY_EN 0x10 /* IORDY Enable */
652 #define FIFO_FLUSH 0x20 /* Flush FIFOs */
653 #define SOFT_RST 0x40 /* Soft Reset */
654 #define DEV_RST 0x80 /* Device Reset */
655 #define TFRCNT_RST 0x100 /* Trans Count Reset */
656 #define END_ON_TERM 0x200 /* End/Terminate Select */
657 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
658 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
660 /* Bit masks for ATAPI_STATUS */
662 #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
663 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
664 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
665 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
667 /* Bit masks for ATAPI_DEV_ADDR */
669 #define DEV_ADDR 0x1f /* Device Address */
671 /* Bit masks for ATAPI_INT_MASK */
673 #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
674 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
675 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
676 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
677 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
678 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
679 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
680 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
681 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
683 /* Bit masks for ATAPI_INT_STATUS */
685 #define ATAPI_DEV_INT 0x1 /* Device interrupt status */
686 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
687 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
688 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
689 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
690 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
691 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
692 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
693 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
695 /* Bit masks for ATAPI_LINE_STATUS */
697 #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
698 #define ATAPI_DASP 0x2 /* Device dasp to host line status */
699 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
700 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
701 #define ATAPI_ADDR 0x70 /* ATAPI address line status */
702 #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
704 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
705 #define ATAPI_DIORN 0x400 /* ATAPI read line status */
706 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
708 /* Bit masks for ATAPI_SM_STATE */
710 #define PIO_CSTATE 0xf /* PIO mode state machine current state */
711 #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
712 #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
713 #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
715 /* Bit masks for ATAPI_TERMINATE */
717 #define ATAPI_HOST_TERM 0x1 /* Host terminationation */
719 /* Bit masks for ATAPI_REG_TIM_0 */
721 #define T2_REG 0xff /* End of cycle time for register access transfers */
722 #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
724 /* Bit masks for ATAPI_PIO_TIM_0 */
726 #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
727 #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
728 #define T4_REG 0xf000 /* DIOW data hold */
730 /* Bit masks for ATAPI_PIO_TIM_1 */
732 #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
734 /* Bit masks for ATAPI_MULTI_TIM_0 */
736 #define TD 0xff /* DIOR/DIOW asserted pulsewidth */
737 #define TM 0xff00 /* Time from address valid to DIOR/DIOW */
739 /* Bit masks for ATAPI_MULTI_TIM_1 */
741 #define TKW 0xff /* Selects DIOW negated pulsewidth */
742 #define TKR 0xff00 /* Selects DIOR negated pulsewidth */
744 /* Bit masks for ATAPI_MULTI_TIM_2 */
746 #define TH 0xff /* Selects DIOW data hold */
747 #define TEOC 0xff00 /* Selects end of cycle for DMA */
749 /* Bit masks for ATAPI_ULTRA_TIM_0 */
751 #define TACK 0xff /* Selects setup and hold times for TACK */
752 #define TENV 0xff00 /* Selects envelope time */
754 /* Bit masks for ATAPI_ULTRA_TIM_1 */
756 #define TDVS 0xff /* Selects data valid setup time */
757 #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
759 /* Bit masks for ATAPI_ULTRA_TIM_2 */
761 #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
762 #define TMLI 0xff00 /* Selects interlock time */
764 /* Bit masks for ATAPI_ULTRA_TIM_3 */
766 #define TZAH 0xff /* Selects minimum delay required for output */
767 #define READY_PAUSE 0xff00 /* Selects ready to pause */
769 /* Bit masks for TIMER_ENABLE1 */
771 #define TIMEN8 0x1 /* Timer 8 Enable */
772 #define TIMEN9 0x2 /* Timer 9 Enable */
773 #define TIMEN10 0x4 /* Timer 10 Enable */
775 /* Bit masks for TIMER_DISABLE1 */
777 #define TIMDIS8 0x1 /* Timer 8 Disable */
778 #define TIMDIS9 0x2 /* Timer 9 Disable */
779 #define TIMDIS10 0x4 /* Timer 10 Disable */
781 /* Bit masks for TIMER_STATUS1 */
783 #define TIMIL8 0x1 /* Timer 8 Interrupt */
784 #define TIMIL9 0x2 /* Timer 9 Interrupt */
785 #define TIMIL10 0x4 /* Timer 10 Interrupt */
786 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
787 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
788 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
789 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
790 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
791 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
793 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
795 /* Bit masks for USB_FADDR */
797 #define FUNCTION_ADDRESS 0x7f /* Function address */
799 /* Bit masks for USB_POWER */
801 #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
802 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
803 #define RESUME_MODE 0x4 /* DMA Mode */
804 #define RESET 0x8 /* Reset indicator */
805 #define HS_MODE 0x10 /* High Speed mode indicator */
806 #define HS_ENABLE 0x20 /* high Speed Enable */
807 #define SOFT_CONN 0x40 /* Soft connect */
808 #define ISO_UPDATE 0x80 /* Isochronous update */
810 /* Bit masks for USB_INTRTX */
812 #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
813 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
814 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
815 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
816 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
817 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
818 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
819 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
821 /* Bit masks for USB_INTRRX */
823 #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
824 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
825 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
826 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
827 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
828 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
829 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
831 /* Bit masks for USB_INTRTXE */
833 #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
834 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
835 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
836 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
837 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
838 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
839 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
840 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
842 /* Bit masks for USB_INTRRXE */
844 #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
845 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
846 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
847 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
848 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
849 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
850 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
852 /* Bit masks for USB_INTRUSB */
854 #define SUSPEND_B 0x1 /* Suspend indicator */
855 #define RESUME_B 0x2 /* Resume indicator */
856 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
857 #define SOF_B 0x8 /* Start of frame */
858 #define CONN_B 0x10 /* Connection indicator */
859 #define DISCON_B 0x20 /* Disconnect indicator */
860 #define SESSION_REQ_B 0x40 /* Session Request */
861 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
863 /* Bit masks for USB_INTRUSBE */
865 #define SUSPEND_BE 0x1 /* Suspend indicator int enable */
866 #define RESUME_BE 0x2 /* Resume indicator int enable */
867 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
868 #define SOF_BE 0x8 /* Start of frame int enable */
869 #define CONN_BE 0x10 /* Connection indicator int enable */
870 #define DISCON_BE 0x20 /* Disconnect indicator int enable */
871 #define SESSION_REQ_BE 0x40 /* Session Request int enable */
872 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
874 /* Bit masks for USB_FRAME */
876 #define FRAME_NUMBER 0x7ff /* Frame number */
878 /* Bit masks for USB_INDEX */
880 #define SELECTED_ENDPOINT 0xf /* selected endpoint */
882 /* Bit masks for USB_GLOBAL_CTL */
884 #define GLOBAL_ENA 0x1 /* enables USB module */
885 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
886 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
887 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
888 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
889 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
890 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
891 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
892 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
893 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
894 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
895 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
896 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
897 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
898 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
900 /* Bit masks for USB_OTG_DEV_CTL */
902 #define SESSION 0x1 /* session indicator */
903 #define HOST_REQ 0x2 /* Host negotiation request */
904 #define HOST_MODE 0x4 /* indicates USBDRC is a host */
905 #define VBUS0 0x8 /* Vbus level indicator[0] */
906 #define VBUS1 0x10 /* Vbus level indicator[1] */
907 #define LSDEV 0x20 /* Low-speed indicator */
908 #define FSDEV 0x40 /* Full or High-speed indicator */
909 #define B_DEVICE 0x80 /* A' or 'B' device indicator */
911 /* Bit masks for USB_OTG_VBUS_IRQ */
913 #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
914 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
915 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
916 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
917 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
918 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
920 /* Bit masks for USB_OTG_VBUS_MASK */
922 #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
923 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
924 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
925 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
926 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
927 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
929 /* Bit masks for USB_CSR0 */
931 #define RXPKTRDY 0x1 /* data packet receive indicator */
932 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */
933 #define STALL_SENT 0x4 /* STALL handshake sent */
934 #define DATAEND 0x8 /* Data end indicator */
935 #define SETUPEND 0x10 /* Setup end */
936 #define SENDSTALL 0x20 /* Send STALL handshake */
937 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
938 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
939 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */
940 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
941 #define SETUPPKT_H 0x8 /* send Setup token host mode */
942 #define ERROR_H 0x10 /* timeout error indicator host mode */
943 #define REQPKT_H 0x20 /* Request an IN transaction host mode */
944 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */
945 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
947 /* Bit masks for USB_COUNT0 */
949 #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
951 /* Bit masks for USB_NAKLIMIT0 */
953 #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
955 /* Bit masks for USB_TX_MAX_PACKET */
957 #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
959 /* Bit masks for USB_RX_MAX_PACKET */
961 #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
963 /* Bit masks for USB_TXCSR */
965 #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
966 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
967 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
968 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
969 #define STALL_SEND_T 0x10 /* issue a Stall handshake */
970 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */
971 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
972 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */
973 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
974 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
975 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
976 #define ISO_T 0x4000 /* enable Isochronous transfers */
977 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
978 #define ERROR_TH 0x4 /* error condition host mode */
979 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
980 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
982 /* Bit masks for USB_TXCOUNT */
984 #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
986 /* Bit masks for USB_RXCSR */
988 #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
989 #define FIFO_FULL_R 0x2 /* FIFO not empty */
990 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
991 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
992 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
993 #define STALL_SEND_R 0x20 /* issue a Stall handshake */
994 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */
995 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
996 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */
997 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
998 #define DISNYET_R 0x1000 /* disable Nyet handshakes */
999 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1000 #define ISO_R 0x4000 /* enable Isochronous transfers */
1001 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1002 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1003 #define REQPKT_RH 0x20 /* request an IN transaction host mode */
1004 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1005 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1006 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1007 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1009 /* Bit masks for USB_RXCOUNT */
1011 #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1013 /* Bit masks for USB_TXTYPE */
1015 #define TARGET_EP_NO_T 0xf /* EP number */
1016 #define PROTOCOL_T 0xc /* transfer type */
1018 /* Bit masks for USB_TXINTERVAL */
1020 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1022 /* Bit masks for USB_RXTYPE */
1024 #define TARGET_EP_NO_R 0xf /* EP number */
1025 #define PROTOCOL_R 0xc /* transfer type */
1027 /* Bit masks for USB_RXINTERVAL */
1029 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1031 /* Bit masks for USB_DMA_INTERRUPT */
1033 #define DMA0_INT 0x1 /* DMA0 pending interrupt */
1034 #define DMA1_INT 0x2 /* DMA1 pending interrupt */
1035 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
1036 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
1037 #define DMA4_INT 0x10 /* DMA4 pending interrupt */
1038 #define DMA5_INT 0x20 /* DMA5 pending interrupt */
1039 #define DMA6_INT 0x40 /* DMA6 pending interrupt */
1040 #define DMA7_INT 0x80 /* DMA7 pending interrupt */
1042 /* Bit masks for USB_DMAxCONTROL */
1044 #define DMA_ENA 0x1 /* DMA enable */
1045 #define DIRECTION 0x2 /* direction of DMA transfer */
1046 #define MODE 0x4 /* DMA Bus error */
1047 #define INT_ENA 0x8 /* Interrupt enable */
1048 #define EPNUM 0xf0 /* EP number */
1049 #define BUSERROR 0x100 /* DMA Bus error */
1051 /* Bit masks for USB_DMAxADDRHIGH */
1053 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1055 /* Bit masks for USB_DMAxADDRLOW */
1057 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1059 /* Bit masks for USB_DMAxCOUNTHIGH */
1061 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1063 /* Bit masks for USB_DMAxCOUNTLOW */
1065 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1067 #endif /* _DEF_BF547_H */
