arch/mips/include/uapi/asm/inst.h

   1 /*
   2  * Format of an instruction in memory.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 2000 by Ralf Baechle
   9  * Copyright (C) 2006 by Thiemo Seufer
  10  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  11  */
  12 #ifndef _UAPI_ASM_INST_H
  13 #define _UAPI_ASM_INST_H
  14
  15 /*
  16  * Major opcodes; before MIPS IV cop1x was called cop3.
  17  */
  18 enum major_op {
  19         spec_op, bcond_op, j_op, jal_op,
  20         beq_op, bne_op, blez_op, bgtz_op,
  21         addi_op, addiu_op, slti_op, sltiu_op,
  22         andi_op, ori_op, xori_op, lui_op,
  23         cop0_op, cop1_op, cop2_op, cop1x_op,
  24         beql_op, bnel_op, blezl_op, bgtzl_op,
  25         daddi_op, daddiu_op, ldl_op, ldr_op,
  26         spec2_op, jalx_op, mdmx_op, spec3_op,
  27         lb_op, lh_op, lwl_op, lw_op,
  28         lbu_op, lhu_op, lwr_op, lwu_op,
  29         sb_op, sh_op, swl_op, sw_op,
  30         sdl_op, sdr_op, swr_op, cache_op,
  31         ll_op, lwc1_op, lwc2_op, pref_op,
  32         lld_op, ldc1_op, ldc2_op, ld_op,
  33         sc_op, swc1_op, swc2_op, major_3b_op,
  34         scd_op, sdc1_op, sdc2_op, sd_op
  35 };
  36
  37 /*
  38  * func field of spec opcode.
  39  */
  40 enum spec_op {
  41         sll_op, movc_op, srl_op, sra_op,
  42         sllv_op, pmon_op, srlv_op, srav_op,
  43         jr_op, jalr_op, movz_op, movn_op,
  44         syscall_op, break_op, spim_op, sync_op,
  45         mfhi_op, mthi_op, mflo_op, mtlo_op,
  46         dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  47         mult_op, multu_op, div_op, divu_op,
  48         dmult_op, dmultu_op, ddiv_op, ddivu_op,
  49         add_op, addu_op, sub_op, subu_op,
  50         and_op, or_op, xor_op, nor_op,
  51         spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  52         dadd_op, daddu_op, dsub_op, dsubu_op,
  53         tge_op, tgeu_op, tlt_op, tltu_op,
  54         teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  55         dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  56         dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  57 };
  58
  59 /*
  60  * func field of spec2 opcode.
  61  */
  62 enum spec2_op {
  63         madd_op, maddu_op, mul_op, spec2_3_unused_op,
  64         msub_op, msubu_op, /* more unused ops */
  65         clz_op = 0x20, clo_op,
  66         dclz_op = 0x24, dclo_op,
  67         sdbpp_op = 0x3f
  68 };
  69
  70 /*
  71  * func field of spec3 opcode.
  72  */
  73 enum spec3_op {
  74         ext_op, dextm_op, dextu_op, dext_op,
  75         ins_op, dinsm_op, dinsu_op, dins_op,
  76         lx_op = 0x0a,
  77         bshfl_op = 0x20,
  78         dbshfl_op = 0x24,
  79         rdhwr_op = 0x3b
  80 };
  81
  82 /*
  83  * rt field of bcond opcodes.
  84  */
  85 enum rt_op {
  86         bltz_op, bgez_op, bltzl_op, bgezl_op,
  87         spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
  88         tgei_op, tgeiu_op, tlti_op, tltiu_op,
  89         teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
  90         bltzal_op, bgezal_op, bltzall_op, bgezall_op,
  91         rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
  92         rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
  93         bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
  94 };
  95
  96 /*
  97  * rs field of cop opcodes.
  98  */
  99 enum cop_op {
 100         mfc_op        = 0x00, dmfc_op       = 0x01,
 101         cfc_op        = 0x02, mtc_op        = 0x04,
 102         dmtc_op       = 0x05, ctc_op        = 0x06,
 103         bc_op         = 0x08, cop_op        = 0x10,
 104         copm_op       = 0x18
 105 };
 106
 107 /*
 108  * rt field of cop.bc_op opcodes
 109  */
 110 enum bcop_op {
 111         bcf_op, bct_op, bcfl_op, bctl_op
 112 };
 113
 114 /*
 115  * func field of cop0 coi opcodes.
 116  */
 117 enum cop0_coi_func {
 118         tlbr_op       = 0x01, tlbwi_op      = 0x02,
 119         tlbwr_op      = 0x06, tlbp_op       = 0x08,
 120         rfe_op        = 0x10, eret_op       = 0x18
 121 };
 122
 123 /*
 124  * func field of cop0 com opcodes.
 125  */
 126 enum cop0_com_func {
 127         tlbr1_op      = 0x01, tlbw_op       = 0x02,
 128         tlbp1_op      = 0x08, dctr_op       = 0x09,
 129         dctw_op       = 0x0a
 130 };
 131
 132 /*
 133  * fmt field of cop1 opcodes.
 134  */
 135 enum cop1_fmt {
 136         s_fmt, d_fmt, e_fmt, q_fmt,
 137         w_fmt, l_fmt
 138 };
 139
 140 /*
 141  * func field of cop1 instructions using d, s or w format.
 142  */
 143 enum cop1_sdw_func {
 144         fadd_op      =  0x00, fsub_op      =  0x01,
 145         fmul_op      =  0x02, fdiv_op      =  0x03,
 146         fsqrt_op     =  0x04, fabs_op      =  0x05,
 147         fmov_op      =  0x06, fneg_op      =  0x07,
 148         froundl_op   =  0x08, ftruncl_op   =  0x09,
 149         fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 150         fround_op    =  0x0c, ftrunc_op    =  0x0d,
 151         fceil_op     =  0x0e, ffloor_op    =  0x0f,
 152         fmovc_op     =  0x11, fmovz_op     =  0x12,
 153         fmovn_op     =  0x13, frecip_op    =  0x15,
 154         frsqrt_op    =  0x16, fcvts_op     =  0x20,
 155         fcvtd_op     =  0x21, fcvte_op     =  0x22,
 156         fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 157         fcmp_op      =  0x30
 158 };
 159
 160 /*
 161  * func field of cop1x opcodes (MIPS IV).
 162  */
 163 enum cop1x_func {
 164         lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 165         pfetch_op    =  0x07, swxc1_op     =  0x08,
 166         sdxc1_op     =  0x09, madd_s_op    =  0x20,
 167         madd_d_op    =  0x21, madd_e_op    =  0x22,
 168         msub_s_op    =  0x28, msub_d_op    =  0x29,
 169         msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 170         nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 171         nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 172         nmsub_e_op   =  0x3a
 173 };
 174
 175 /*
 176  * func field for mad opcodes (MIPS IV).
 177  */
 178 enum mad_func {
 179         madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 180         nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 181 };
 182
 183 /*
 184  * func field for special3 lx opcodes (Cavium Octeon).
 185  */
 186 enum lx_func {
 187         lwx_op  = 0x00,
 188         lhx_op  = 0x04,
 189         lbux_op = 0x06,
 190         ldx_op  = 0x08,
 191         lwux_op = 0x10,
 192         lhux_op = 0x14,
 193         lbx_op  = 0x16,
 194 };
 195
 196 /*
 197  * (microMIPS) Major opcodes.
 198  */
 199 enum mm_major_op {
 200         mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 201         mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 202         mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 203         mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 204         mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 205         mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
 206         mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 207         mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 208         mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 209         mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 210         mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 211         mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 212         mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 213         mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 214         mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 215         mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 216 };
 217
 218 /*
 219  * (microMIPS) POOL32I minor opcodes.
 220  */
 221 enum mm_32i_minor_op {
 222         mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 223         mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 224         mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 225         mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 226         mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 227         mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 228         mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 229         mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 230         mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 231 };
 232
 233 /*
 234  * (microMIPS) POOL32A minor opcodes.
 235  */
 236 enum mm_32a_minor_op {
 237         mm_sll32_op = 0x000,
 238         mm_ins_op = 0x00c,
 239         mm_ext_op = 0x02c,
 240         mm_pool32axf_op = 0x03c,
 241         mm_srl32_op = 0x040,
 242         mm_sra_op = 0x080,
 243         mm_rotr_op = 0x0c0,
 244         mm_lwxs_op = 0x118,
 245         mm_addu32_op = 0x150,
 246         mm_subu32_op = 0x1d0,
 247         mm_and_op = 0x250,
 248         mm_or32_op = 0x290,
 249         mm_xor32_op = 0x310,
 250 };
 251
 252 /*
 253  * (microMIPS) POOL32B functions.
 254  */
 255 enum mm_32b_func {
 256         mm_lwc2_func = 0x0,
 257         mm_lwp_func = 0x1,
 258         mm_ldc2_func = 0x2,
 259         mm_ldp_func = 0x4,
 260         mm_lwm32_func = 0x5,
 261         mm_cache_func = 0x6,
 262         mm_ldm_func = 0x7,
 263         mm_swc2_func = 0x8,
 264         mm_swp_func = 0x9,
 265         mm_sdc2_func = 0xa,
 266         mm_sdp_func = 0xc,
 267         mm_swm32_func = 0xd,
 268         mm_sdm_func = 0xf,
 269 };
 270
 271 /*
 272  * (microMIPS) POOL32C functions.
 273  */
 274 enum mm_32c_func {
 275         mm_pref_func = 0x2,
 276         mm_ll_func = 0x3,
 277         mm_swr_func = 0x9,
 278         mm_sc_func = 0xb,
 279         mm_lwu_func = 0xe,
 280 };
 281
 282 /*
 283  * (microMIPS) POOL32AXF minor opcodes.
 284  */
 285 enum mm_32axf_minor_op {
 286         mm_mfc0_op = 0x003,
 287         mm_mtc0_op = 0x00b,
 288         mm_tlbp_op = 0x00d,
 289         mm_jalr_op = 0x03c,
 290         mm_tlbr_op = 0x04d,
 291         mm_jalrhb_op = 0x07c,
 292         mm_tlbwi_op = 0x08d,
 293         mm_tlbwr_op = 0x0cd,
 294         mm_jalrs_op = 0x13c,
 295         mm_jalrshb_op = 0x17c,
 296         mm_syscall_op = 0x22d,
 297         mm_eret_op = 0x3cd,
 298 };
 299
 300 /*
 301  * (microMIPS) POOL32F minor opcodes.
 302  */
 303 enum mm_32f_minor_op {
 304         mm_32f_00_op = 0x00,
 305         mm_32f_01_op = 0x01,
 306         mm_32f_02_op = 0x02,
 307         mm_32f_10_op = 0x08,
 308         mm_32f_11_op = 0x09,
 309         mm_32f_12_op = 0x0a,
 310         mm_32f_20_op = 0x10,
 311         mm_32f_30_op = 0x18,
 312         mm_32f_40_op = 0x20,
 313         mm_32f_41_op = 0x21,
 314         mm_32f_42_op = 0x22,
 315         mm_32f_50_op = 0x28,
 316         mm_32f_51_op = 0x29,
 317         mm_32f_52_op = 0x2a,
 318         mm_32f_60_op = 0x30,
 319         mm_32f_70_op = 0x38,
 320         mm_32f_73_op = 0x3b,
 321         mm_32f_74_op = 0x3c,
 322 };
 323
 324 /*
 325  * (microMIPS) POOL32F secondary minor opcodes.
 326  */
 327 enum mm_32f_10_minor_op {
 328         mm_lwxc1_op = 0x1,
 329         mm_swxc1_op,
 330         mm_ldxc1_op,
 331         mm_sdxc1_op,
 332         mm_luxc1_op,
 333         mm_suxc1_op,
 334 };
 335
 336 enum mm_32f_func {
 337         mm_lwxc1_func = 0x048,
 338         mm_swxc1_func = 0x088,
 339         mm_ldxc1_func = 0x0c8,
 340         mm_sdxc1_func = 0x108,
 341 };
 342
 343 /*
 344  * (microMIPS) POOL32F secondary minor opcodes.
 345  */
 346 enum mm_32f_40_minor_op {
 347         mm_fmovf_op,
 348         mm_fmovt_op,
 349 };
 350
 351 /*
 352  * (microMIPS) POOL32F secondary minor opcodes.
 353  */
 354 enum mm_32f_60_minor_op {
 355         mm_fadd_op,
 356         mm_fsub_op,
 357         mm_fmul_op,
 358         mm_fdiv_op,
 359 };
 360
 361 /*
 362  * (microMIPS) POOL32F secondary minor opcodes.
 363  */
 364 enum mm_32f_70_minor_op {
 365         mm_fmovn_op,
 366         mm_fmovz_op,
 367 };
 368
 369 /*
 370  * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 371  */
 372 enum mm_32f_73_minor_op {
 373         mm_fmov0_op = 0x01,
 374         mm_fcvtl_op = 0x04,
 375         mm_movf0_op = 0x05,
 376         mm_frsqrt_op = 0x08,
 377         mm_ffloorl_op = 0x0c,
 378         mm_fabs0_op = 0x0d,
 379         mm_fcvtw_op = 0x24,
 380         mm_movt0_op = 0x25,
 381         mm_fsqrt_op = 0x28,
 382         mm_ffloorw_op = 0x2c,
 383         mm_fneg0_op = 0x2d,
 384         mm_cfc1_op = 0x40,
 385         mm_frecip_op = 0x48,
 386         mm_fceill_op = 0x4c,
 387         mm_fcvtd0_op = 0x4d,
 388         mm_ctc1_op = 0x60,
 389         mm_fceilw_op = 0x6c,
 390         mm_fcvts0_op = 0x6d,
 391         mm_mfc1_op = 0x80,
 392         mm_fmov1_op = 0x81,
 393         mm_movf1_op = 0x85,
 394         mm_ftruncl_op = 0x8c,
 395         mm_fabs1_op = 0x8d,
 396         mm_mtc1_op = 0xa0,
 397         mm_movt1_op = 0xa5,
 398         mm_ftruncw_op = 0xac,
 399         mm_fneg1_op = 0xad,
 400         mm_froundl_op = 0xcc,
 401         mm_fcvtd1_op = 0xcd,
 402         mm_froundw_op = 0xec,
 403         mm_fcvts1_op = 0xed,
 404 };
 405
 406 /*
 407  * (microMIPS) POOL16C minor opcodes.
 408  */
 409 enum mm_16c_minor_op {
 410         mm_lwm16_op = 0x04,
 411         mm_swm16_op = 0x05,
 412         mm_jr16_op = 0x0c,
 413         mm_jrc_op = 0x0d,
 414         mm_jalr16_op = 0x0e,
 415         mm_jalrs16_op = 0x0f,
 416         mm_jraddiusp_op = 0x18,
 417 };
 418
 419 /*
 420  * (microMIPS) POOL16D minor opcodes.
 421  */
 422 enum mm_16d_minor_op {
 423         mm_addius5_func,
 424         mm_addiusp_func,
 425 };
 426
 427 /*
 428  * (MIPS16e) opcodes.
 429  */
 430 enum MIPS16e_ops {
 431         MIPS16e_jal_op = 003,
 432         MIPS16e_ld_op = 007,
 433         MIPS16e_i8_op = 014,
 434         MIPS16e_sd_op = 017,
 435         MIPS16e_lb_op = 020,
 436         MIPS16e_lh_op = 021,
 437         MIPS16e_lwsp_op = 022,
 438         MIPS16e_lw_op = 023,
 439         MIPS16e_lbu_op = 024,
 440         MIPS16e_lhu_op = 025,
 441         MIPS16e_lwpc_op = 026,
 442         MIPS16e_lwu_op = 027,
 443         MIPS16e_sb_op = 030,
 444         MIPS16e_sh_op = 031,
 445         MIPS16e_swsp_op = 032,
 446         MIPS16e_sw_op = 033,
 447         MIPS16e_rr_op = 035,
 448         MIPS16e_extend_op = 036,
 449         MIPS16e_i64_op = 037,
 450 };
 451
 452 enum MIPS16e_i64_func {
 453         MIPS16e_ldsp_func,
 454         MIPS16e_sdsp_func,
 455         MIPS16e_sdrasp_func,
 456         MIPS16e_dadjsp_func,
 457         MIPS16e_ldpc_func,
 458 };
 459
 460 enum MIPS16e_rr_func {
 461         MIPS16e_jr_func,
 462 };
 463
 464 enum MIPS6e_i8_func {
 465         MIPS16e_swrasp_func = 02,
 466 };
 467
 468 /*
 469  * (microMIPS & MIPS16e) NOP instruction.
 470  */
 471 #define MM_NOP16        0x0c00
 472
 473 /*
 474  * Damn ...  bitfields depend from byteorder :-(
 475  */
 476 #ifdef __MIPSEB__
 477 #define BITFIELD_FIELD(field, more)                                     \
 478         field;                                                          \
 479         more
 480
 481 #elif defined(__MIPSEL__)
 482
 483 #define BITFIELD_FIELD(field, more)                                     \
 484         more                                                            \
 485         field;
 486
 487 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 488 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 489 #endif
 490
 491 struct j_format {
 492         BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 493         BITFIELD_FIELD(unsigned int target : 26,
 494         ;))
 495 };
 496
 497 struct i_format {                       /* signed immediate format */
 498         BITFIELD_FIELD(unsigned int opcode : 6,
 499         BITFIELD_FIELD(unsigned int rs : 5,
 500         BITFIELD_FIELD(unsigned int rt : 5,
 501         BITFIELD_FIELD(signed int simmediate : 16,
 502         ;))))
 503 };
 504
 505 struct u_format {                       /* unsigned immediate format */
 506         BITFIELD_FIELD(unsigned int opcode : 6,
 507         BITFIELD_FIELD(unsigned int rs : 5,
 508         BITFIELD_FIELD(unsigned int rt : 5,
 509         BITFIELD_FIELD(unsigned int uimmediate : 16,
 510         ;))))
 511 };
 512
 513 struct c_format {                       /* Cache (>= R6000) format */
 514         BITFIELD_FIELD(unsigned int opcode : 6,
 515         BITFIELD_FIELD(unsigned int rs : 5,
 516         BITFIELD_FIELD(unsigned int c_op : 3,
 517         BITFIELD_FIELD(unsigned int cache : 2,
 518         BITFIELD_FIELD(unsigned int simmediate : 16,
 519         ;)))))
 520 };
 521
 522 struct r_format {                       /* Register format */
 523         BITFIELD_FIELD(unsigned int opcode : 6,
 524         BITFIELD_FIELD(unsigned int rs : 5,
 525         BITFIELD_FIELD(unsigned int rt : 5,
 526         BITFIELD_FIELD(unsigned int rd : 5,
 527         BITFIELD_FIELD(unsigned int re : 5,
 528         BITFIELD_FIELD(unsigned int func : 6,
 529         ;))))))
 530 };
 531
 532 struct p_format {               /* Performance counter format (R10000) */
 533         BITFIELD_FIELD(unsigned int opcode : 6,
 534         BITFIELD_FIELD(unsigned int rs : 5,
 535         BITFIELD_FIELD(unsigned int rt : 5,
 536         BITFIELD_FIELD(unsigned int rd : 5,
 537         BITFIELD_FIELD(unsigned int re : 5,
 538         BITFIELD_FIELD(unsigned int func : 6,
 539         ;))))))
 540 };
 541
 542 struct f_format {                       /* FPU register format */
 543         BITFIELD_FIELD(unsigned int opcode : 6,
 544         BITFIELD_FIELD(unsigned int : 1,
 545         BITFIELD_FIELD(unsigned int fmt : 4,
 546         BITFIELD_FIELD(unsigned int rt : 5,
 547         BITFIELD_FIELD(unsigned int rd : 5,
 548         BITFIELD_FIELD(unsigned int re : 5,
 549         BITFIELD_FIELD(unsigned int func : 6,
 550         ;)))))))
 551 };
 552
 553 struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 554         BITFIELD_FIELD(unsigned int opcode : 6,
 555         BITFIELD_FIELD(unsigned int fr : 5,
 556         BITFIELD_FIELD(unsigned int ft : 5,
 557         BITFIELD_FIELD(unsigned int fs : 5,
 558         BITFIELD_FIELD(unsigned int fd : 5,
 559         BITFIELD_FIELD(unsigned int func : 4,
 560         BITFIELD_FIELD(unsigned int fmt : 2,
 561         ;)))))))
 562 };
 563
 564 struct b_format {                       /* BREAK and SYSCALL */
 565         BITFIELD_FIELD(unsigned int opcode : 6,
 566         BITFIELD_FIELD(unsigned int code : 20,
 567         BITFIELD_FIELD(unsigned int func : 6,
 568         ;)))
 569 };
 570
 571 struct ps_format {                      /* MIPS-3D / paired single format */
 572         BITFIELD_FIELD(unsigned int opcode : 6,
 573         BITFIELD_FIELD(unsigned int rs : 5,
 574         BITFIELD_FIELD(unsigned int ft : 5,
 575         BITFIELD_FIELD(unsigned int fs : 5,
 576         BITFIELD_FIELD(unsigned int fd : 5,
 577         BITFIELD_FIELD(unsigned int func : 6,
 578         ;))))))
 579 };
 580
 581 struct v_format {                               /* MDMX vector format */
 582         BITFIELD_FIELD(unsigned int opcode : 6,
 583         BITFIELD_FIELD(unsigned int sel : 4,
 584         BITFIELD_FIELD(unsigned int fmt : 1,
 585         BITFIELD_FIELD(unsigned int vt : 5,
 586         BITFIELD_FIELD(unsigned int vs : 5,
 587         BITFIELD_FIELD(unsigned int vd : 5,
 588         BITFIELD_FIELD(unsigned int func : 6,
 589         ;)))))))
 590 };
 591
 592 /*
 593  * microMIPS instruction formats (32-bit length)
 594  *
 595  * NOTE:
 596  *      Parenthesis denote whether the format is a microMIPS instruction or
 597  *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 598  */
 599 struct fb_format {              /* FPU branch format (MIPS32) */
 600         BITFIELD_FIELD(unsigned int opcode : 6,
 601         BITFIELD_FIELD(unsigned int bc : 5,
 602         BITFIELD_FIELD(unsigned int cc : 3,
 603         BITFIELD_FIELD(unsigned int flag : 2,
 604         BITFIELD_FIELD(signed int simmediate : 16,
 605         ;)))))
 606 };
 607
 608 struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 609         BITFIELD_FIELD(unsigned int opcode : 6,
 610         BITFIELD_FIELD(unsigned int fmt : 5,
 611         BITFIELD_FIELD(unsigned int ft : 5,
 612         BITFIELD_FIELD(unsigned int fs : 5,
 613         BITFIELD_FIELD(unsigned int fd : 5,
 614         BITFIELD_FIELD(unsigned int func : 6,
 615         ;))))))
 616 };
 617
 618 struct mm_fp0_format {          /* FPU multipy and add format (microMIPS) */
 619         BITFIELD_FIELD(unsigned int opcode : 6,
 620         BITFIELD_FIELD(unsigned int ft : 5,
 621         BITFIELD_FIELD(unsigned int fs : 5,
 622         BITFIELD_FIELD(unsigned int fd : 5,
 623         BITFIELD_FIELD(unsigned int fmt : 3,
 624         BITFIELD_FIELD(unsigned int op : 2,
 625         BITFIELD_FIELD(unsigned int func : 6,
 626         ;)))))))
 627 };
 628
 629 struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 630         BITFIELD_FIELD(unsigned int opcode : 6,
 631         BITFIELD_FIELD(unsigned int op : 5,
 632         BITFIELD_FIELD(unsigned int rt : 5,
 633         BITFIELD_FIELD(unsigned int fs : 5,
 634         BITFIELD_FIELD(unsigned int fd : 5,
 635         BITFIELD_FIELD(unsigned int func : 6,
 636         ;))))))
 637 };
 638
 639 struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 640         BITFIELD_FIELD(unsigned int opcode : 6,
 641         BITFIELD_FIELD(unsigned int rt : 5,
 642         BITFIELD_FIELD(unsigned int fs : 5,
 643         BITFIELD_FIELD(unsigned int fmt : 2,
 644         BITFIELD_FIELD(unsigned int op : 8,
 645         BITFIELD_FIELD(unsigned int func : 6,
 646         ;))))))
 647 };
 648
 649 struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 650         BITFIELD_FIELD(unsigned int opcode : 6,
 651         BITFIELD_FIELD(unsigned int fd : 5,
 652         BITFIELD_FIELD(unsigned int fs : 5,
 653         BITFIELD_FIELD(unsigned int cc : 3,
 654         BITFIELD_FIELD(unsigned int zero : 2,
 655         BITFIELD_FIELD(unsigned int fmt : 2,
 656         BITFIELD_FIELD(unsigned int op : 3,
 657         BITFIELD_FIELD(unsigned int func : 6,
 658         ;))))))))
 659 };
 660
 661 struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 662         BITFIELD_FIELD(unsigned int opcode : 6,
 663         BITFIELD_FIELD(unsigned int rt : 5,
 664         BITFIELD_FIELD(unsigned int fs : 5,
 665         BITFIELD_FIELD(unsigned int fmt : 3,
 666         BITFIELD_FIELD(unsigned int op : 7,
 667         BITFIELD_FIELD(unsigned int func : 6,
 668         ;))))))
 669 };
 670
 671 struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 672         BITFIELD_FIELD(unsigned int opcode : 6,
 673         BITFIELD_FIELD(unsigned int rt : 5,
 674         BITFIELD_FIELD(unsigned int fs : 5,
 675         BITFIELD_FIELD(unsigned int cc : 3,
 676         BITFIELD_FIELD(unsigned int fmt : 3,
 677         BITFIELD_FIELD(unsigned int cond : 4,
 678         BITFIELD_FIELD(unsigned int func : 6,
 679         ;)))))))
 680 };
 681
 682 struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 683         BITFIELD_FIELD(unsigned int opcode : 6,
 684         BITFIELD_FIELD(unsigned int index : 5,
 685         BITFIELD_FIELD(unsigned int base : 5,
 686         BITFIELD_FIELD(unsigned int fd : 5,
 687         BITFIELD_FIELD(unsigned int op : 5,
 688         BITFIELD_FIELD(unsigned int func : 6,
 689         ;))))))
 690 };
 691
 692 struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 693         BITFIELD_FIELD(unsigned int opcode : 6,
 694         BITFIELD_FIELD(unsigned int fr : 5,
 695         BITFIELD_FIELD(unsigned int ft : 5,
 696         BITFIELD_FIELD(unsigned int fs : 5,
 697         BITFIELD_FIELD(unsigned int fd : 5,
 698         BITFIELD_FIELD(unsigned int func : 6,
 699         ;))))))
 700 };
 701
 702 struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 703         BITFIELD_FIELD(unsigned int opcode : 6,
 704         BITFIELD_FIELD(unsigned int ft : 5,
 705         BITFIELD_FIELD(unsigned int fs : 5,
 706         BITFIELD_FIELD(unsigned int fd : 5,
 707         BITFIELD_FIELD(unsigned int fr : 5,
 708         BITFIELD_FIELD(unsigned int func : 6,
 709         ;))))))
 710 };
 711
 712 struct mm_i_format {            /* Immediate format (microMIPS) */
 713         BITFIELD_FIELD(unsigned int opcode : 6,
 714         BITFIELD_FIELD(unsigned int rt : 5,
 715         BITFIELD_FIELD(unsigned int rs : 5,
 716         BITFIELD_FIELD(signed int simmediate : 16,
 717         ;))))
 718 };
 719
 720 struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 721         BITFIELD_FIELD(unsigned int opcode : 6,
 722         BITFIELD_FIELD(unsigned int rd : 5,
 723         BITFIELD_FIELD(unsigned int base : 5,
 724         BITFIELD_FIELD(unsigned int func : 4,
 725         BITFIELD_FIELD(signed int simmediate : 12,
 726         ;)))))
 727 };
 728
 729 struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 730         BITFIELD_FIELD(unsigned int opcode : 6,
 731         BITFIELD_FIELD(unsigned int index : 5,
 732         BITFIELD_FIELD(unsigned int base : 5,
 733         BITFIELD_FIELD(unsigned int rd : 5,
 734         BITFIELD_FIELD(unsigned int func : 11,
 735         ;)))))
 736 };
 737
 738 /*
 739  * microMIPS instruction formats (16-bit length)
 740  */
 741 struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 742         BITFIELD_FIELD(unsigned int opcode : 6,
 743         BITFIELD_FIELD(signed int simmediate : 10,
 744         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 745         ;)))
 746 };
 747
 748 struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 749         BITFIELD_FIELD(unsigned int opcode : 6,
 750         BITFIELD_FIELD(unsigned int rs : 3,
 751         BITFIELD_FIELD(signed int simmediate : 7,
 752         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 753         ;))))
 754 };
 755
 756 struct mm16_m_format {          /* Multi-word load/store format */
 757         BITFIELD_FIELD(unsigned int opcode : 6,
 758         BITFIELD_FIELD(unsigned int func : 4,
 759         BITFIELD_FIELD(unsigned int rlist : 2,
 760         BITFIELD_FIELD(unsigned int imm : 4,
 761         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 762         ;)))))
 763 };
 764
 765 struct mm16_rb_format {         /* Signed immediate format */
 766         BITFIELD_FIELD(unsigned int opcode : 6,
 767         BITFIELD_FIELD(unsigned int rt : 3,
 768         BITFIELD_FIELD(unsigned int base : 3,
 769         BITFIELD_FIELD(signed int simmediate : 4,
 770         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 771         ;)))))
 772 };
 773
 774 struct mm16_r3_format {         /* Load from global pointer format */
 775         BITFIELD_FIELD(unsigned int opcode : 6,
 776         BITFIELD_FIELD(unsigned int rt : 3,
 777         BITFIELD_FIELD(signed int simmediate : 7,
 778         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 779         ;))))
 780 };
 781
 782 struct mm16_r5_format {         /* Load/store from stack pointer format */
 783         BITFIELD_FIELD(unsigned int opcode : 6,
 784         BITFIELD_FIELD(unsigned int rt : 5,
 785         BITFIELD_FIELD(signed int simmediate : 5,
 786         BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 787         ;))))
 788 };
 789
 790 /*
 791  * MIPS16e instruction formats (16-bit length)
 792  */
 793 struct m16e_rr {
 794         BITFIELD_FIELD(unsigned int opcode : 5,
 795         BITFIELD_FIELD(unsigned int rx : 3,
 796         BITFIELD_FIELD(unsigned int nd : 1,
 797         BITFIELD_FIELD(unsigned int l : 1,
 798         BITFIELD_FIELD(unsigned int ra : 1,
 799         BITFIELD_FIELD(unsigned int func : 5,
 800         ;))))))
 801 };
 802
 803 struct m16e_jal {
 804         BITFIELD_FIELD(unsigned int opcode : 5,
 805         BITFIELD_FIELD(unsigned int x : 1,
 806         BITFIELD_FIELD(unsigned int imm20_16 : 5,
 807         BITFIELD_FIELD(signed int imm25_21 : 5,
 808         ;))))
 809 };
 810
 811 struct m16e_i64 {
 812         BITFIELD_FIELD(unsigned int opcode : 5,
 813         BITFIELD_FIELD(unsigned int func : 3,
 814         BITFIELD_FIELD(unsigned int imm : 8,
 815         ;)))
 816 };
 817
 818 struct m16e_ri64 {
 819         BITFIELD_FIELD(unsigned int opcode : 5,
 820         BITFIELD_FIELD(unsigned int func : 3,
 821         BITFIELD_FIELD(unsigned int ry : 3,
 822         BITFIELD_FIELD(unsigned int imm : 5,
 823         ;))))
 824 };
 825
 826 struct m16e_ri {
 827         BITFIELD_FIELD(unsigned int opcode : 5,
 828         BITFIELD_FIELD(unsigned int rx : 3,
 829         BITFIELD_FIELD(unsigned int imm : 8,
 830         ;)))
 831 };
 832
 833 struct m16e_rri {
 834         BITFIELD_FIELD(unsigned int opcode : 5,
 835         BITFIELD_FIELD(unsigned int rx : 3,
 836         BITFIELD_FIELD(unsigned int ry : 3,
 837         BITFIELD_FIELD(unsigned int imm : 5,
 838         ;))))
 839 };
 840
 841 struct m16e_i8 {
 842         BITFIELD_FIELD(unsigned int opcode : 5,
 843         BITFIELD_FIELD(unsigned int func : 3,
 844         BITFIELD_FIELD(unsigned int imm : 8,
 845         ;)))
 846 };
 847
 848 union mips_instruction {
 849         unsigned int word;
 850         unsigned short halfword[2];
 851         unsigned char byte[4];
 852         struct j_format j_format;
 853         struct i_format i_format;
 854         struct u_format u_format;
 855         struct c_format c_format;
 856         struct r_format r_format;
 857         struct p_format p_format;
 858         struct f_format f_format;
 859         struct ma_format ma_format;
 860         struct b_format b_format;
 861         struct ps_format ps_format;
 862         struct v_format v_format;
 863         struct fb_format fb_format;
 864         struct fp0_format fp0_format;
 865         struct mm_fp0_format mm_fp0_format;
 866         struct fp1_format fp1_format;
 867         struct mm_fp1_format mm_fp1_format;
 868         struct mm_fp2_format mm_fp2_format;
 869         struct mm_fp3_format mm_fp3_format;
 870         struct mm_fp4_format mm_fp4_format;
 871         struct mm_fp5_format mm_fp5_format;
 872         struct fp6_format fp6_format;
 873         struct mm_fp6_format mm_fp6_format;
 874         struct mm_i_format mm_i_format;
 875         struct mm_m_format mm_m_format;
 876         struct mm_x_format mm_x_format;
 877         struct mm_b0_format mm_b0_format;
 878         struct mm_b1_format mm_b1_format;
 879         struct mm16_m_format mm16_m_format ;
 880         struct mm16_rb_format mm16_rb_format;
 881         struct mm16_r3_format mm16_r3_format;
 882         struct mm16_r5_format mm16_r5_format;
 883 };
 884
 885 union mips16e_instruction {
 886         unsigned int full : 16;
 887         struct m16e_rr rr;
 888         struct m16e_jal jal;
 889         struct m16e_i64 i64;
 890         struct m16e_ri64 ri64;
 891         struct m16e_ri ri;
 892         struct m16e_rri rri;
 893         struct m16e_i8 i8;
 894 };
 895
 896 #endif /* _UAPI_ASM_INST_H */