2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
26 #include <lantiq_soc.h>
29 #define LTQ_DMA_ID 0x08
30 #define LTQ_DMA_CTRL 0x10
31 #define LTQ_DMA_CPOLL 0x14
32 #define LTQ_DMA_CS 0x18
33 #define LTQ_DMA_CCTRL 0x1C
34 #define LTQ_DMA_CDBA 0x20
35 #define LTQ_DMA_CDLEN 0x24
36 #define LTQ_DMA_CIS 0x28
37 #define LTQ_DMA_CIE 0x2C
38 #define LTQ_DMA_PS 0x40
39 #define LTQ_DMA_PCTRL 0x44
40 #define LTQ_DMA_IRNEN 0xf4
42 #define DMA_DESCPT BIT(3) /* descriptor complete irq */
43 #define DMA_TX BIT(8) /* TX channel direction */
44 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */
45 #define DMA_PDEN BIT(6) /* enable packet drop */
46 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */
47 #define DMA_RESET BIT(0) /* channel on / off bit */
48 #define DMA_IRQ_ACK 0x7e /* IRQ status register */
49 #define DMA_POLL BIT(31) /* turn on channel polling */
50 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
51 #define DMA_2W_BURST BIT(1) /* 2 word burst length */
52 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
53 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
54 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
56 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
57 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
58 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
59 ltq_dma_membase + (z))
61 static void __iomem
*ltq_dma_membase
;
64 ltq_dma_enable_irq(struct ltq_dma_channel
*ch
)
68 local_irq_save(flags
);
69 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
70 ltq_dma_w32_mask(0, 1 << ch
->nr
, LTQ_DMA_IRNEN
);
71 local_irq_restore(flags
);
73 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq
);
76 ltq_dma_disable_irq(struct ltq_dma_channel
*ch
)
80 local_irq_save(flags
);
81 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
82 ltq_dma_w32_mask(1 << ch
->nr
, 0, LTQ_DMA_IRNEN
);
83 local_irq_restore(flags
);
85 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq
);
88 ltq_dma_ack_irq(struct ltq_dma_channel
*ch
)
92 local_irq_save(flags
);
93 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
94 ltq_dma_w32(DMA_IRQ_ACK
, LTQ_DMA_CIS
);
95 local_irq_restore(flags
);
97 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq
);
100 ltq_dma_open(struct ltq_dma_channel
*ch
)
104 local_irq_save(flag
);
105 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
106 ltq_dma_w32_mask(0, DMA_CHAN_ON
, LTQ_DMA_CCTRL
);
107 ltq_dma_enable_irq(ch
);
108 local_irq_restore(flag
);
110 EXPORT_SYMBOL_GPL(ltq_dma_open
);
113 ltq_dma_close(struct ltq_dma_channel
*ch
)
117 local_irq_save(flag
);
118 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
119 ltq_dma_w32_mask(DMA_CHAN_ON
, 0, LTQ_DMA_CCTRL
);
120 ltq_dma_disable_irq(ch
);
121 local_irq_restore(flag
);
123 EXPORT_SYMBOL_GPL(ltq_dma_close
);
126 ltq_dma_alloc(struct ltq_dma_channel
*ch
)
131 ch
->desc_base
= dma_alloc_coherent(NULL
,
132 LTQ_DESC_NUM
* LTQ_DESC_SIZE
,
133 &ch
->phys
, GFP_ATOMIC
);
134 memset(ch
->desc_base
, 0, LTQ_DESC_NUM
* LTQ_DESC_SIZE
);
136 local_irq_save(flags
);
137 ltq_dma_w32(ch
->nr
, LTQ_DMA_CS
);
138 ltq_dma_w32(ch
->phys
, LTQ_DMA_CDBA
);
139 ltq_dma_w32(LTQ_DESC_NUM
, LTQ_DMA_CDLEN
);
140 ltq_dma_w32_mask(DMA_CHAN_ON
, 0, LTQ_DMA_CCTRL
);
142 ltq_dma_w32_mask(0, DMA_CHAN_RST
, LTQ_DMA_CCTRL
);
143 while (ltq_dma_r32(LTQ_DMA_CCTRL
) & DMA_CHAN_RST
)
145 local_irq_restore(flags
);
149 ltq_dma_alloc_tx(struct ltq_dma_channel
*ch
)
155 local_irq_save(flags
);
156 ltq_dma_w32(DMA_DESCPT
, LTQ_DMA_CIE
);
157 ltq_dma_w32_mask(0, 1 << ch
->nr
, LTQ_DMA_IRNEN
);
158 ltq_dma_w32(DMA_WEIGHT
| DMA_TX
, LTQ_DMA_CCTRL
);
159 local_irq_restore(flags
);
161 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx
);
164 ltq_dma_alloc_rx(struct ltq_dma_channel
*ch
)
170 local_irq_save(flags
);
171 ltq_dma_w32(DMA_DESCPT
, LTQ_DMA_CIE
);
172 ltq_dma_w32_mask(0, 1 << ch
->nr
, LTQ_DMA_IRNEN
);
173 ltq_dma_w32(DMA_WEIGHT
, LTQ_DMA_CCTRL
);
174 local_irq_restore(flags
);
176 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx
);
179 ltq_dma_free(struct ltq_dma_channel
*ch
)
184 dma_free_coherent(NULL
, LTQ_DESC_NUM
* LTQ_DESC_SIZE
,
185 ch
->desc_base
, ch
->phys
);
187 EXPORT_SYMBOL_GPL(ltq_dma_free
);
190 ltq_dma_init_port(int p
)
192 ltq_dma_w32(p
, LTQ_DMA_PS
);
196 * Tell the DMA engine to swap the endianness of data frames and
197 * drop packets if the channel arbitration fails.
199 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS
| DMA_PDEN
,
204 ltq_dma_w32((DMA_2W_BURST
<< 4) | (DMA_2W_BURST
<< 2),
212 EXPORT_SYMBOL_GPL(ltq_dma_init_port
);
215 ltq_dma_init(struct platform_device
*pdev
)
218 struct resource
*res
;
222 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
224 panic("Failed to get dma resource");
226 /* remap dma register range */
227 ltq_dma_membase
= devm_ioremap_resource(&pdev
->dev
, res
);
228 if (IS_ERR(ltq_dma_membase
))
229 panic("Failed to remap dma resource");
231 /* power up and reset the dma engine */
232 clk
= clk_get(&pdev
->dev
, NULL
);
234 panic("Failed to get dma clock");
237 ltq_dma_w32_mask(0, DMA_RESET
, LTQ_DMA_CTRL
);
239 /* disable all interrupts */
240 ltq_dma_w32(0, LTQ_DMA_IRNEN
);
242 /* reset/configure each channel */
243 for (i
= 0; i
< DMA_MAX_CHANNEL
; i
++) {
244 ltq_dma_w32(i
, LTQ_DMA_CS
);
245 ltq_dma_w32(DMA_CHAN_RST
, LTQ_DMA_CCTRL
);
246 ltq_dma_w32(DMA_POLL
| DMA_CLK_DIV4
, LTQ_DMA_CPOLL
);
247 ltq_dma_w32_mask(DMA_CHAN_ON
, 0, LTQ_DMA_CCTRL
);
250 id
= ltq_dma_r32(LTQ_DMA_ID
);
252 "Init done - hw rev: %X, ports: %d, channels: %d\n",
253 id
& 0x1f, (id
>> 16) & 0xf, id
>> 20);
258 static const struct of_device_id dma_match
[] = {
259 { .compatible
= "lantiq,dma-xway" },
262 MODULE_DEVICE_TABLE(of
, dma_match
);
264 static struct platform_driver dma_driver
= {
265 .probe
= ltq_dma_init
,
268 .owner
= THIS_MODULE
,
269 .of_match_table
= dma_match
,
276 return platform_driver_register(&dma_driver
);
279 postcore_initcall(dma_init
);