2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/cache.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cpu-type.h>
34 #include <asm/pgtable.h>
37 #include <asm/setup.h>
40 * TLB load/store/modify handlers.
42 * Only the fastpath gets synthesized at runtime, the slowpath for
43 * do_page_fault remains normal asm.
45 extern void tlb_do_page_fault_0(void);
46 extern void tlb_do_page_fault_1(void);
48 struct work_registers
{
57 } ____cacheline_aligned_in_smp
;
59 static struct tlb_reg_save handler_reg_save
[NR_CPUS
];
61 static inline int r45k_bvahwbug(void)
63 /* XXX: We should probe for the presence of this bug, but we don't. */
67 static inline int r4k_250MHZhwbug(void)
69 /* XXX: We should probe for the presence of this bug, but we don't. */
73 static inline int __maybe_unused
bcm1250_m3_war(void)
75 return BCM1250_M3_WAR
;
78 static inline int __maybe_unused
r10000_llsc_war(void)
80 return R10000_LLSC_WAR
;
83 static int use_bbit_insns(void)
85 switch (current_cpu_type()) {
86 case CPU_CAVIUM_OCTEON
:
87 case CPU_CAVIUM_OCTEON_PLUS
:
88 case CPU_CAVIUM_OCTEON2
:
89 case CPU_CAVIUM_OCTEON3
:
96 static int use_lwx_insns(void)
98 switch (current_cpu_type()) {
99 case CPU_CAVIUM_OCTEON2
:
100 case CPU_CAVIUM_OCTEON3
:
106 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
107 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
108 static bool scratchpad_available(void)
112 static int scratchpad_offset(int i
)
115 * CVMSEG starts at address -32768 and extends for
116 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
118 i
+= 1; /* Kernel use starts at the top and works down. */
119 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
* 128 - (8 * i
) - 32768;
122 static bool scratchpad_available(void)
126 static int scratchpad_offset(int i
)
129 /* Really unreachable, but evidently some GCC want this. */
134 * Found by experiment: At least some revisions of the 4kc throw under
135 * some circumstances a machine check exception, triggered by invalid
136 * values in the index register. Delaying the tlbp instruction until
137 * after the next branch, plus adding an additional nop in front of
138 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
139 * why; it's not an issue caused by the core RTL.
142 static int m4kc_tlbp_war(void)
144 return (current_cpu_data
.processor_id
& 0xffff00) ==
145 (PRID_COMP_MIPS
| PRID_IMP_4KC
);
148 /* Handle labels (which must be positive integers). */
150 label_second_part
= 1,
155 label_split
= label_tlbw_hazard_0
+ 8,
156 label_tlbl_goaround1
,
157 label_tlbl_goaround2
,
161 label_smp_pgtable_change
,
162 label_r3000_write_probe_fail
,
163 label_large_segbits_fault
,
164 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
165 label_tlb_huge_update
,
169 UASM_L_LA(_second_part
)
172 UASM_L_LA(_vmalloc_done
)
173 /* _tlbw_hazard_x is handled differently. */
175 UASM_L_LA(_tlbl_goaround1
)
176 UASM_L_LA(_tlbl_goaround2
)
177 UASM_L_LA(_nopage_tlbl
)
178 UASM_L_LA(_nopage_tlbs
)
179 UASM_L_LA(_nopage_tlbm
)
180 UASM_L_LA(_smp_pgtable_change
)
181 UASM_L_LA(_r3000_write_probe_fail
)
182 UASM_L_LA(_large_segbits_fault
)
183 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
184 UASM_L_LA(_tlb_huge_update
)
187 static int hazard_instance
;
189 static void uasm_bgezl_hazard(u32
**p
, struct uasm_reloc
**r
, int instance
)
193 uasm_il_bgezl(p
, r
, 0, label_tlbw_hazard_0
+ instance
);
200 static void uasm_bgezl_label(struct uasm_label
**l
, u32
**p
, int instance
)
204 uasm_build_label(l
, *p
, label_tlbw_hazard_0
+ instance
);
212 * pgtable bits are assigned dynamically depending on processor feature
213 * and statically based on kernel configuration. This spits out the actual
214 * values the kernel is using. Required to make sense from disassembled
215 * TLB exception handlers.
217 static void output_pgtable_bits_defines(void)
219 #define pr_define(fmt, ...) \
220 pr_debug("#define " fmt, ##__VA_ARGS__)
222 pr_debug("#include <asm/asm.h>\n");
223 pr_debug("#include <asm/regdef.h>\n");
226 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT
);
227 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT
);
228 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT
);
229 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT
);
230 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT
);
231 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
232 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT
);
233 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT
);
236 #ifdef _PAGE_NO_EXEC_SHIFT
237 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT
);
239 #ifdef _PAGE_NO_READ_SHIFT
240 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT
);
243 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT
);
244 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT
);
245 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT
);
246 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT
);
250 static inline void dump_handler(const char *symbol
, const u32
*handler
, int count
)
254 pr_debug("LEAF(%s)\n", symbol
);
256 pr_debug("\t.set push\n");
257 pr_debug("\t.set noreorder\n");
259 for (i
= 0; i
< count
; i
++)
260 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler
[i
], &handler
[i
]);
262 pr_debug("\t.set\tpop\n");
264 pr_debug("\tEND(%s)\n", symbol
);
267 /* The only general purpose registers allowed in TLB handlers. */
271 /* Some CP0 registers */
272 #define C0_INDEX 0, 0
273 #define C0_ENTRYLO0 2, 0
274 #define C0_TCBIND 2, 2
275 #define C0_ENTRYLO1 3, 0
276 #define C0_CONTEXT 4, 0
277 #define C0_PAGEMASK 5, 0
278 #define C0_BADVADDR 8, 0
279 #define C0_ENTRYHI 10, 0
281 #define C0_XCONTEXT 20, 0
284 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
286 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
289 /* The worst case length of the handler is around 18 instructions for
290 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
291 * Maximum space available is 32 instructions for R3000 and 64
292 * instructions for R4000.
294 * We deliberately chose a buffer size of 128, so we won't scribble
295 * over anything important on overflow before we panic.
297 static u32 tlb_handler
[128];
299 /* simply assume worst case size for labels and relocs */
300 static struct uasm_label labels
[128];
301 static struct uasm_reloc relocs
[128];
303 static int check_for_high_segbits
;
305 static unsigned int kscratch_used_mask
;
307 static inline int __maybe_unused
c0_kscratch(void)
309 switch (current_cpu_type()) {
318 static int allocate_kscratch(void)
321 unsigned int a
= cpu_data
[0].kscratch_mask
& ~kscratch_used_mask
;
328 r
--; /* make it zero based */
330 kscratch_used_mask
|= (1 << r
);
335 static int scratch_reg
;
337 enum vmalloc64_mode
{not_refill
, refill_scratch
, refill_noscratch
};
339 static struct work_registers
build_get_work_registers(u32
**p
)
341 struct work_registers r
;
343 int smp_processor_id_reg
;
344 int smp_processor_id_sel
;
345 int smp_processor_id_shift
;
347 if (scratch_reg
>= 0) {
348 /* Save in CPU local C0_KScratch? */
349 UASM_i_MTC0(p
, 1, c0_kscratch(), scratch_reg
);
356 if (num_possible_cpus() > 1) {
357 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
358 smp_processor_id_shift
= 51;
359 smp_processor_id_reg
= 20; /* XContext */
360 smp_processor_id_sel
= 0;
363 smp_processor_id_shift
= 25;
364 smp_processor_id_reg
= 4; /* Context */
365 smp_processor_id_sel
= 0;
368 smp_processor_id_shift
= 26;
369 smp_processor_id_reg
= 4; /* Context */
370 smp_processor_id_sel
= 0;
373 /* Get smp_processor_id */
374 UASM_i_MFC0(p
, K0
, smp_processor_id_reg
, smp_processor_id_sel
);
375 UASM_i_SRL_SAFE(p
, K0
, K0
, smp_processor_id_shift
);
377 /* handler_reg_save index in K0 */
378 UASM_i_SLL(p
, K0
, K0
, ilog2(sizeof(struct tlb_reg_save
)));
380 UASM_i_LA(p
, K1
, (long)&handler_reg_save
);
381 UASM_i_ADDU(p
, K0
, K0
, K1
);
383 UASM_i_LA(p
, K0
, (long)&handler_reg_save
);
385 /* K0 now points to save area, save $1 and $2 */
386 UASM_i_SW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
387 UASM_i_SW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
395 static void build_restore_work_registers(u32
**p
)
397 if (scratch_reg
>= 0) {
398 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
401 /* K0 already points to save area, restore $1 and $2 */
402 UASM_i_LW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
403 UASM_i_LW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
406 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
409 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
410 * we cannot do r3000 under these circumstances.
412 * Declare pgd_current here instead of including mmu_context.h to avoid type
413 * conflicts for tlbmiss_handler_setup_pgd
415 extern unsigned long pgd_current
[];
418 * The R3000 TLB handler is simple.
420 static void build_r3000_tlb_refill_handler(void)
422 long pgdc
= (long)pgd_current
;
425 memset(tlb_handler
, 0, sizeof(tlb_handler
));
428 uasm_i_mfc0(&p
, K0
, C0_BADVADDR
);
429 uasm_i_lui(&p
, K1
, uasm_rel_hi(pgdc
)); /* cp0 delay */
430 uasm_i_lw(&p
, K1
, uasm_rel_lo(pgdc
), K1
);
431 uasm_i_srl(&p
, K0
, K0
, 22); /* load delay */
432 uasm_i_sll(&p
, K0
, K0
, 2);
433 uasm_i_addu(&p
, K1
, K1
, K0
);
434 uasm_i_mfc0(&p
, K0
, C0_CONTEXT
);
435 uasm_i_lw(&p
, K1
, 0, K1
); /* cp0 delay */
436 uasm_i_andi(&p
, K0
, K0
, 0xffc); /* load delay */
437 uasm_i_addu(&p
, K1
, K1
, K0
);
438 uasm_i_lw(&p
, K0
, 0, K1
);
439 uasm_i_nop(&p
); /* load delay */
440 uasm_i_mtc0(&p
, K0
, C0_ENTRYLO0
);
441 uasm_i_mfc0(&p
, K1
, C0_EPC
); /* cp0 delay */
442 uasm_i_tlbwr(&p
); /* cp0 delay */
444 uasm_i_rfe(&p
); /* branch delay */
446 if (p
> tlb_handler
+ 32)
447 panic("TLB refill handler space exceeded");
449 pr_debug("Wrote TLB refill handler (%u instructions).\n",
450 (unsigned int)(p
- tlb_handler
));
452 memcpy((void *)ebase
, tlb_handler
, 0x80);
454 dump_handler("r3000_tlb_refill", (u32
*)ebase
, 32);
456 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
459 * The R4000 TLB handler is much more complicated. We have two
460 * consecutive handler areas with 32 instructions space each.
461 * Since they aren't used at the same time, we can overflow in the
462 * other one.To keep things simple, we first assume linear space,
463 * then we relocate it to the final handler layout as needed.
465 static u32 final_handler
[64];
470 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
471 * 2. A timing hazard exists for the TLBP instruction.
473 * stalling_instruction
476 * The JTLB is being read for the TLBP throughout the stall generated by the
477 * previous instruction. This is not really correct as the stalling instruction
478 * can modify the address used to access the JTLB. The failure symptom is that
479 * the TLBP instruction will use an address created for the stalling instruction
480 * and not the address held in C0_ENHI and thus report the wrong results.
482 * The software work-around is to not allow the instruction preceding the TLBP
483 * to stall - make it an NOP or some other instruction guaranteed not to stall.
485 * Errata 2 will not be fixed. This errata is also on the R5000.
487 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
489 static void __maybe_unused
build_tlb_probe_entry(u32
**p
)
491 switch (current_cpu_type()) {
492 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
508 * Write random or indexed TLB entry, and care about the hazards from
509 * the preceding mtc0 and for the following eret.
511 enum tlb_write_entry
{ tlb_random
, tlb_indexed
};
513 static void build_tlb_write_entry(u32
**p
, struct uasm_label
**l
,
514 struct uasm_reloc
**r
,
515 enum tlb_write_entry wmode
)
517 void(*tlbw
)(u32
**) = NULL
;
520 case tlb_random
: tlbw
= uasm_i_tlbwr
; break;
521 case tlb_indexed
: tlbw
= uasm_i_tlbwi
; break;
524 if (cpu_has_mips_r2
) {
526 * The architecture spec says an ehb is required here,
527 * but a number of cores do not have the hazard and
528 * using an ehb causes an expensive pipeline stall.
530 switch (current_cpu_type()) {
543 switch (current_cpu_type()) {
551 * This branch uses up a mtc0 hazard nop slot and saves
552 * two nops after the tlbw instruction.
554 uasm_bgezl_hazard(p
, r
, hazard_instance
);
556 uasm_bgezl_label(l
, p
, hazard_instance
);
570 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
571 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
643 panic("No TLB refill handler yet (CPU type: %d)",
644 current_cpu_data
.cputype
);
649 static __maybe_unused
void build_convert_pte_to_entrylo(u32
**p
,
653 UASM_i_ROTR(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
655 #ifdef CONFIG_64BIT_PHYS_ADDR
656 uasm_i_dsrl_safe(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
658 UASM_i_SRL(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
663 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
665 static void build_restore_pagemask(u32
**p
, struct uasm_reloc
**r
,
666 unsigned int tmp
, enum label_id lid
,
669 if (restore_scratch
) {
670 /* Reset default page size */
671 if (PM_DEFAULT_MASK
>> 16) {
672 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
673 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
674 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
675 uasm_il_b(p
, r
, lid
);
676 } else if (PM_DEFAULT_MASK
) {
677 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
678 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
679 uasm_il_b(p
, r
, lid
);
681 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
682 uasm_il_b(p
, r
, lid
);
684 if (scratch_reg
>= 0)
685 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
687 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
689 /* Reset default page size */
690 if (PM_DEFAULT_MASK
>> 16) {
691 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
692 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
693 uasm_il_b(p
, r
, lid
);
694 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
695 } else if (PM_DEFAULT_MASK
) {
696 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
697 uasm_il_b(p
, r
, lid
);
698 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
700 uasm_il_b(p
, r
, lid
);
701 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
706 static void build_huge_tlb_write_entry(u32
**p
, struct uasm_label
**l
,
707 struct uasm_reloc
**r
,
709 enum tlb_write_entry wmode
,
712 /* Set huge page tlb entry size */
713 uasm_i_lui(p
, tmp
, PM_HUGE_MASK
>> 16);
714 uasm_i_ori(p
, tmp
, tmp
, PM_HUGE_MASK
& 0xffff);
715 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
717 build_tlb_write_entry(p
, l
, r
, wmode
);
719 build_restore_pagemask(p
, r
, tmp
, label_leave
, restore_scratch
);
723 * Check if Huge PTE is present, if so then jump to LABEL.
726 build_is_huge_pte(u32
**p
, struct uasm_reloc
**r
, unsigned int tmp
,
727 unsigned int pmd
, int lid
)
729 UASM_i_LW(p
, tmp
, 0, pmd
);
730 if (use_bbit_insns()) {
731 uasm_il_bbit1(p
, r
, tmp
, ilog2(_PAGE_HUGE
), lid
);
733 uasm_i_andi(p
, tmp
, tmp
, _PAGE_HUGE
);
734 uasm_il_bnez(p
, r
, tmp
, lid
);
738 static void build_huge_update_entries(u32
**p
, unsigned int pte
,
744 * A huge PTE describes an area the size of the
745 * configured huge page size. This is twice the
746 * of the large TLB entry size we intend to use.
747 * A TLB entry half the size of the configured
748 * huge page size is configured into entrylo0
749 * and entrylo1 to cover the contiguous huge PTE
752 small_sequence
= (HPAGE_SIZE
>> 7) < 0x10000;
754 /* We can clobber tmp. It isn't used after this.*/
756 uasm_i_lui(p
, tmp
, HPAGE_SIZE
>> (7 + 16));
758 build_convert_pte_to_entrylo(p
, pte
);
759 UASM_i_MTC0(p
, pte
, C0_ENTRYLO0
); /* load it */
760 /* convert to entrylo1 */
762 UASM_i_ADDIU(p
, pte
, pte
, HPAGE_SIZE
>> 7);
764 UASM_i_ADDU(p
, pte
, pte
, tmp
);
766 UASM_i_MTC0(p
, pte
, C0_ENTRYLO1
); /* load it */
769 static void build_huge_handler_tail(u32
**p
, struct uasm_reloc
**r
,
770 struct uasm_label
**l
,
775 UASM_i_SC(p
, pte
, 0, ptr
);
776 uasm_il_beqz(p
, r
, pte
, label_tlb_huge_update
);
777 UASM_i_LW(p
, pte
, 0, ptr
); /* Needed because SC killed our PTE */
779 UASM_i_SW(p
, pte
, 0, ptr
);
781 build_huge_update_entries(p
, pte
, ptr
);
782 build_huge_tlb_write_entry(p
, l
, r
, pte
, tlb_indexed
, 0);
784 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
788 * TMP and PTR are scratch.
789 * TMP will be clobbered, PTR will hold the pmd entry.
792 build_get_pmde64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
793 unsigned int tmp
, unsigned int ptr
)
795 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
796 long pgdc
= (long)pgd_current
;
799 * The vmalloc handling is not in the hotpath.
801 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
803 if (check_for_high_segbits
) {
805 * The kernel currently implicitely assumes that the
806 * MIPS SEGBITS parameter for the processor is
807 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
808 * allocate virtual addresses outside the maximum
809 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
810 * that doesn't prevent user code from accessing the
811 * higher xuseg addresses. Here, we make sure that
812 * everything but the lower xuseg addresses goes down
813 * the module_alloc/vmalloc path.
815 uasm_i_dsrl_safe(p
, ptr
, tmp
, PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
816 uasm_il_bnez(p
, r
, ptr
, label_vmalloc
);
818 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
820 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
822 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
824 /* pgd is in pgd_reg */
825 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
828 * &pgd << 11 stored in CONTEXT [23..63].
830 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
832 /* Clear lower 23 bits of context. */
833 uasm_i_dins(p
, ptr
, 0, 0, 23);
835 /* 1 0 1 0 1 << 6 xkphys cached */
836 uasm_i_ori(p
, ptr
, ptr
, 0x540);
837 uasm_i_drotr(p
, ptr
, ptr
, 11);
839 #elif defined(CONFIG_SMP)
840 # ifdef CONFIG_MIPS_MT_SMTC
842 * SMTC uses TCBind value as "CPU" index
844 uasm_i_mfc0(p
, ptr
, C0_TCBIND
);
845 uasm_i_dsrl_safe(p
, ptr
, ptr
, 19);
848 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
851 uasm_i_dmfc0(p
, ptr
, C0_CONTEXT
);
852 uasm_i_dsrl_safe(p
, ptr
, ptr
, 23);
854 UASM_i_LA_mostly(p
, tmp
, pgdc
);
855 uasm_i_daddu(p
, ptr
, ptr
, tmp
);
856 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
857 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
859 UASM_i_LA_mostly(p
, ptr
, pgdc
);
860 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
863 uasm_l_vmalloc_done(l
, *p
);
865 /* get pgd offset in bytes */
866 uasm_i_dsrl_safe(p
, tmp
, tmp
, PGDIR_SHIFT
- 3);
868 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PGD
- 1)<<3);
869 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
870 #ifndef __PAGETABLE_PMD_FOLDED
871 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
872 uasm_i_ld(p
, ptr
, 0, ptr
); /* get pmd pointer */
873 uasm_i_dsrl_safe(p
, tmp
, tmp
, PMD_SHIFT
-3); /* get pmd offset in bytes */
874 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PMD
- 1)<<3);
875 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pmd offset */
880 * BVADDR is the faulting address, PTR is scratch.
881 * PTR will hold the pgd for vmalloc.
884 build_get_pgd_vmalloc64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
885 unsigned int bvaddr
, unsigned int ptr
,
886 enum vmalloc64_mode mode
)
888 long swpd
= (long)swapper_pg_dir
;
889 int single_insn_swpd
;
890 int did_vmalloc_branch
= 0;
892 single_insn_swpd
= uasm_in_compat_space_p(swpd
) && !uasm_rel_lo(swpd
);
894 uasm_l_vmalloc(l
, *p
);
896 if (mode
!= not_refill
&& check_for_high_segbits
) {
897 if (single_insn_swpd
) {
898 uasm_il_bltz(p
, r
, bvaddr
, label_vmalloc_done
);
899 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
900 did_vmalloc_branch
= 1;
903 uasm_il_bgez(p
, r
, bvaddr
, label_large_segbits_fault
);
906 if (!did_vmalloc_branch
) {
907 if (uasm_in_compat_space_p(swpd
) && !uasm_rel_lo(swpd
)) {
908 uasm_il_b(p
, r
, label_vmalloc_done
);
909 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
911 UASM_i_LA_mostly(p
, ptr
, swpd
);
912 uasm_il_b(p
, r
, label_vmalloc_done
);
913 if (uasm_in_compat_space_p(swpd
))
914 uasm_i_addiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
916 uasm_i_daddiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
919 if (mode
!= not_refill
&& check_for_high_segbits
) {
920 uasm_l_large_segbits_fault(l
, *p
);
922 * We get here if we are an xsseg address, or if we are
923 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
925 * Ignoring xsseg (assume disabled so would generate
926 * (address errors?), the only remaining possibility
927 * is the upper xuseg addresses. On processors with
928 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
929 * addresses would have taken an address error. We try
930 * to mimic that here by taking a load/istream page
933 UASM_i_LA(p
, ptr
, (unsigned long)tlb_do_page_fault_0
);
936 if (mode
== refill_scratch
) {
937 if (scratch_reg
>= 0)
938 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
940 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
947 #else /* !CONFIG_64BIT */
950 * TMP and PTR are scratch.
951 * TMP will be clobbered, PTR will hold the pgd entry.
953 static void __maybe_unused
954 build_get_pgde32(u32
**p
, unsigned int tmp
, unsigned int ptr
)
956 long pgdc
= (long)pgd_current
;
958 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
960 #ifdef CONFIG_MIPS_MT_SMTC
962 * SMTC uses TCBind value as "CPU" index
964 uasm_i_mfc0(p
, ptr
, C0_TCBIND
);
965 UASM_i_LA_mostly(p
, tmp
, pgdc
);
966 uasm_i_srl(p
, ptr
, ptr
, 19);
969 * smp_processor_id() << 2 is stored in CONTEXT.
971 uasm_i_mfc0(p
, ptr
, C0_CONTEXT
);
972 UASM_i_LA_mostly(p
, tmp
, pgdc
);
973 uasm_i_srl(p
, ptr
, ptr
, 23);
975 uasm_i_addu(p
, ptr
, tmp
, ptr
);
977 UASM_i_LA_mostly(p
, ptr
, pgdc
);
979 uasm_i_mfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
980 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
981 uasm_i_srl(p
, tmp
, tmp
, PGDIR_SHIFT
); /* get pgd only bits */
982 uasm_i_sll(p
, tmp
, tmp
, PGD_T_LOG2
);
983 uasm_i_addu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
986 #endif /* !CONFIG_64BIT */
988 static void build_adjust_context(u32
**p
, unsigned int ctx
)
990 unsigned int shift
= 4 - (PTE_T_LOG2
+ 1) + PAGE_SHIFT
- 12;
991 unsigned int mask
= (PTRS_PER_PTE
/ 2 - 1) << (PTE_T_LOG2
+ 1);
993 switch (current_cpu_type()) {
1010 UASM_i_SRL(p
, ctx
, ctx
, shift
);
1011 uasm_i_andi(p
, ctx
, ctx
, mask
);
1014 static void build_get_ptep(u32
**p
, unsigned int tmp
, unsigned int ptr
)
1017 * Bug workaround for the Nevada. It seems as if under certain
1018 * circumstances the move from cp0_context might produce a
1019 * bogus result when the mfc0 instruction and its consumer are
1020 * in a different cacheline or a load instruction, probably any
1021 * memory reference, is between them.
1023 switch (current_cpu_type()) {
1025 UASM_i_LW(p
, ptr
, 0, ptr
);
1026 GET_CONTEXT(p
, tmp
); /* get context reg */
1030 GET_CONTEXT(p
, tmp
); /* get context reg */
1031 UASM_i_LW(p
, ptr
, 0, ptr
);
1035 build_adjust_context(p
, tmp
);
1036 UASM_i_ADDU(p
, ptr
, ptr
, tmp
); /* add in offset */
1039 static void build_update_entries(u32
**p
, unsigned int tmp
, unsigned int ptep
)
1042 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1043 * Kernel is a special case. Only a few CPUs use it.
1045 #ifdef CONFIG_64BIT_PHYS_ADDR
1046 if (cpu_has_64bits
) {
1047 uasm_i_ld(p
, tmp
, 0, ptep
); /* get even pte */
1048 uasm_i_ld(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1050 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1051 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1052 UASM_i_ROTR(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
));
1054 uasm_i_dsrl_safe(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo0 */
1055 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1056 uasm_i_dsrl_safe(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo1 */
1058 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1060 int pte_off_even
= sizeof(pte_t
) / 2;
1061 int pte_off_odd
= pte_off_even
+ sizeof(pte_t
);
1063 /* The pte entries are pre-shifted */
1064 uasm_i_lw(p
, tmp
, pte_off_even
, ptep
); /* get even pte */
1065 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1066 uasm_i_lw(p
, ptep
, pte_off_odd
, ptep
); /* get odd pte */
1067 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1070 UASM_i_LW(p
, tmp
, 0, ptep
); /* get even pte */
1071 UASM_i_LW(p
, ptep
, sizeof(pte_t
), ptep
); /* get odd pte */
1072 if (r45k_bvahwbug())
1073 build_tlb_probe_entry(p
);
1075 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1076 if (r4k_250MHZhwbug())
1077 UASM_i_MTC0(p
, 0, C0_ENTRYLO0
);
1078 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1079 UASM_i_ROTR(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
));
1081 UASM_i_SRL(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo0 */
1082 if (r4k_250MHZhwbug())
1083 UASM_i_MTC0(p
, 0, C0_ENTRYLO0
);
1084 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1085 UASM_i_SRL(p
, ptep
, ptep
, ilog2(_PAGE_GLOBAL
)); /* convert to entrylo1 */
1086 if (r45k_bvahwbug())
1087 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1089 if (r4k_250MHZhwbug())
1090 UASM_i_MTC0(p
, 0, C0_ENTRYLO1
);
1091 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1095 struct mips_huge_tlb_info
{
1097 int restore_scratch
;
1100 static struct mips_huge_tlb_info
1101 build_fast_tlb_refill_handler (u32
**p
, struct uasm_label
**l
,
1102 struct uasm_reloc
**r
, unsigned int tmp
,
1103 unsigned int ptr
, int c0_scratch_reg
)
1105 struct mips_huge_tlb_info rv
;
1106 unsigned int even
, odd
;
1107 int vmalloc_branch_delay_filled
= 0;
1108 const int scratch
= 1; /* Our extra working register */
1110 rv
.huge_pte
= scratch
;
1111 rv
.restore_scratch
= 0;
1113 if (check_for_high_segbits
) {
1114 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1117 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1119 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1121 if (c0_scratch_reg
>= 0)
1122 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1124 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1126 uasm_i_dsrl_safe(p
, scratch
, tmp
,
1127 PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
1128 uasm_il_bnez(p
, r
, scratch
, label_vmalloc
);
1130 if (pgd_reg
== -1) {
1131 vmalloc_branch_delay_filled
= 1;
1132 /* Clear lower 23 bits of context. */
1133 uasm_i_dins(p
, ptr
, 0, 0, 23);
1137 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1139 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1141 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1143 if (c0_scratch_reg
>= 0)
1144 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1146 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1149 /* Clear lower 23 bits of context. */
1150 uasm_i_dins(p
, ptr
, 0, 0, 23);
1152 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
1155 if (pgd_reg
== -1) {
1156 vmalloc_branch_delay_filled
= 1;
1157 /* 1 0 1 0 1 << 6 xkphys cached */
1158 uasm_i_ori(p
, ptr
, ptr
, 0x540);
1159 uasm_i_drotr(p
, ptr
, ptr
, 11);
1162 #ifdef __PAGETABLE_PMD_FOLDED
1163 #define LOC_PTEP scratch
1165 #define LOC_PTEP ptr
1168 if (!vmalloc_branch_delay_filled
)
1169 /* get pgd offset in bytes */
1170 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1172 uasm_l_vmalloc_done(l
, *p
);
1176 * fall-through case = badvaddr *pgd_current
1177 * vmalloc case = badvaddr swapper_pg_dir
1180 if (vmalloc_branch_delay_filled
)
1181 /* get pgd offset in bytes */
1182 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1184 #ifdef __PAGETABLE_PMD_FOLDED
1185 GET_CONTEXT(p
, tmp
); /* get context reg */
1187 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PGD
- 1) << 3);
1189 if (use_lwx_insns()) {
1190 UASM_i_LWX(p
, LOC_PTEP
, scratch
, ptr
);
1192 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pgd offset */
1193 uasm_i_ld(p
, LOC_PTEP
, 0, ptr
); /* get pmd pointer */
1196 #ifndef __PAGETABLE_PMD_FOLDED
1197 /* get pmd offset in bytes */
1198 uasm_i_dsrl_safe(p
, scratch
, tmp
, PMD_SHIFT
- 3);
1199 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PMD
- 1) << 3);
1200 GET_CONTEXT(p
, tmp
); /* get context reg */
1202 if (use_lwx_insns()) {
1203 UASM_i_LWX(p
, scratch
, scratch
, ptr
);
1205 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pmd offset */
1206 UASM_i_LW(p
, scratch
, 0, ptr
);
1209 /* Adjust the context during the load latency. */
1210 build_adjust_context(p
, tmp
);
1212 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1213 uasm_il_bbit1(p
, r
, scratch
, ilog2(_PAGE_HUGE
), label_tlb_huge_update
);
1215 * The in the LWX case we don't want to do the load in the
1216 * delay slot. It cannot issue in the same cycle and may be
1217 * speculative and unneeded.
1219 if (use_lwx_insns())
1221 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1224 /* build_update_entries */
1225 if (use_lwx_insns()) {
1228 UASM_i_LWX(p
, even
, scratch
, tmp
);
1229 UASM_i_ADDIU(p
, tmp
, tmp
, sizeof(pte_t
));
1230 UASM_i_LWX(p
, odd
, scratch
, tmp
);
1232 UASM_i_ADDU(p
, ptr
, scratch
, tmp
); /* add in offset */
1235 UASM_i_LW(p
, even
, 0, ptr
); /* get even pte */
1236 UASM_i_LW(p
, odd
, sizeof(pte_t
), ptr
); /* get odd pte */
1239 uasm_i_drotr(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1240 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1241 uasm_i_drotr(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1243 uasm_i_dsrl_safe(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1244 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1245 uasm_i_dsrl_safe(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1247 UASM_i_MTC0(p
, odd
, C0_ENTRYLO1
); /* load it */
1249 if (c0_scratch_reg
>= 0) {
1250 UASM_i_MFC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1251 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1252 uasm_l_leave(l
, *p
);
1253 rv
.restore_scratch
= 1;
1254 } else if (PAGE_SHIFT
== 14 || PAGE_SHIFT
== 13) {
1255 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1256 uasm_l_leave(l
, *p
);
1257 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1259 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1260 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1261 uasm_l_leave(l
, *p
);
1262 rv
.restore_scratch
= 1;
1265 uasm_i_eret(p
); /* return from trap */
1271 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1272 * because EXL == 0. If we wrap, we can also use the 32 instruction
1273 * slots before the XTLB refill exception handler which belong to the
1274 * unused TLB refill exception.
1276 #define MIPS64_REFILL_INSNS 32
1278 static void build_r4000_tlb_refill_handler(void)
1280 u32
*p
= tlb_handler
;
1281 struct uasm_label
*l
= labels
;
1282 struct uasm_reloc
*r
= relocs
;
1284 unsigned int final_len
;
1285 struct mips_huge_tlb_info htlb_info __maybe_unused
;
1286 enum vmalloc64_mode vmalloc_mode __maybe_unused
;
1288 memset(tlb_handler
, 0, sizeof(tlb_handler
));
1289 memset(labels
, 0, sizeof(labels
));
1290 memset(relocs
, 0, sizeof(relocs
));
1291 memset(final_handler
, 0, sizeof(final_handler
));
1293 if ((scratch_reg
>= 0 || scratchpad_available()) && use_bbit_insns()) {
1294 htlb_info
= build_fast_tlb_refill_handler(&p
, &l
, &r
, K0
, K1
,
1296 vmalloc_mode
= refill_scratch
;
1298 htlb_info
.huge_pte
= K0
;
1299 htlb_info
.restore_scratch
= 0;
1300 vmalloc_mode
= refill_noscratch
;
1302 * create the plain linear handler
1304 if (bcm1250_m3_war()) {
1305 unsigned int segbits
= 44;
1307 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1308 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
1309 uasm_i_xor(&p
, K0
, K0
, K1
);
1310 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
1311 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
1312 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
1313 uasm_i_or(&p
, K0
, K0
, K1
);
1314 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
1315 /* No need for uasm_i_nop */
1319 build_get_pmde64(&p
, &l
, &r
, K0
, K1
); /* get pmd in K1 */
1321 build_get_pgde32(&p
, K0
, K1
); /* get pgd in K1 */
1324 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1325 build_is_huge_pte(&p
, &r
, K0
, K1
, label_tlb_huge_update
);
1328 build_get_ptep(&p
, K0
, K1
);
1329 build_update_entries(&p
, K0
, K1
);
1330 build_tlb_write_entry(&p
, &l
, &r
, tlb_random
);
1331 uasm_l_leave(&l
, p
);
1332 uasm_i_eret(&p
); /* return from trap */
1334 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1335 uasm_l_tlb_huge_update(&l
, p
);
1336 build_huge_update_entries(&p
, htlb_info
.huge_pte
, K1
);
1337 build_huge_tlb_write_entry(&p
, &l
, &r
, K0
, tlb_random
,
1338 htlb_info
.restore_scratch
);
1342 build_get_pgd_vmalloc64(&p
, &l
, &r
, K0
, K1
, vmalloc_mode
);
1346 * Overflow check: For the 64bit handler, we need at least one
1347 * free instruction slot for the wrap-around branch. In worst
1348 * case, if the intended insertion point is a delay slot, we
1349 * need three, with the second nop'ed and the third being
1352 /* Loongson2 ebase is different than r4k, we have more space */
1353 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1354 if ((p
- tlb_handler
) > 64)
1355 panic("TLB refill handler space exceeded");
1357 if (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 1)
1358 || (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 3)
1359 && uasm_insn_has_bdelay(relocs
,
1360 tlb_handler
+ MIPS64_REFILL_INSNS
- 3)))
1361 panic("TLB refill handler space exceeded");
1365 * Now fold the handler in the TLB refill handler space.
1367 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1369 /* Simplest case, just copy the handler. */
1370 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1371 final_len
= p
- tlb_handler
;
1372 #else /* CONFIG_64BIT */
1373 f
= final_handler
+ MIPS64_REFILL_INSNS
;
1374 if ((p
- tlb_handler
) <= MIPS64_REFILL_INSNS
) {
1375 /* Just copy the handler. */
1376 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1377 final_len
= p
- tlb_handler
;
1379 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1380 const enum label_id ls
= label_tlb_huge_update
;
1382 const enum label_id ls
= label_vmalloc
;
1388 for (i
= 0; i
< ARRAY_SIZE(labels
) && labels
[i
].lab
!= ls
; i
++)
1390 BUG_ON(i
== ARRAY_SIZE(labels
));
1391 split
= labels
[i
].addr
;
1394 * See if we have overflown one way or the other.
1396 if (split
> tlb_handler
+ MIPS64_REFILL_INSNS
||
1397 split
< p
- MIPS64_REFILL_INSNS
)
1402 * Split two instructions before the end. One
1403 * for the branch and one for the instruction
1404 * in the delay slot.
1406 split
= tlb_handler
+ MIPS64_REFILL_INSNS
- 2;
1409 * If the branch would fall in a delay slot,
1410 * we must back up an additional instruction
1411 * so that it is no longer in a delay slot.
1413 if (uasm_insn_has_bdelay(relocs
, split
- 1))
1416 /* Copy first part of the handler. */
1417 uasm_copy_handler(relocs
, labels
, tlb_handler
, split
, f
);
1418 f
+= split
- tlb_handler
;
1421 /* Insert branch. */
1422 uasm_l_split(&l
, final_handler
);
1423 uasm_il_b(&f
, &r
, label_split
);
1424 if (uasm_insn_has_bdelay(relocs
, split
))
1427 uasm_copy_handler(relocs
, labels
,
1428 split
, split
+ 1, f
);
1429 uasm_move_labels(labels
, f
, f
+ 1, -1);
1435 /* Copy the rest of the handler. */
1436 uasm_copy_handler(relocs
, labels
, split
, p
, final_handler
);
1437 final_len
= (f
- (final_handler
+ MIPS64_REFILL_INSNS
)) +
1440 #endif /* CONFIG_64BIT */
1442 uasm_resolve_relocs(relocs
, labels
);
1443 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1446 memcpy((void *)ebase
, final_handler
, 0x100);
1448 dump_handler("r4000_tlb_refill", (u32
*)ebase
, 64);
1451 extern u32 handle_tlbl
[], handle_tlbl_end
[];
1452 extern u32 handle_tlbs
[], handle_tlbs_end
[];
1453 extern u32 handle_tlbm
[], handle_tlbm_end
[];
1455 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1456 extern u32 tlbmiss_handler_setup_pgd
[], tlbmiss_handler_setup_pgd_end
[];
1458 static void build_r4000_setup_pgd(void)
1462 u32
*p
= tlbmiss_handler_setup_pgd
;
1463 const int tlbmiss_handler_setup_pgd_size
=
1464 tlbmiss_handler_setup_pgd_end
- tlbmiss_handler_setup_pgd
;
1465 struct uasm_label
*l
= labels
;
1466 struct uasm_reloc
*r
= relocs
;
1468 memset(tlbmiss_handler_setup_pgd
, 0, tlbmiss_handler_setup_pgd_size
*
1469 sizeof(tlbmiss_handler_setup_pgd
[0]));
1470 memset(labels
, 0, sizeof(labels
));
1471 memset(relocs
, 0, sizeof(relocs
));
1473 pgd_reg
= allocate_kscratch();
1475 if (pgd_reg
== -1) {
1476 /* PGD << 11 in c0_Context */
1478 * If it is a ckseg0 address, convert to a physical
1479 * address. Shifting right by 29 and adding 4 will
1480 * result in zero for these addresses.
1483 UASM_i_SRA(&p
, a1
, a0
, 29);
1484 UASM_i_ADDIU(&p
, a1
, a1
, 4);
1485 uasm_il_bnez(&p
, &r
, a1
, label_tlbl_goaround1
);
1487 uasm_i_dinsm(&p
, a0
, 0, 29, 64 - 29);
1488 uasm_l_tlbl_goaround1(&l
, p
);
1489 UASM_i_SLL(&p
, a0
, a0
, 11);
1491 UASM_i_MTC0(&p
, a0
, C0_CONTEXT
);
1493 /* PGD in c0_KScratch */
1495 UASM_i_MTC0(&p
, a0
, c0_kscratch(), pgd_reg
);
1497 if (p
>= tlbmiss_handler_setup_pgd_end
)
1498 panic("tlbmiss_handler_setup_pgd space exceeded");
1500 uasm_resolve_relocs(relocs
, labels
);
1501 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1502 (unsigned int)(p
- tlbmiss_handler_setup_pgd
));
1504 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd
,
1505 tlbmiss_handler_setup_pgd_size
);
1510 iPTE_LW(u32
**p
, unsigned int pte
, unsigned int ptr
)
1513 # ifdef CONFIG_64BIT_PHYS_ADDR
1515 uasm_i_lld(p
, pte
, 0, ptr
);
1518 UASM_i_LL(p
, pte
, 0, ptr
);
1520 # ifdef CONFIG_64BIT_PHYS_ADDR
1522 uasm_i_ld(p
, pte
, 0, ptr
);
1525 UASM_i_LW(p
, pte
, 0, ptr
);
1530 iPTE_SW(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
, unsigned int ptr
,
1533 #ifdef CONFIG_64BIT_PHYS_ADDR
1534 unsigned int hwmode
= mode
& (_PAGE_VALID
| _PAGE_DIRTY
);
1537 uasm_i_ori(p
, pte
, pte
, mode
);
1539 # ifdef CONFIG_64BIT_PHYS_ADDR
1541 uasm_i_scd(p
, pte
, 0, ptr
);
1544 UASM_i_SC(p
, pte
, 0, ptr
);
1546 if (r10000_llsc_war())
1547 uasm_il_beqzl(p
, r
, pte
, label_smp_pgtable_change
);
1549 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1551 # ifdef CONFIG_64BIT_PHYS_ADDR
1552 if (!cpu_has_64bits
) {
1553 /* no uasm_i_nop needed */
1554 uasm_i_ll(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1555 uasm_i_ori(p
, pte
, pte
, hwmode
);
1556 uasm_i_sc(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1557 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1558 /* no uasm_i_nop needed */
1559 uasm_i_lw(p
, pte
, 0, ptr
);
1566 # ifdef CONFIG_64BIT_PHYS_ADDR
1568 uasm_i_sd(p
, pte
, 0, ptr
);
1571 UASM_i_SW(p
, pte
, 0, ptr
);
1573 # ifdef CONFIG_64BIT_PHYS_ADDR
1574 if (!cpu_has_64bits
) {
1575 uasm_i_lw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1576 uasm_i_ori(p
, pte
, pte
, hwmode
);
1577 uasm_i_sw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1578 uasm_i_lw(p
, pte
, 0, ptr
);
1585 * Check if PTE is present, if not then jump to LABEL. PTR points to
1586 * the page table where this PTE is located, PTE will be re-loaded
1587 * with it's original value.
1590 build_pte_present(u32
**p
, struct uasm_reloc
**r
,
1591 int pte
, int ptr
, int scratch
, enum label_id lid
)
1593 int t
= scratch
>= 0 ? scratch
: pte
;
1596 if (use_bbit_insns()) {
1597 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_PRESENT
), lid
);
1600 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
);
1601 uasm_il_beqz(p
, r
, t
, lid
);
1603 /* You lose the SMP race :-(*/
1604 iPTE_LW(p
, pte
, ptr
);
1607 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
| _PAGE_READ
);
1608 uasm_i_xori(p
, t
, t
, _PAGE_PRESENT
| _PAGE_READ
);
1609 uasm_il_bnez(p
, r
, t
, lid
);
1611 /* You lose the SMP race :-(*/
1612 iPTE_LW(p
, pte
, ptr
);
1616 /* Make PTE valid, store result in PTR. */
1618 build_make_valid(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1621 unsigned int mode
= _PAGE_VALID
| _PAGE_ACCESSED
;
1623 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1627 * Check if PTE can be written to, if not branch to LABEL. Regardless
1628 * restore PTE with value from PTR when done.
1631 build_pte_writable(u32
**p
, struct uasm_reloc
**r
,
1632 unsigned int pte
, unsigned int ptr
, int scratch
,
1635 int t
= scratch
>= 0 ? scratch
: pte
;
1637 uasm_i_andi(p
, t
, pte
, _PAGE_PRESENT
| _PAGE_WRITE
);
1638 uasm_i_xori(p
, t
, t
, _PAGE_PRESENT
| _PAGE_WRITE
);
1639 uasm_il_bnez(p
, r
, t
, lid
);
1641 /* You lose the SMP race :-(*/
1642 iPTE_LW(p
, pte
, ptr
);
1647 /* Make PTE writable, update software status bits as well, then store
1651 build_make_write(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1654 unsigned int mode
= (_PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
1657 iPTE_SW(p
, r
, pte
, ptr
, mode
);
1661 * Check if PTE can be modified, if not branch to LABEL. Regardless
1662 * restore PTE with value from PTR when done.
1665 build_pte_modifiable(u32
**p
, struct uasm_reloc
**r
,
1666 unsigned int pte
, unsigned int ptr
, int scratch
,
1669 if (use_bbit_insns()) {
1670 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_WRITE
), lid
);
1673 int t
= scratch
>= 0 ? scratch
: pte
;
1674 uasm_i_andi(p
, t
, pte
, _PAGE_WRITE
);
1675 uasm_il_beqz(p
, r
, t
, lid
);
1677 /* You lose the SMP race :-(*/
1678 iPTE_LW(p
, pte
, ptr
);
1682 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1686 * R3000 style TLB load/store/modify handlers.
1690 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1694 build_r3000_pte_reload_tlbwi(u32
**p
, unsigned int pte
, unsigned int tmp
)
1696 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1697 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* cp0 delay */
1700 uasm_i_rfe(p
); /* branch delay */
1704 * This places the pte into ENTRYLO0 and writes it with tlbwi
1705 * or tlbwr as appropriate. This is because the index register
1706 * may have the probe fail bit set as a result of a trap on a
1707 * kseg2 access, i.e. without refill. Then it returns.
1710 build_r3000_tlb_reload_write(u32
**p
, struct uasm_label
**l
,
1711 struct uasm_reloc
**r
, unsigned int pte
,
1714 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1715 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1716 uasm_il_bltz(p
, r
, tmp
, label_r3000_write_probe_fail
); /* cp0 delay */
1717 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* branch delay */
1718 uasm_i_tlbwi(p
); /* cp0 delay */
1720 uasm_i_rfe(p
); /* branch delay */
1721 uasm_l_r3000_write_probe_fail(l
, *p
);
1722 uasm_i_tlbwr(p
); /* cp0 delay */
1724 uasm_i_rfe(p
); /* branch delay */
1728 build_r3000_tlbchange_handler_head(u32
**p
, unsigned int pte
,
1731 long pgdc
= (long)pgd_current
;
1733 uasm_i_mfc0(p
, pte
, C0_BADVADDR
);
1734 uasm_i_lui(p
, ptr
, uasm_rel_hi(pgdc
)); /* cp0 delay */
1735 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
1736 uasm_i_srl(p
, pte
, pte
, 22); /* load delay */
1737 uasm_i_sll(p
, pte
, pte
, 2);
1738 uasm_i_addu(p
, ptr
, ptr
, pte
);
1739 uasm_i_mfc0(p
, pte
, C0_CONTEXT
);
1740 uasm_i_lw(p
, ptr
, 0, ptr
); /* cp0 delay */
1741 uasm_i_andi(p
, pte
, pte
, 0xffc); /* load delay */
1742 uasm_i_addu(p
, ptr
, ptr
, pte
);
1743 uasm_i_lw(p
, pte
, 0, ptr
);
1744 uasm_i_tlbp(p
); /* load delay */
1747 static void build_r3000_tlb_load_handler(void)
1749 u32
*p
= handle_tlbl
;
1750 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
1751 struct uasm_label
*l
= labels
;
1752 struct uasm_reloc
*r
= relocs
;
1754 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
1755 memset(labels
, 0, sizeof(labels
));
1756 memset(relocs
, 0, sizeof(relocs
));
1758 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1759 build_pte_present(&p
, &r
, K0
, K1
, -1, label_nopage_tlbl
);
1760 uasm_i_nop(&p
); /* load delay */
1761 build_make_valid(&p
, &r
, K0
, K1
);
1762 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1764 uasm_l_nopage_tlbl(&l
, p
);
1765 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
1768 if (p
>= handle_tlbl_end
)
1769 panic("TLB load handler fastpath space exceeded");
1771 uasm_resolve_relocs(relocs
, labels
);
1772 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1773 (unsigned int)(p
- handle_tlbl
));
1775 dump_handler("r3000_tlb_load", handle_tlbl
, handle_tlbl_size
);
1778 static void build_r3000_tlb_store_handler(void)
1780 u32
*p
= handle_tlbs
;
1781 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
1782 struct uasm_label
*l
= labels
;
1783 struct uasm_reloc
*r
= relocs
;
1785 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
1786 memset(labels
, 0, sizeof(labels
));
1787 memset(relocs
, 0, sizeof(relocs
));
1789 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1790 build_pte_writable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbs
);
1791 uasm_i_nop(&p
); /* load delay */
1792 build_make_write(&p
, &r
, K0
, K1
);
1793 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1795 uasm_l_nopage_tlbs(&l
, p
);
1796 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1799 if (p
>= handle_tlbs_end
)
1800 panic("TLB store handler fastpath space exceeded");
1802 uasm_resolve_relocs(relocs
, labels
);
1803 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1804 (unsigned int)(p
- handle_tlbs
));
1806 dump_handler("r3000_tlb_store", handle_tlbs
, handle_tlbs_size
);
1809 static void build_r3000_tlb_modify_handler(void)
1811 u32
*p
= handle_tlbm
;
1812 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
1813 struct uasm_label
*l
= labels
;
1814 struct uasm_reloc
*r
= relocs
;
1816 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
1817 memset(labels
, 0, sizeof(labels
));
1818 memset(relocs
, 0, sizeof(relocs
));
1820 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1821 build_pte_modifiable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbm
);
1822 uasm_i_nop(&p
); /* load delay */
1823 build_make_write(&p
, &r
, K0
, K1
);
1824 build_r3000_pte_reload_tlbwi(&p
, K0
, K1
);
1826 uasm_l_nopage_tlbm(&l
, p
);
1827 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1830 if (p
>= handle_tlbm_end
)
1831 panic("TLB modify handler fastpath space exceeded");
1833 uasm_resolve_relocs(relocs
, labels
);
1834 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1835 (unsigned int)(p
- handle_tlbm
));
1837 dump_handler("r3000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
1839 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1842 * R4000 style TLB load/store/modify handlers.
1844 static struct work_registers
1845 build_r4000_tlbchange_handler_head(u32
**p
, struct uasm_label
**l
,
1846 struct uasm_reloc
**r
)
1848 struct work_registers wr
= build_get_work_registers(p
);
1851 build_get_pmde64(p
, l
, r
, wr
.r1
, wr
.r2
); /* get pmd in ptr */
1853 build_get_pgde32(p
, wr
.r1
, wr
.r2
); /* get pgd in ptr */
1856 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1858 * For huge tlb entries, pmd doesn't contain an address but
1859 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1860 * see if we need to jump to huge tlb processing.
1862 build_is_huge_pte(p
, r
, wr
.r1
, wr
.r2
, label_tlb_huge_update
);
1865 UASM_i_MFC0(p
, wr
.r1
, C0_BADVADDR
);
1866 UASM_i_LW(p
, wr
.r2
, 0, wr
.r2
);
1867 UASM_i_SRL(p
, wr
.r1
, wr
.r1
, PAGE_SHIFT
+ PTE_ORDER
- PTE_T_LOG2
);
1868 uasm_i_andi(p
, wr
.r1
, wr
.r1
, (PTRS_PER_PTE
- 1) << PTE_T_LOG2
);
1869 UASM_i_ADDU(p
, wr
.r2
, wr
.r2
, wr
.r1
);
1872 uasm_l_smp_pgtable_change(l
, *p
);
1874 iPTE_LW(p
, wr
.r1
, wr
.r2
); /* get even pte */
1875 if (!m4kc_tlbp_war())
1876 build_tlb_probe_entry(p
);
1881 build_r4000_tlbchange_handler_tail(u32
**p
, struct uasm_label
**l
,
1882 struct uasm_reloc
**r
, unsigned int tmp
,
1885 uasm_i_ori(p
, ptr
, ptr
, sizeof(pte_t
));
1886 uasm_i_xori(p
, ptr
, ptr
, sizeof(pte_t
));
1887 build_update_entries(p
, tmp
, ptr
);
1888 build_tlb_write_entry(p
, l
, r
, tlb_indexed
);
1889 uasm_l_leave(l
, *p
);
1890 build_restore_work_registers(p
);
1891 uasm_i_eret(p
); /* return from trap */
1894 build_get_pgd_vmalloc64(p
, l
, r
, tmp
, ptr
, not_refill
);
1898 static void build_r4000_tlb_load_handler(void)
1900 u32
*p
= handle_tlbl
;
1901 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
1902 struct uasm_label
*l
= labels
;
1903 struct uasm_reloc
*r
= relocs
;
1904 struct work_registers wr
;
1906 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
1907 memset(labels
, 0, sizeof(labels
));
1908 memset(relocs
, 0, sizeof(relocs
));
1910 if (bcm1250_m3_war()) {
1911 unsigned int segbits
= 44;
1913 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1914 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
1915 uasm_i_xor(&p
, K0
, K0
, K1
);
1916 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
1917 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
1918 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
1919 uasm_i_or(&p
, K0
, K0
, K1
);
1920 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
1921 /* No need for uasm_i_nop */
1924 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
1925 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
1926 if (m4kc_tlbp_war())
1927 build_tlb_probe_entry(&p
);
1931 * If the page is not _PAGE_VALID, RI or XI could not
1932 * have triggered it. Skip the expensive test..
1934 if (use_bbit_insns()) {
1935 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
1936 label_tlbl_goaround1
);
1938 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
1939 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround1
);
1945 switch (current_cpu_type()) {
1947 if (cpu_has_mips_r2
) {
1950 case CPU_CAVIUM_OCTEON
:
1951 case CPU_CAVIUM_OCTEON_PLUS
:
1952 case CPU_CAVIUM_OCTEON2
:
1957 /* Examine entrylo 0 or 1 based on ptr. */
1958 if (use_bbit_insns()) {
1959 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
1961 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
1962 uasm_i_beqz(&p
, wr
.r3
, 8);
1964 /* load it in the delay slot*/
1965 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
1966 /* load it if ptr is odd */
1967 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
1969 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1970 * XI must have triggered it.
1972 if (use_bbit_insns()) {
1973 uasm_il_bbit1(&p
, &r
, wr
.r3
, 1, label_nopage_tlbl
);
1975 uasm_l_tlbl_goaround1(&l
, p
);
1977 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
1978 uasm_il_bnez(&p
, &r
, wr
.r3
, label_nopage_tlbl
);
1981 uasm_l_tlbl_goaround1(&l
, p
);
1983 build_make_valid(&p
, &r
, wr
.r1
, wr
.r2
);
1984 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
1986 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1988 * This is the entry point when build_r4000_tlbchange_handler_head
1989 * spots a huge page.
1991 uasm_l_tlb_huge_update(&l
, p
);
1992 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
1993 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
1994 build_tlb_probe_entry(&p
);
1998 * If the page is not _PAGE_VALID, RI or XI could not
1999 * have triggered it. Skip the expensive test..
2001 if (use_bbit_insns()) {
2002 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
2003 label_tlbl_goaround2
);
2005 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
2006 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2012 switch (current_cpu_type()) {
2014 if (cpu_has_mips_r2
) {
2017 case CPU_CAVIUM_OCTEON
:
2018 case CPU_CAVIUM_OCTEON_PLUS
:
2019 case CPU_CAVIUM_OCTEON2
:
2024 /* Examine entrylo 0 or 1 based on ptr. */
2025 if (use_bbit_insns()) {
2026 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
2028 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
2029 uasm_i_beqz(&p
, wr
.r3
, 8);
2031 /* load it in the delay slot*/
2032 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
2033 /* load it if ptr is odd */
2034 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
2036 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2037 * XI must have triggered it.
2039 if (use_bbit_insns()) {
2040 uasm_il_bbit0(&p
, &r
, wr
.r3
, 1, label_tlbl_goaround2
);
2042 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
2043 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2045 if (PM_DEFAULT_MASK
== 0)
2048 * We clobbered C0_PAGEMASK, restore it. On the other branch
2049 * it is restored in build_huge_tlb_write_entry.
2051 build_restore_pagemask(&p
, &r
, wr
.r3
, label_nopage_tlbl
, 0);
2053 uasm_l_tlbl_goaround2(&l
, p
);
2055 uasm_i_ori(&p
, wr
.r1
, wr
.r1
, (_PAGE_ACCESSED
| _PAGE_VALID
));
2056 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2059 uasm_l_nopage_tlbl(&l
, p
);
2060 build_restore_work_registers(&p
);
2061 #ifdef CONFIG_CPU_MICROMIPS
2062 if ((unsigned long)tlb_do_page_fault_0
& 1) {
2063 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_0
));
2064 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_0
));
2068 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
2071 if (p
>= handle_tlbl_end
)
2072 panic("TLB load handler fastpath space exceeded");
2074 uasm_resolve_relocs(relocs
, labels
);
2075 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2076 (unsigned int)(p
- handle_tlbl
));
2078 dump_handler("r4000_tlb_load", handle_tlbl
, handle_tlbl_size
);
2081 static void build_r4000_tlb_store_handler(void)
2083 u32
*p
= handle_tlbs
;
2084 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
2085 struct uasm_label
*l
= labels
;
2086 struct uasm_reloc
*r
= relocs
;
2087 struct work_registers wr
;
2089 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
2090 memset(labels
, 0, sizeof(labels
));
2091 memset(relocs
, 0, sizeof(relocs
));
2093 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2094 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2095 if (m4kc_tlbp_war())
2096 build_tlb_probe_entry(&p
);
2097 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
);
2098 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2100 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2102 * This is the entry point when
2103 * build_r4000_tlbchange_handler_head spots a huge page.
2105 uasm_l_tlb_huge_update(&l
, p
);
2106 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2107 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2108 build_tlb_probe_entry(&p
);
2109 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2110 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2111 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2114 uasm_l_nopage_tlbs(&l
, p
);
2115 build_restore_work_registers(&p
);
2116 #ifdef CONFIG_CPU_MICROMIPS
2117 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2118 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2119 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2123 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2126 if (p
>= handle_tlbs_end
)
2127 panic("TLB store handler fastpath space exceeded");
2129 uasm_resolve_relocs(relocs
, labels
);
2130 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2131 (unsigned int)(p
- handle_tlbs
));
2133 dump_handler("r4000_tlb_store", handle_tlbs
, handle_tlbs_size
);
2136 static void build_r4000_tlb_modify_handler(void)
2138 u32
*p
= handle_tlbm
;
2139 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
2140 struct uasm_label
*l
= labels
;
2141 struct uasm_reloc
*r
= relocs
;
2142 struct work_registers wr
;
2144 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
2145 memset(labels
, 0, sizeof(labels
));
2146 memset(relocs
, 0, sizeof(relocs
));
2148 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2149 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2150 if (m4kc_tlbp_war())
2151 build_tlb_probe_entry(&p
);
2152 /* Present and writable bits set, set accessed and dirty bits. */
2153 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
);
2154 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2156 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2158 * This is the entry point when
2159 * build_r4000_tlbchange_handler_head spots a huge page.
2161 uasm_l_tlb_huge_update(&l
, p
);
2162 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2163 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2164 build_tlb_probe_entry(&p
);
2165 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2166 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2167 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
);
2170 uasm_l_nopage_tlbm(&l
, p
);
2171 build_restore_work_registers(&p
);
2172 #ifdef CONFIG_CPU_MICROMIPS
2173 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2174 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2175 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2179 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2182 if (p
>= handle_tlbm_end
)
2183 panic("TLB modify handler fastpath space exceeded");
2185 uasm_resolve_relocs(relocs
, labels
);
2186 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2187 (unsigned int)(p
- handle_tlbm
));
2189 dump_handler("r4000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
2192 static void flush_tlb_handlers(void)
2194 local_flush_icache_range((unsigned long)handle_tlbl
,
2195 (unsigned long)handle_tlbl_end
);
2196 local_flush_icache_range((unsigned long)handle_tlbs
,
2197 (unsigned long)handle_tlbs_end
);
2198 local_flush_icache_range((unsigned long)handle_tlbm
,
2199 (unsigned long)handle_tlbm_end
);
2200 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2201 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd
,
2202 (unsigned long)tlbmiss_handler_setup_pgd_end
);
2206 void build_tlb_refill_handler(void)
2209 * The refill handler is generated per-CPU, multi-node systems
2210 * may have local storage for it. The other handlers are only
2213 static int run_once
= 0;
2215 output_pgtable_bits_defines();
2218 check_for_high_segbits
= current_cpu_data
.vmbits
> (PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
2221 switch (current_cpu_type()) {
2229 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2230 if (cpu_has_local_ebase
)
2231 build_r3000_tlb_refill_handler();
2233 if (!cpu_has_local_ebase
)
2234 build_r3000_tlb_refill_handler();
2235 build_r3000_tlb_load_handler();
2236 build_r3000_tlb_store_handler();
2237 build_r3000_tlb_modify_handler();
2238 flush_tlb_handlers();
2242 panic("No R3000 TLB refill handler");
2248 panic("No R6000 TLB refill handler yet");
2252 panic("No R8000 TLB refill handler yet");
2257 scratch_reg
= allocate_kscratch();
2258 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2259 build_r4000_setup_pgd();
2261 build_r4000_tlb_load_handler();
2262 build_r4000_tlb_store_handler();
2263 build_r4000_tlb_modify_handler();
2264 if (!cpu_has_local_ebase
)
2265 build_r4000_tlb_refill_handler();
2266 flush_tlb_handlers();
2269 if (cpu_has_local_ebase
)
2270 build_r4000_tlb_refill_handler();