2 * B4420 Silicon/SoC Device Tree Source (post include)
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38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
44 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 fsl,iommu-parent = <&pamu0>;
52 #interrupt-cells = <1>;
57 interrupts = <20 2 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
72 compatible = "fsl,dcsr", "simple-bus";
75 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
76 interrupts = <52 2 0 0
84 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
85 reg = <0x1000 0x1000 0x1002000 0x10000>;
88 compatible = "fsl,dcsr-nxc";
89 reg = <0x2000 0x1000>;
92 compatible = "fsl,dcsr-corenet";
93 reg = <0x8000 0x1000 0x1A000 0x1000>;
96 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
97 reg = <0x9000 0x1000>;
100 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
101 reg = <0x11000 0x1000>;
104 compatible = "fsl,dcsr-ddr";
105 dev-handle = <&ddr1>;
106 reg = <0x12000 0x1000>;
109 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
110 reg = <0x18000 0x1000>;
113 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
114 reg = <0x22000 0x1000>;
117 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
118 reg = <0x30000 0x1000 0x1022000 0x10000>;
121 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
122 reg = <0x31000 0x1000 0x1042000 0x10000>;
124 dcsr-cpu-sb-proxy@100000 {
125 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
126 cpu-handle = <&cpu0>;
127 reg = <0x100000 0x1000 0x101000 0x1000>;
132 #address-cells = <1>;
135 compatible = "simple-bus";
138 compatible = "fsl,soc-sram-error";
139 interrupts = <16 2 1 2>;
143 compatible = "fsl,corenet-law";
148 ddr1: memory-controller@8000 {
149 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
150 reg = <0x8000 0x1000>;
151 interrupts = <16 2 1 8>;
154 cpc: l3-cache-controller@10000 {
155 compatible = "fsl,b4-l3-cache-controller", "cache";
156 reg = <0x10000 0x1000>;
157 interrupts = <16 2 1 4>;
161 compatible = "fsl,b4-corenet-cf";
162 reg = <0x18000 0x1000>;
163 interrupts = <16 2 1 0>;
164 fsl,ccf-num-csdids = <32>;
165 fsl,ccf-num-snoopids = <32>;
169 compatible = "fsl,pamu-v1.0", "fsl,pamu";
170 reg = <0x20000 0x4000>;
171 #address-cells = <1>;
178 /* PCIe, DMA, SRIO */
181 fsl,primary-cache-geometry = <8 1>;
182 fsl,secondary-cache-geometry = <32 2>;
187 reg = <0x1000 0x1000>;
188 fsl,primary-cache-geometry = <32 1>;
189 fsl,secondary-cache-geometry = <32 2>;
194 reg = <0x2000 0x1000>;
195 fsl,primary-cache-geometry = <32 1>;
196 fsl,secondary-cache-geometry = <32 2>;
201 reg = <0x3000 0x1000>;
202 fsl,primary-cache-geometry = <32 1>;
203 fsl,secondary-cache-geometry = <32 2>;
207 /include/ "qoriq-mpic4.3.dtsi"
209 guts: global-utilities@e0000 {
210 compatible = "fsl,b4-device-config";
211 reg = <0xe0000 0xe00>;
213 fsl,liodn-bits = <12>;
216 clockgen: global-utilities@e1000 {
217 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
218 reg = <0xe1000 0x1000>;
221 rcpm: global-utilities@e2000 {
222 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
223 reg = <0xe2000 0x1000>;
226 /include/ "qoriq-dma-0.dtsi"
228 fsl,iommu-parent = <&pamu0>;
229 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
232 /include/ "qoriq-dma-1.dtsi"
234 fsl,iommu-parent = <&pamu0>;
235 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
238 /include/ "qonverge-usb2-dr-0.dtsi"
240 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
241 fsl,iommu-parent = <&pamu1>;
242 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
245 /include/ "qoriq-espi-0.dtsi"
247 fsl,espi-num-chipselects = <4>;
250 /include/ "qoriq-esdhc-0.dtsi"
253 fsl,iommu-parent = <&pamu1>;
254 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
257 /include/ "qoriq-i2c-0.dtsi"
258 /include/ "qoriq-i2c-1.dtsi"
259 /include/ "qoriq-duart-0.dtsi"
260 /include/ "qoriq-duart-1.dtsi"
261 /include/ "qoriq-sec5.3-0.dtsi"
263 L2: l2-cache-controller@c20000 {
264 compatible = "fsl,b4-l2-cache-controller";
265 reg = <0xc20000 0x1000>;
266 next-level-cache = <&cpc>;