2 * MPC8536 Silicon/SoC Device Tree Source (post include)
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38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
44 compatible = "fsl,mpc8540-pci";
46 interrupts = <24 0x2 0 0>;
48 #interrupt-cells = <1>;
53 /* controller at 0x9000 */
55 compatible = "fsl,mpc8548-pcie";
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
65 #interrupt-cells = <1>;
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
82 /* controller at 0xa000 */
84 compatible = "fsl,mpc8548-pcie";
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
94 #interrupt-cells = <1>;
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
110 /* controller at 0xb000 */
112 compatible = "fsl,mpc8548-pcie";
115 #address-cells = <3>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
122 #interrupt-cells = <1>;
124 #address-cells = <3>;
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
138 #address-cells = <1>;
141 compatible = "fsl,mpc8536-immr", "simple-bus";
142 bus-frequency = <0>; // Filled out by uboot.
145 compatible = "fsl,ecm-law";
151 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2 0 0>;
156 memory-controller@2000 {
157 compatible = "fsl,mpc8536-memory-controller";
158 reg = <0x2000 0x1000>;
159 interrupts = <18 2 0 0>;
162 /include/ "pq3-i2c-0.dtsi"
163 /include/ "pq3-i2c-1.dtsi"
164 /include/ "pq3-duart-0.dtsi"
166 /include/ "pq3-espi-0.dtsi"
168 fsl,espi-num-chipselects = <4>;
171 /include/ "pq3-gpio-0.dtsi"
173 /* mark compat w/8572 to get some erratum treatment */
174 gpio-controller@f000 {
175 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
179 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
180 reg = <0x18000 0x1000>;
182 interrupts = <74 0x2 0 0>;
186 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
187 reg = <0x19000 0x1000>;
189 interrupts = <41 0x2 0 0>;
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8536-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x80000>; // L2, 512K
197 interrupts = <16 2 0 0>;
200 /include/ "pq3-dma-0.dtsi"
201 /include/ "pq3-etsec1-0.dtsi"
202 /include/ "pq3-etsec1-timer-0.dtsi"
205 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
209 interrupts = <28 0x2 0 0>;
213 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>;
215 #address-cells = <1>;
217 interrupts = <46 0x2 0 0>;
221 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
224 /include/ "pq3-etsec1-2.dtsi"
231 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
232 reg = <0x2b000 0x1000>;
233 #address-cells = <1>;
235 interrupts = <60 0x2 0 0>;
238 /include/ "pq3-esdhc-0.dtsi"
240 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
243 /include/ "pq3-sec3.0-0.dtsi"
244 /include/ "pq3-mpic.dtsi"
245 /include/ "pq3-mpic-timer-B.dtsi"
247 global-utilities@e0000 {
248 compatible = "fsl,mpc8536-guts";
249 reg = <0xe0000 0x1000>;