2 * T4240 Silicon/SoC Device Tree Source (pre include)
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37 /include/ "e6500_power_isa.dtsi"
40 compatible = "fsl,T4240";
43 interrupt-parent = <&mpic>;
67 cpu0: PowerPC,e6500@0 {
70 next-level-cache = <&L2_1>;
72 cpu1: PowerPC,e6500@2 {
75 next-level-cache = <&L2_1>;
77 cpu2: PowerPC,e6500@4 {
80 next-level-cache = <&L2_1>;
82 cpu3: PowerPC,e6500@6 {
85 next-level-cache = <&L2_1>;
87 cpu4: PowerPC,e6500@8 {
90 next-level-cache = <&L2_2>;
92 cpu5: PowerPC,e6500@10 {
95 next-level-cache = <&L2_2>;
97 cpu6: PowerPC,e6500@12 {
100 next-level-cache = <&L2_2>;
102 cpu7: PowerPC,e6500@14 {
105 next-level-cache = <&L2_2>;
107 cpu8: PowerPC,e6500@16 {
110 next-level-cache = <&L2_3>;
112 cpu9: PowerPC,e6500@18 {
115 next-level-cache = <&L2_3>;
117 cpu10: PowerPC,e6500@20 {
120 next-level-cache = <&L2_3>;
122 cpu11: PowerPC,e6500@22 {
125 next-level-cache = <&L2_3>;