| blob | 2d31863accf5331112d575d6e44bc0152c6e47ab |
1 /*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 /include/ "fsl/e500v2_power_isa.dtsi"
16 / {
17 model = "MPC8540ADS";
18 compatible = "MPC8540ADS", "MPC85xxADS";
19 #address-cells = <1>;
20 #size-cells = <1>;
22 aliases {
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 };
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
35 PowerPC,8540@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // 166 MHz
44 clock-frequency = <0>; // 825 MHz, from uboot
45 next-level-cache = <&L2>;
46 };
47 };
49 memory {
50 device_type = "memory";
51 reg = <0x0 0x8000000>; // 128M at 0x0
52 };
54 soc8540@e0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 device_type = "soc";
58 compatible = "simple-bus";
59 ranges = <0x0 0xe0000000 0x100000>;
60 bus-frequency = <0>;
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <8>;
66 };
68 ecm@1000 {
69 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
75 memory-controller@2000 {
76 compatible = "fsl,mpc8540-memory-controller";
77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>;
80 };
82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,mpc8540-l2-cache-controller";
84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
87 interrupt-parent = <&mpic>;
88 interrupts = <16 2>;
89 };
91 i2c@3000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <0>;
95 compatible = "fsl-i2c";
96 reg = <0x3000 0x100>;
97 interrupts = <43 2>;
98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
102 dma@21300 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
106 reg = <0x21300 0x4>;
107 ranges = <0x0 0x21100 0x200>;
108 cell-index = <0>;
109 dma-channel@0 {
110 compatible = "fsl,mpc8540-dma-channel",
111 "fsl,eloplus-dma-channel";
112 reg = <0x0 0x80>;
113 cell-index = <0>;
114 interrupt-parent = <&mpic>;
115 interrupts = <20 2>;
116 };
117 dma-channel@80 {
118 compatible = "fsl,mpc8540-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x80 0x80>;
121 cell-index = <1>;
122 interrupt-parent = <&mpic>;
123 interrupts = <21 2>;
124 };
125 dma-channel@100 {
126 compatible = "fsl,mpc8540-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x100 0x80>;
129 cell-index = <2>;
130 interrupt-parent = <&mpic>;
131 interrupts = <22 2>;
132 };
133 dma-channel@180 {
134 compatible = "fsl,mpc8540-dma-channel",
135 "fsl,eloplus-dma-channel";
136 reg = <0x180 0x80>;
137 cell-index = <3>;
138 interrupt-parent = <&mpic>;
139 interrupts = <23 2>;
140 };
141 };
143 enet0: ethernet@24000 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 cell-index = <0>;
147 device_type = "network";
148 model = "TSEC";
149 compatible = "gianfar";
150 reg = <0x24000 0x1000>;
151 ranges = <0x0 0x24000 0x1000>;
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <29 2 30 2 34 2>;
154 interrupt-parent = <&mpic>;
155 tbi-handle = <&tbi0>;
156 phy-handle = <&phy0>;
158 mdio@520 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,gianfar-mdio";
162 reg = <0x520 0x20>;
164 phy0: ethernet-phy@0 {
165 interrupt-parent = <&mpic>;
166 interrupts = <5 1>;
167 reg = <0x0>;
168 device_type = "ethernet-phy";
169 };
170 phy1: ethernet-phy@1 {
171 interrupt-parent = <&mpic>;
172 interrupts = <5 1>;
173 reg = <0x1>;
174 device_type = "ethernet-phy";
175 };
176 phy3: ethernet-phy@3 {
177 interrupt-parent = <&mpic>;
178 interrupts = <7 1>;
179 reg = <0x3>;
180 device_type = "ethernet-phy";
181 };
182 tbi0: tbi-phy@11 {
183 reg = <0x11>;
184 device_type = "tbi-phy";
185 };
186 };
187 };
189 enet1: ethernet@25000 {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <1>;
193 device_type = "network";
194 model = "TSEC";
195 compatible = "gianfar";
196 reg = <0x25000 0x1000>;
197 ranges = <0x0 0x25000 0x1000>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <35 2 36 2 40 2>;
200 interrupt-parent = <&mpic>;
201 tbi-handle = <&tbi1>;
202 phy-handle = <&phy1>;
204 mdio@520 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,gianfar-tbi";
208 reg = <0x520 0x20>;
210 tbi1: tbi-phy@11 {
211 reg = <0x11>;
212 device_type = "tbi-phy";
213 };
214 };
215 };
217 enet2: ethernet@26000 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 cell-index = <2>;
221 device_type = "network";
222 model = "FEC";
223 compatible = "gianfar";
224 reg = <0x26000 0x1000>;
225 ranges = <0x0 0x26000 0x1000>;
226 local-mac-address = [ 00 00 00 00 00 00 ];
227 interrupts = <41 2>;
228 interrupt-parent = <&mpic>;
229 tbi-handle = <&tbi2>;
230 phy-handle = <&phy3>;
232 mdio@520 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,gianfar-tbi";
236 reg = <0x520 0x20>;
238 tbi2: tbi-phy@11 {
239 reg = <0x11>;
240 device_type = "tbi-phy";
241 };
242 };
243 };
245 serial0: serial@4500 {
246 cell-index = <0>;
247 device_type = "serial";
248 compatible = "fsl,ns16550", "ns16550";
249 reg = <0x4500 0x100>; // reg base, size
250 clock-frequency = <0>; // should we fill in in uboot?
251 interrupts = <42 2>;
252 interrupt-parent = <&mpic>;
253 };
255 serial1: serial@4600 {
256 cell-index = <1>;
257 device_type = "serial";
258 compatible = "fsl,ns16550", "ns16550";
259 reg = <0x4600 0x100>; // reg base, size
260 clock-frequency = <0>; // should we fill in in uboot?
261 interrupts = <42 2>;
262 interrupt-parent = <&mpic>;
263 };
264 mpic: pic@40000 {
265 interrupt-controller;
266 #address-cells = <0>;
267 #interrupt-cells = <2>;
268 reg = <0x40000 0x40000>;
269 compatible = "chrp,open-pic";
270 device_type = "open-pic";
271 };
272 };
274 pci0: pci@e0008000 {
275 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
276 interrupt-map = <
278 /* IDSEL 0x02 */
279 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
280 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
281 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
282 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
284 /* IDSEL 0x03 */
285 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
286 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
287 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
288 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
290 /* IDSEL 0x04 */
291 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
292 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
293 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
294 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
296 /* IDSEL 0x05 */
297 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
298 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
299 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
300 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
302 /* IDSEL 0x0c */
303 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
304 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
305 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
306 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
308 /* IDSEL 0x0d */
309 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
310 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
311 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
312 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
314 /* IDSEL 0x0e */
315 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
316 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
317 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
318 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
320 /* IDSEL 0x0f */
321 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
322 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
323 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
324 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
326 /* IDSEL 0x12 */
327 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
328 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
329 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
330 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
332 /* IDSEL 0x13 */
333 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
334 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
335 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
336 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
338 /* IDSEL 0x14 */
339 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
340 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
341 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
342 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
344 /* IDSEL 0x15 */
345 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
346 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
347 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
348 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
349 interrupt-parent = <&mpic>;
350 interrupts = <24 2>;
351 bus-range = <0 0>;
352 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
353 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
354 clock-frequency = <66666666>;
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0xe0008000 0x1000>;
359 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
360 device_type = "pci";
361 };
362 };