arch/powerpc/boot/dts/p4080ds.dts

   1 /*
   2  * P4080DS Device Tree Source
   3  *
   4  * Copyright 2009-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "fsl/p4080si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,P4080DS";
  39         compatible = "fsl,P4080DS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         memory {
  45                 device_type = "memory";
  46         };
  47
  48         dcsr: dcsr@f00000000 {
  49                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  50         };
  51
  52         soc: soc@ffe000000 {
  53                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  54                 reg = <0xf 0xfe000000 0 0x00001000>;
  55
  56                 spi@110000 {
  57                         flash@0 {
  58                                 #address-cells = <1>;
  59                                 #size-cells = <1>;
  60                                 compatible = "spansion,s25sl12801";
  61                                 reg = <0>;
  62                                 spi-max-frequency = <40000000>; /* input clock */
  63                                 partition@u-boot {
  64                                         label = "u-boot";
  65                                         reg = <0x00000000 0x00100000>;
  66                                         read-only;
  67                                 };
  68                                 partition@kernel {
  69                                         label = "kernel";
  70                                         reg = <0x00100000 0x00500000>;
  71                                         read-only;
  72                                 };
  73                                 partition@dtb {
  74                                         label = "dtb";
  75                                         reg = <0x00600000 0x00100000>;
  76                                         read-only;
  77                                 };
  78                                 partition@fs {
  79                                         label = "file system";
  80                                         reg = <0x00700000 0x00900000>;
  81                                 };
  82                         };
  83                 };
  84
  85                 i2c@118100 {
  86                         eeprom@51 {
  87                                 compatible = "at24,24c256";
  88                                 reg = <0x51>;
  89                         };
  90                         eeprom@52 {
  91                                 compatible = "at24,24c256";
  92                                 reg = <0x52>;
  93                         };
  94                         rtc@68 {
  95                                 compatible = "dallas,ds3232";
  96                                 reg = <0x68>;
  97                                 interrupts = <0x1 0x1 0 0>;
  98                         };
  99                         adt7461@4c {
 100                                 compatible = "adi,adt7461";
 101                                 reg = <0x4c>;
 102                         };
 103                 };
 104
 105                 usb0: usb@210000 {
 106                         phy_type = "ulpi";
 107                 };
 108
 109                 usb1: usb@211000 {
 110                         dr_mode = "host";
 111                         phy_type = "ulpi";
 112                 };
 113         };
 114
 115         rio: rapidio@ffe0c0000 {
 116                 reg = <0xf 0xfe0c0000 0 0x11000>;
 117
 118                 port1 {
 119                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 120                 };
 121                 port2 {
 122                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 123                 };
 124         };
 125
 126         lbc: localbus@ffe124000 {
 127                 reg = <0xf 0xfe124000 0 0x1000>;
 128                 ranges = <0 0 0xf 0xe8000000 0x08000000
 129                           3 0 0xf 0xffdf0000 0x00008000>;
 130
 131                 flash@0,0 {
 132                         compatible = "cfi-flash";
 133                         reg = <0 0 0x08000000>;
 134                         bank-width = <2>;
 135                         device-width = <2>;
 136                 };
 137
 138                 board-control@3,0 {
 139                         compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
 140                         reg = <3 0 0x30>;
 141                 };
 142         };
 143
 144         pci0: pcie@ffe200000 {
 145                 reg = <0xf 0xfe200000 0 0x1000>;
 146                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 147                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 148                 pcie@0 {
 149                         ranges = <0x02000000 0 0xe0000000
 150                                   0x02000000 0 0xe0000000
 151                                   0 0x20000000
 152
 153                                   0x01000000 0 0x00000000
 154                                   0x01000000 0 0x00000000
 155                                   0 0x00010000>;
 156                 };
 157         };
 158
 159         pci1: pcie@ffe201000 {
 160                 reg = <0xf 0xfe201000 0 0x1000>;
 161                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 162                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 163                 pcie@0 {
 164                         ranges = <0x02000000 0 0xe0000000
 165                                   0x02000000 0 0xe0000000
 166                                   0 0x20000000
 167
 168                                   0x01000000 0 0x00000000
 169                                   0x01000000 0 0x00000000
 170                                   0 0x00010000>;
 171                 };
 172         };
 173
 174         pci2: pcie@ffe202000 {
 175                 reg = <0xf 0xfe202000 0 0x1000>;
 176                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 177                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 178                 pcie@0 {
 179                         ranges = <0x02000000 0 0xe0000000
 180                                   0x02000000 0 0xe0000000
 181                                   0 0x20000000
 182
 183                                   0x01000000 0 0x00000000
 184                                   0x01000000 0 0x00000000
 185                                   0 0x00010000>;
 186                 };
 187         };
 188
 189 };
 190
 191 /include/ "fsl/p4080si-post.dtsi"