| blob | 33a47e27a11e3578665efc4aeb005967abb1be27 |
1 /*
2 * SBC8548 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
14 /{
15 soc8548@e0000000 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 device_type = "soc";
19 ranges = <0x00000000 0xe0000000 0x00100000>;
20 bus-frequency = <0>;
21 compatible = "simple-bus";
23 ecm-law@0 {
24 compatible = "fsl,ecm-law";
25 reg = <0x0 0x1000>;
26 fsl,num-laws = <10>;
27 };
29 ecm@1000 {
30 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
31 reg = <0x1000 0x1000>;
32 interrupts = <17 2>;
33 interrupt-parent = <&mpic>;
34 };
36 memory-controller@2000 {
37 compatible = "fsl,mpc8548-memory-controller";
38 reg = <0x2000 0x1000>;
39 interrupt-parent = <&mpic>;
40 interrupts = <0x12 0x2>;
41 };
43 L2: l2-cache-controller@20000 {
44 compatible = "fsl,mpc8548-l2-cache-controller";
45 reg = <0x20000 0x1000>;
46 cache-line-size = <0x20>; // 32 bytes
47 cache-size = <0x80000>; // L2, 512K
48 interrupt-parent = <&mpic>;
49 interrupts = <0x10 0x2>;
50 };
52 i2c@3000 {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 cell-index = <0>;
56 compatible = "fsl-i2c";
57 reg = <0x3000 0x100>;
58 interrupts = <0x2b 0x2>;
59 interrupt-parent = <&mpic>;
60 dfsrr;
61 };
63 i2c@3100 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 cell-index = <1>;
67 compatible = "fsl-i2c";
68 reg = <0x3100 0x100>;
69 interrupts = <0x2b 0x2>;
70 interrupt-parent = <&mpic>;
71 dfsrr;
72 };
74 dma@21300 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
78 reg = <0x21300 0x4>;
79 ranges = <0x0 0x21100 0x200>;
80 cell-index = <0>;
81 dma-channel@0 {
82 compatible = "fsl,mpc8548-dma-channel",
83 "fsl,eloplus-dma-channel";
84 reg = <0x0 0x80>;
85 cell-index = <0>;
86 interrupt-parent = <&mpic>;
87 interrupts = <20 2>;
88 };
89 dma-channel@80 {
90 compatible = "fsl,mpc8548-dma-channel",
91 "fsl,eloplus-dma-channel";
92 reg = <0x80 0x80>;
93 cell-index = <1>;
94 interrupt-parent = <&mpic>;
95 interrupts = <21 2>;
96 };
97 dma-channel@100 {
98 compatible = "fsl,mpc8548-dma-channel",
99 "fsl,eloplus-dma-channel";
100 reg = <0x100 0x80>;
101 cell-index = <2>;
102 interrupt-parent = <&mpic>;
103 interrupts = <22 2>;
104 };
105 dma-channel@180 {
106 compatible = "fsl,mpc8548-dma-channel",
107 "fsl,eloplus-dma-channel";
108 reg = <0x180 0x80>;
109 cell-index = <3>;
110 interrupt-parent = <&mpic>;
111 interrupts = <23 2>;
112 };
113 };
115 enet0: ethernet@24000 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 cell-index = <0>;
119 device_type = "network";
120 model = "eTSEC";
121 compatible = "gianfar";
122 reg = <0x24000 0x1000>;
123 ranges = <0x0 0x24000 0x1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
126 interrupt-parent = <&mpic>;
127 tbi-handle = <&tbi0>;
128 phy-handle = <&phy0>;
130 mdio@520 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,gianfar-mdio";
134 reg = <0x520 0x20>;
136 phy0: ethernet-phy@19 {
137 interrupt-parent = <&mpic>;
138 interrupts = <0x6 0x1>;
139 reg = <0x19>;
140 device_type = "ethernet-phy";
141 };
142 phy1: ethernet-phy@1a {
143 interrupt-parent = <&mpic>;
144 interrupts = <0x7 0x1>;
145 reg = <0x1a>;
146 device_type = "ethernet-phy";
147 };
148 tbi0: tbi-phy@11 {
149 reg = <0x11>;
150 device_type = "tbi-phy";
151 };
152 };
153 };
155 enet1: ethernet@25000 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 cell-index = <1>;
159 device_type = "network";
160 model = "eTSEC";
161 compatible = "gianfar";
162 reg = <0x25000 0x1000>;
163 ranges = <0x0 0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
166 interrupt-parent = <&mpic>;
167 tbi-handle = <&tbi1>;
168 phy-handle = <&phy1>;
170 mdio@520 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,gianfar-tbi";
174 reg = <0x520 0x20>;
176 tbi1: tbi-phy@11 {
177 reg = <0x11>;
178 device_type = "tbi-phy";
179 };
180 };
181 };
183 serial0: serial@4500 {
184 cell-index = <0>;
185 device_type = "serial";
186 compatible = "fsl,ns16550", "ns16550";
187 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <0x2a 0x2>;
190 interrupt-parent = <&mpic>;
191 };
193 serial1: serial@4600 {
194 cell-index = <1>;
195 device_type = "serial";
196 compatible = "fsl,ns16550", "ns16550";
197 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <0x2a 0x2>;
200 interrupt-parent = <&mpic>;
201 };
203 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts";
205 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr;
207 };
209 crypto@30000 {
210 compatible = "fsl,sec2.1", "fsl,sec2.0";
211 reg = <0x30000 0x10000>;
212 interrupts = <45 2>;
213 interrupt-parent = <&mpic>;
214 fsl,num-channels = <4>;
215 fsl,channel-fifo-len = <24>;
216 fsl,exec-units-mask = <0xfe>;
217 fsl,descriptor-types-mask = <0x12b0ebf>;
218 };
220 mpic: pic@40000 {
221 interrupt-controller;
222 #address-cells = <0>;
223 #interrupt-cells = <2>;
224 reg = <0x40000 0x40000>;
225 compatible = "chrp,open-pic";
226 device_type = "open-pic";
227 };
228 };
230 pci0: pci@e0008000 {
231 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
232 interrupt-map = <
233 /* IDSEL 0x01 (PCI-X slot) @66MHz */
234 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
235 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
236 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
237 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
239 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
240 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
241 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
242 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
243 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
245 interrupt-parent = <&mpic>;
246 interrupts = <0x18 0x2>;
247 bus-range = <0 0>;
248 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
249 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
250 clock-frequency = <66000000>;
251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
254 reg = <0xe0008000 0x1000>;
255 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
256 device_type = "pci";
257 };
259 pci1: pcie@e000a000 {
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
261 interrupt-map = <
263 /* IDSEL 0x0 (PEX) */
264 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
265 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
266 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
267 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
269 interrupt-parent = <&mpic>;
270 interrupts = <0x1a 0x2>;
271 bus-range = <0x0 0xff>;
272 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
273 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
274 clock-frequency = <33000000>;
275 #interrupt-cells = <1>;
276 #size-cells = <2>;
277 #address-cells = <3>;
278 reg = <0xe000a000 0x1000>;
279 compatible = "fsl,mpc8548-pcie";
280 device_type = "pci";
281 pcie@0 {
282 reg = <0x0 0x0 0x0 0x0 0x0>;
283 #size-cells = <2>;
284 #address-cells = <3>;
285 device_type = "pci";
286 ranges = <0x02000000 0x0 0xa0000000
287 0x02000000 0x0 0xa0000000
288 0x0 0x10000000
290 0x01000000 0x0 0x00000000
291 0x01000000 0x0 0x00000000
292 0x0 0x00800000>;
293 };
294 };
295 };