2 * TQM 8541 Device Tree Source
4 * Copyright 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "tqc,tqm8541";
16 compatible = "tqc,tqm8541";
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
57 compatible = "fsl,mpc8541-immr", "simple-bus";
60 compatible = "fsl,ecm-law";
66 compatible = "fsl,mpc8541-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
69 interrupt-parent = <&mpic>;
72 memory-controller@2000 {
73 compatible = "fsl,mpc8540-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&mpic>;
99 compatible = "national,lm75";
104 compatible = "dallas,ds1337";
110 #address-cells = <1>;
112 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
114 ranges = <0x0 0x21100 0x200>;
117 compatible = "fsl,mpc8541-dma-channel",
118 "fsl,eloplus-dma-channel";
121 interrupt-parent = <&mpic>;
125 compatible = "fsl,mpc8541-dma-channel",
126 "fsl,eloplus-dma-channel";
129 interrupt-parent = <&mpic>;
133 compatible = "fsl,mpc8541-dma-channel",
134 "fsl,eloplus-dma-channel";
137 interrupt-parent = <&mpic>;
141 compatible = "fsl,mpc8541-dma-channel",
142 "fsl,eloplus-dma-channel";
145 interrupt-parent = <&mpic>;
150 enet0: ethernet@24000 {
151 #address-cells = <1>;
154 device_type = "network";
156 compatible = "gianfar";
157 reg = <0x24000 0x1000>;
158 ranges = <0x0 0x24000 0x1000>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <29 2 30 2 34 2>;
161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
166 #address-cells = <1>;
168 compatible = "fsl,gianfar-mdio";
171 phy1: ethernet-phy@1 {
172 interrupt-parent = <&mpic>;
175 device_type = "ethernet-phy";
177 phy2: ethernet-phy@2 {
178 interrupt-parent = <&mpic>;
181 device_type = "ethernet-phy";
183 phy3: ethernet-phy@3 {
184 interrupt-parent = <&mpic>;
187 device_type = "ethernet-phy";
191 device_type = "tbi-phy";
196 enet1: ethernet@25000 {
197 #address-cells = <1>;
200 device_type = "network";
202 compatible = "gianfar";
203 reg = <0x25000 0x1000>;
204 ranges = <0x0 0x25000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <35 2 36 2 40 2>;
207 interrupt-parent = <&mpic>;
208 tbi-handle = <&tbi1>;
209 phy-handle = <&phy1>;
212 #address-cells = <1>;
214 compatible = "fsl,gianfar-tbi";
219 device_type = "tbi-phy";
224 serial0: serial@4500 {
226 device_type = "serial";
227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot?
231 interrupt-parent = <&mpic>;
234 serial1: serial@4600 {
236 device_type = "serial";
237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot?
241 interrupt-parent = <&mpic>;
245 compatible = "fsl,sec2.0";
246 reg = <0x30000 0x10000>;
248 interrupt-parent = <&mpic>;
249 fsl,num-channels = <4>;
250 fsl,channel-fifo-len = <24>;
251 fsl,exec-units-mask = <0x7e>;
252 fsl,descriptor-types-mask = <0x01010ebf>;
256 interrupt-controller;
257 #address-cells = <0>;
258 #interrupt-cells = <2>;
259 reg = <0x40000 0x40000>;
260 device_type = "open-pic";
261 compatible = "chrp,open-pic";
265 #address-cells = <1>;
267 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
268 reg = <0x919c0 0x30>;
272 #address-cells = <1>;
274 ranges = <0 0x80000 0x10000>;
277 compatible = "fsl,cpm-muram-data";
278 reg = <0 0x2000 0x9000 0x1000>;
283 compatible = "fsl,mpc8541-brg",
286 reg = <0x919f0 0x10 0x915f0 0x10>;
287 clock-frequency = <0>;
291 interrupt-controller;
292 #address-cells = <0>;
293 #interrupt-cells = <2>;
295 interrupt-parent = <&mpic>;
296 reg = <0x90c00 0x80>;
297 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
303 #interrupt-cells = <1>;
305 #address-cells = <3>;
306 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
308 reg = <0xe0008000 0x1000>;
309 clock-frequency = <66666666>;
310 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
323 interrupt-parent = <&mpic>;
326 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
327 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;