2 * TQM8548 Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xa0000000 0x100000>;
59 compatible = "fsl,mpc8548-immr", "simple-bus";
62 compatible = "fsl,ecm-law";
68 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
71 interrupt-parent = <&mpic>;
74 memory-controller@2000 {
75 compatible = "fsl,mpc8548-memory-controller";
76 reg = <0x2000 0x1000>;
77 interrupt-parent = <&mpic>;
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8548-l2-cache-controller";
83 reg = <0x20000 0x1000>;
84 cache-line-size = <32>; // 32 bytes
85 cache-size = <0x80000>; // L2, 512K
86 interrupt-parent = <&mpic>;
94 compatible = "fsl-i2c";
97 interrupt-parent = <&mpic>;
101 compatible = "national,lm75";
106 compatible = "dallas,ds1337";
112 #address-cells = <1>;
115 compatible = "fsl-i2c";
116 reg = <0x3100 0x100>;
118 interrupt-parent = <&mpic>;
123 #address-cells = <1>;
125 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
127 ranges = <0x0 0x21100 0x200>;
130 compatible = "fsl,mpc8548-dma-channel",
131 "fsl,eloplus-dma-channel";
134 interrupt-parent = <&mpic>;
138 compatible = "fsl,mpc8548-dma-channel",
139 "fsl,eloplus-dma-channel";
142 interrupt-parent = <&mpic>;
146 compatible = "fsl,mpc8548-dma-channel",
147 "fsl,eloplus-dma-channel";
150 interrupt-parent = <&mpic>;
154 compatible = "fsl,mpc8548-dma-channel",
155 "fsl,eloplus-dma-channel";
158 interrupt-parent = <&mpic>;
163 enet0: ethernet@24000 {
164 #address-cells = <1>;
167 device_type = "network";
169 compatible = "gianfar";
170 reg = <0x24000 0x1000>;
171 ranges = <0x0 0x24000 0x1000>;
172 local-mac-address = [ 00 00 00 00 00 00 ];
173 interrupts = <29 2 30 2 34 2>;
174 interrupt-parent = <&mpic>;
175 tbi-handle = <&tbi0>;
176 phy-handle = <&phy2>;
179 #address-cells = <1>;
181 compatible = "fsl,gianfar-mdio";
184 phy1: ethernet-phy@0 {
185 interrupt-parent = <&mpic>;
188 device_type = "ethernet-phy";
190 phy2: ethernet-phy@1 {
191 interrupt-parent = <&mpic>;
194 device_type = "ethernet-phy";
196 phy3: ethernet-phy@3 {
197 interrupt-parent = <&mpic>;
200 device_type = "ethernet-phy";
202 phy4: ethernet-phy@4 {
203 interrupt-parent = <&mpic>;
206 device_type = "ethernet-phy";
208 phy5: ethernet-phy@5 {
209 interrupt-parent = <&mpic>;
212 device_type = "ethernet-phy";
216 device_type = "tbi-phy";
221 enet1: ethernet@25000 {
222 #address-cells = <1>;
225 device_type = "network";
227 compatible = "gianfar";
228 reg = <0x25000 0x1000>;
229 ranges = <0x0 0x25000 0x1000>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 interrupts = <35 2 36 2 40 2>;
232 interrupt-parent = <&mpic>;
233 tbi-handle = <&tbi1>;
234 phy-handle = <&phy1>;
237 #address-cells = <1>;
239 compatible = "fsl,gianfar-tbi";
244 device_type = "tbi-phy";
249 enet2: ethernet@26000 {
250 #address-cells = <1>;
253 device_type = "network";
255 compatible = "gianfar";
256 reg = <0x26000 0x1000>;
257 ranges = <0x0 0x26000 0x1000>;
258 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupts = <31 2 32 2 33 2>;
260 interrupt-parent = <&mpic>;
261 tbi-handle = <&tbi2>;
262 phy-handle = <&phy4>;
265 #address-cells = <1>;
267 compatible = "fsl,gianfar-tbi";
272 device_type = "tbi-phy";
277 enet3: ethernet@27000 {
278 #address-cells = <1>;
281 device_type = "network";
283 compatible = "gianfar";
284 reg = <0x27000 0x1000>;
285 ranges = <0x0 0x27000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <37 2 38 2 39 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi3>;
290 phy-handle = <&phy5>;
293 #address-cells = <1>;
295 compatible = "fsl,gianfar-tbi";
300 device_type = "tbi-phy";
305 serial0: serial@4500 {
307 device_type = "serial";
308 compatible = "fsl,ns16550", "ns16550";
309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>;
313 interrupt-parent = <&mpic>;
316 serial1: serial@4600 {
318 device_type = "serial";
319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>;
324 interrupt-parent = <&mpic>;
327 global-utilities@e0000 { // global utilities reg
328 compatible = "fsl,mpc8548-guts";
329 reg = <0xe0000 0x1000>;
334 interrupt-controller;
335 #address-cells = <0>;
336 #interrupt-cells = <2>;
337 reg = <0x40000 0x40000>;
338 compatible = "chrp,open-pic";
339 device_type = "open-pic";
344 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
346 #address-cells = <2>;
348 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
349 interrupt-parent = <&mpic>;
353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
355 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770)
356 3 0x0 0xa3010000 0x00008000 // NAND FLASH
361 #address-cells = <1>;
363 compatible = "cfi-flash";
364 reg = <1 0x0 0x8000000>;
370 reg = <0x00000000 0x00200000>;
374 reg = <0x00200000 0x00300000>;
378 reg = <0x00500000 0x07a00000>;
382 reg = <0x07f00000 0x00040000>;
386 reg = <0x07f40000 0x00040000>;
390 reg = <0x07f80000 0x00080000>;
395 /* Note: CAN support needs be enabled in U-Boot */
397 compatible = "bosch,cc770"; // Bosch CC770
400 interrupt-parent = <&mpic>;
401 bosch,external-clock-frequency = <16000000>;
402 bosch,disconnect-rx1-input;
403 bosch,disconnect-tx1-output;
404 bosch,iso-low-speed-mux;
405 bosch,clock-out-frequency = <16000000>;
409 compatible = "bosch,cc770"; // Bosch CC770
410 reg = <2 0x100 0x100>;
412 interrupt-parent = <&mpic>;
413 bosch,external-clock-frequency = <16000000>;
414 bosch,disconnect-rx1-input;
415 bosch,disconnect-tx1-output;
416 bosch,iso-low-speed-mux;
419 /* Note: NAND support needs to be enabled in U-Boot */
421 #address-cells = <0>;
423 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
425 fsl,upm-addr-offset = <0x10>;
426 fsl,upm-cmd-offset = <0x08>;
427 /* Micron MT29F8G08FAB multi-chip device */
428 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
429 fsl,upm-wait-flags = <0x5>;
430 chip-delay = <25>; // in micro-seconds
433 #address-cells = <1>;
438 reg = <0x00000000 0x10000000>;
445 #interrupt-cells = <1>;
447 #address-cells = <3>;
448 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
450 reg = <0xa0008000 0x1000>;
451 clock-frequency = <33333333>;
452 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
455 0xe000 0 0 1 &mpic 2 1
456 0xe000 0 0 2 &mpic 3 1
457 0xe000 0 0 3 &mpic 6 1
458 0xe000 0 0 4 &mpic 5 1
461 0x5800 0 0 1 &mpic 6 1
462 0x5800 0 0 2 &mpic 5 1
465 interrupt-parent = <&mpic>;
468 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
469 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
472 pci1: pcie@a000a000 {
473 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
475 /* IDSEL 0x0 (PEX) */
476 0x00000 0 0 1 &mpic 0 1
477 0x00000 0 0 2 &mpic 1 1
478 0x00000 0 0 3 &mpic 2 1
479 0x00000 0 0 4 &mpic 3 1>;
481 interrupt-parent = <&mpic>;
483 bus-range = <0 0xff>;
484 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
485 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
486 clock-frequency = <33333333>;
487 #interrupt-cells = <1>;
489 #address-cells = <3>;
490 reg = <0xa000a000 0x1000>;
491 compatible = "fsl,mpc8548-pcie";
496 #address-cells = <3>;
498 ranges = <0x02000000 0 0xb0000000 0x02000000 0
499 0xb0000000 0 0x10000000
500 0x01000000 0 0x00000000 0x01000000 0
501 0x00000000 0 0x08000000>;