| blob | 11dbda10d7563dbe574e2cb60e13b09cb0927f01 |
1 /*
2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4 *
5 * XPedite5370 3U VPX single-board computer based on MPC8572E
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 /dts-v1/;
13 / {
14 model = "xes,xpedite5370";
15 compatible = "xes,xpedite5370", "xes,MPC8572";
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci1 = &pci1;
25 pci2 = &pci2;
26 };
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
32 PowerPC,8572@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
43 };
45 PowerPC,8572@1 {
46 device_type = "cpu";
47 reg = <0x1>;
48 d-cache-line-size = <32>; // 32 bytes
49 i-cache-line-size = <32>; // 32 bytes
50 d-cache-size = <0x8000>; // L1, 32K
51 i-cache-size = <0x8000>; // L1, 32K
52 timebase-frequency = <0>;
53 bus-frequency = <0>;
54 clock-frequency = <0>;
55 next-level-cache = <&L2>;
56 };
57 };
59 memory {
60 device_type = "memory";
61 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
62 };
64 localbus@ef005000 {
65 #address-cells = <2>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
68 reg = <0 0xef005000 0 0x1000>;
69 interrupts = <19 2>;
70 interrupt-parent = <&mpic>;
71 /* Local bus region mappings */
72 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
73 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
74 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
75 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
77 nor-boot@0,0 {
78 compatible = "amd,s29gl01gp", "cfi-flash";
79 bank-width = <2>;
80 reg = <0 0 0x8000000>; /* 128MB */
81 #address-cells = <1>;
82 #size-cells = <1>;
83 partition@0 {
84 label = "Primary user space";
85 reg = <0x00000000 0x6f00000>; /* 111 MB */
86 };
87 partition@6f00000 {
88 label = "Primary kernel";
89 reg = <0x6f00000 0x1000000>; /* 16 MB */
90 };
91 partition@7f00000 {
92 label = "Primary DTB";
93 reg = <0x7f00000 0x40000>; /* 256 KB */
94 };
95 partition@7f40000 {
96 label = "Primary U-Boot environment";
97 reg = <0x7f40000 0x40000>; /* 256 KB */
98 };
99 partition@7f80000 {
100 label = "Primary U-Boot";
101 reg = <0x7f80000 0x80000>; /* 512 KB */
102 read-only;
103 };
104 };
106 nor-alternate@1,0 {
107 compatible = "amd,s29gl01gp", "cfi-flash";
108 bank-width = <2>;
109 //reg = <0xf0000000 0x08000000>; /* 128MB */
110 reg = <1 0 0x8000000>; /* 128MB */
111 #address-cells = <1>;
112 #size-cells = <1>;
113 partition@0 {
114 label = "Secondary user space";
115 reg = <0x00000000 0x6f00000>; /* 111 MB */
116 };
117 partition@6f00000 {
118 label = "Secondary kernel";
119 reg = <0x6f00000 0x1000000>; /* 16 MB */
120 };
121 partition@7f00000 {
122 label = "Secondary DTB";
123 reg = <0x7f00000 0x40000>; /* 256 KB */
124 };
125 partition@7f40000 {
126 label = "Secondary U-Boot environment";
127 reg = <0x7f40000 0x40000>; /* 256 KB */
128 };
129 partition@7f80000 {
130 label = "Secondary U-Boot";
131 reg = <0x7f80000 0x80000>; /* 512 KB */
132 read-only;
133 };
134 };
136 nand@2,0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 /*
140 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
141 * Micron MT29F8G08DAA (2x 512 MB), or Micron
142 * MT29F16G08FAA (2x 1 GB), depending on the build
143 * configuration
144 */
145 compatible = "fsl,mpc8572-fcm-nand",
146 "fsl,elbc-fcm-nand";
147 reg = <2 0 0x40000>;
148 /* U-Boot should fix this up if chip size > 1 GB */
149 partition@0 {
150 label = "NAND Filesystem";
151 reg = <0 0x40000000>;
152 };
153 };
155 };
157 soc8572@ef000000 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 device_type = "soc";
161 compatible = "fsl,mpc8572-immr", "simple-bus";
162 ranges = <0x0 0 0xef000000 0x100000>;
163 bus-frequency = <0>; // Filled out by uboot.
165 ecm-law@0 {
166 compatible = "fsl,ecm-law";
167 reg = <0x0 0x1000>;
168 fsl,num-laws = <12>;
169 };
171 ecm@1000 {
172 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
173 reg = <0x1000 0x1000>;
174 interrupts = <17 2>;
175 interrupt-parent = <&mpic>;
176 };
178 memory-controller@2000 {
179 compatible = "fsl,mpc8572-memory-controller";
180 reg = <0x2000 0x1000>;
181 interrupt-parent = <&mpic>;
182 interrupts = <18 2>;
183 };
185 memory-controller@6000 {
186 compatible = "fsl,mpc8572-memory-controller";
187 reg = <0x6000 0x1000>;
188 interrupt-parent = <&mpic>;
189 interrupts = <18 2>;
190 };
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8572-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x100000>; // L2, 1M
197 interrupt-parent = <&mpic>;
198 interrupts = <16 2>;
199 };
201 i2c@3000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 cell-index = <0>;
205 compatible = "fsl-i2c";
206 reg = <0x3000 0x100>;
207 interrupts = <43 2>;
208 interrupt-parent = <&mpic>;
209 dfsrr;
211 temp-sensor@48 {
212 compatible = "dallas,ds1631", "dallas,ds1621";
213 reg = <0x48>;
214 };
216 temp-sensor@4c {
217 compatible = "adi,adt7461";
218 reg = <0x4c>;
219 };
221 cpu-supervisor@51 {
222 compatible = "dallas,ds4510";
223 reg = <0x51>;
224 };
226 eeprom@54 {
227 compatible = "atmel,at24c128b";
228 reg = <0x54>;
229 };
231 rtc@68 {
232 compatible = "stm,m41t00",
233 "dallas,ds1338";
234 reg = <0x68>;
235 };
237 pcie-switch@70 {
238 compatible = "plx,pex8518";
239 reg = <0x70>;
240 };
242 gpio1: gpio@18 {
243 compatible = "nxp,pca9557";
244 reg = <0x18>;
245 #gpio-cells = <2>;
246 gpio-controller;
247 polarity = <0x00>;
248 };
250 gpio2: gpio@1c {
251 compatible = "nxp,pca9557";
252 reg = <0x1c>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 polarity = <0x00>;
256 };
258 gpio3: gpio@1e {
259 compatible = "nxp,pca9557";
260 reg = <0x1e>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 polarity = <0x00>;
264 };
266 gpio4: gpio@1f {
267 compatible = "nxp,pca9557";
268 reg = <0x1f>;
269 #gpio-cells = <2>;
270 gpio-controller;
271 polarity = <0x00>;
272 };
273 };
275 i2c@3100 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 cell-index = <1>;
279 compatible = "fsl-i2c";
280 reg = <0x3100 0x100>;
281 interrupts = <43 2>;
282 interrupt-parent = <&mpic>;
283 dfsrr;
284 };
286 dma@c300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0xc300 0x4>;
291 ranges = <0x0 0xc100 0x200>;
292 cell-index = <1>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <76 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <77 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <78 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <79 2>;
324 };
325 };
327 dma@21300 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
331 reg = <0x21300 0x4>;
332 ranges = <0x0 0x21100 0x200>;
333 cell-index = <0>;
334 dma-channel@0 {
335 compatible = "fsl,mpc8572-dma-channel",
336 "fsl,eloplus-dma-channel";
337 reg = <0x0 0x80>;
338 cell-index = <0>;
339 interrupt-parent = <&mpic>;
340 interrupts = <20 2>;
341 };
342 dma-channel@80 {
343 compatible = "fsl,mpc8572-dma-channel",
344 "fsl,eloplus-dma-channel";
345 reg = <0x80 0x80>;
346 cell-index = <1>;
347 interrupt-parent = <&mpic>;
348 interrupts = <21 2>;
349 };
350 dma-channel@100 {
351 compatible = "fsl,mpc8572-dma-channel",
352 "fsl,eloplus-dma-channel";
353 reg = <0x100 0x80>;
354 cell-index = <2>;
355 interrupt-parent = <&mpic>;
356 interrupts = <22 2>;
357 };
358 dma-channel@180 {
359 compatible = "fsl,mpc8572-dma-channel",
360 "fsl,eloplus-dma-channel";
361 reg = <0x180 0x80>;
362 cell-index = <3>;
363 interrupt-parent = <&mpic>;
364 interrupts = <23 2>;
365 };
366 };
368 /* eTSEC 1 */
369 enet0: ethernet@24000 {
370 #address-cells = <1>;
371 #size-cells = <1>;
372 cell-index = <0>;
373 device_type = "network";
374 model = "eTSEC";
375 compatible = "gianfar";
376 reg = <0x24000 0x1000>;
377 ranges = <0x0 0x24000 0x1000>;
378 local-mac-address = [ 00 00 00 00 00 00 ];
379 interrupts = <29 2 30 2 34 2>;
380 interrupt-parent = <&mpic>;
381 tbi-handle = <&tbi0>;
382 phy-handle = <&phy0>;
383 phy-connection-type = "sgmii";
385 mdio@520 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "fsl,gianfar-mdio";
389 reg = <0x520 0x20>;
391 phy0: ethernet-phy@1 {
392 interrupt-parent = <&mpic>;
393 interrupts = <8 1>;
394 reg = <0x1>;
395 };
396 phy1: ethernet-phy@2 {
397 interrupt-parent = <&mpic>;
398 interrupts = <8 1>;
399 reg = <0x2>;
400 };
401 tbi0: tbi-phy@11 {
402 reg = <0x11>;
403 device_type = "tbi-phy";
404 };
405 };
406 };
408 /* eTSEC 2 */
409 enet1: ethernet@25000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <1>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "gianfar";
416 reg = <0x25000 0x1000>;
417 ranges = <0x0 0x25000 0x1000>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupts = <35 2 36 2 40 2>;
420 interrupt-parent = <&mpic>;
421 tbi-handle = <&tbi1>;
422 phy-handle = <&phy1>;
423 phy-connection-type = "sgmii";
425 mdio@520 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "fsl,gianfar-tbi";
429 reg = <0x520 0x20>;
431 tbi1: tbi-phy@11 {
432 reg = <0x11>;
433 device_type = "tbi-phy";
434 };
435 };
436 };
438 /* UART0 */
439 serial0: serial@4500 {
440 cell-index = <0>;
441 device_type = "serial";
442 compatible = "fsl,ns16550", "ns16550";
443 reg = <0x4500 0x100>;
444 clock-frequency = <0>;
445 interrupts = <42 2>;
446 interrupt-parent = <&mpic>;
447 };
449 /* UART1 */
450 serial1: serial@4600 {
451 cell-index = <1>;
452 device_type = "serial";
453 compatible = "fsl,ns16550", "ns16550";
454 reg = <0x4600 0x100>;
455 clock-frequency = <0>;
456 interrupts = <42 2>;
457 interrupt-parent = <&mpic>;
458 };
460 global-utilities@e0000 { //global utilities block
461 compatible = "fsl,mpc8572-guts";
462 reg = <0xe0000 0x1000>;
463 fsl,has-rstcr;
464 };
466 msi@41600 {
467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
468 reg = <0x41600 0x80>;
469 msi-available-ranges = <0 0x100>;
470 interrupts = <
471 0xe0 0
472 0xe1 0
473 0xe2 0
474 0xe3 0
475 0xe4 0
476 0xe5 0
477 0xe6 0
478 0xe7 0>;
479 interrupt-parent = <&mpic>;
480 };
482 crypto@30000 {
483 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
484 "fsl,sec2.1", "fsl,sec2.0";
485 reg = <0x30000 0x10000>;
486 interrupts = <45 2 58 2>;
487 interrupt-parent = <&mpic>;
488 fsl,num-channels = <4>;
489 fsl,channel-fifo-len = <24>;
490 fsl,exec-units-mask = <0x9fe>;
491 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 };
494 mpic: pic@40000 {
495 interrupt-controller;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
498 reg = <0x40000 0x40000>;
499 compatible = "chrp,open-pic";
500 device_type = "open-pic";
501 };
503 gpio0: gpio@f000 {
504 compatible = "fsl,mpc8572-gpio";
505 reg = <0xf000 0x1000>;
506 interrupts = <47 2>;
507 interrupt-parent = <&mpic>;
508 #gpio-cells = <2>;
509 gpio-controller;
510 };
512 gpio-leds {
513 compatible = "gpio-leds";
515 heartbeat {
516 label = "Heartbeat";
517 gpios = <&gpio0 4 1>;
518 linux,default-trigger = "heartbeat";
519 };
521 yellow {
522 label = "Yellow";
523 gpios = <&gpio0 5 1>;
524 };
526 red {
527 label = "Red";
528 gpios = <&gpio0 6 1>;
529 };
531 green {
532 label = "Green";
533 gpios = <&gpio0 7 1>;
534 };
535 };
537 /* PME (pattern-matcher) */
538 pme@10000 {
539 compatible = "fsl,mpc8572-pme", "pme8572";
540 reg = <0x10000 0x5000>;
541 interrupts = <57 2 64 2 65 2 66 2 67 2>;
542 interrupt-parent = <&mpic>;
543 };
545 tlu@2f000 {
546 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
547 reg = <0x2f000 0x1000>;
548 interupts = <61 2 >;
549 interrupt-parent = <&mpic>;
550 };
552 tlu@15000 {
553 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
554 reg = <0x15000 0x1000>;
555 interupts = <75 2>;
556 interrupt-parent = <&mpic>;
557 };
558 };
560 /*
561 * PCI Express controller 3 @ ef008000 is not used.
562 * This would have been pci0 on other mpc85xx platforms.
563 */
565 /* PCI Express controller 2, wired to VPX P1,P2 backplane */
566 pci1: pcie@ef009000 {
567 compatible = "fsl,mpc8548-pcie";
568 device_type = "pci";
569 #interrupt-cells = <1>;
570 #size-cells = <2>;
571 #address-cells = <3>;
572 reg = <0 0xef009000 0 0x1000>;
573 bus-range = <0 255>;
574 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
575 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
576 clock-frequency = <33333333>;
577 interrupt-parent = <&mpic>;
578 interrupts = <25 2>;
579 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
580 interrupt-map = <
581 /* IDSEL 0x0 */
582 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
583 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
584 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
585 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
586 >;
587 pcie@0 {
588 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
589 #size-cells = <2>;
590 #address-cells = <3>;
591 device_type = "pci";
592 ranges = <0x2000000 0x0 0xc0000000
593 0x2000000 0x0 0xc0000000
594 0x0 0x10000000
596 0x1000000 0x0 0x0
597 0x1000000 0x0 0x0
598 0x0 0x100000>;
599 };
600 };
602 /* PCI Express controller 1, wired to PEX8518 PCIe switch */
603 pci2: pcie@ef00a000 {
604 compatible = "fsl,mpc8548-pcie";
605 device_type = "pci";
606 #interrupt-cells = <1>;
607 #size-cells = <2>;
608 #address-cells = <3>;
609 reg = <0 0xef00a000 0 0x1000>;
610 bus-range = <0 255>;
611 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
612 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
613 clock-frequency = <33333333>;
614 interrupt-parent = <&mpic>;
615 interrupts = <26 2>;
616 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
617 interrupt-map = <
618 /* IDSEL 0x0 */
619 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
620 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
621 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
622 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
623 >;
624 pcie@0 {
625 reg = <0x0 0x0 0x0 0x0 0x0>;
626 #size-cells = <2>;
627 #address-cells = <3>;
628 device_type = "pci";
629 ranges = <0x2000000 0x0 0x80000000
630 0x2000000 0x0 0x80000000
631 0x0 0x40000000
633 0x1000000 0x0 0x0
634 0x1000000 0x0 0x0
635 0x0 0x100000>;
636 };
637 };
638 };