1 #ifndef _ASM_POWERPC_CACHE_H
2 #define _ASM_POWERPC_CACHE_H
7 /* bytes per L1 cache line */
8 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
9 #define L1_CACHE_SHIFT 4
10 #define MAX_COPY_PREFETCH 1
11 #elif defined(CONFIG_PPC_E500MC)
12 #define L1_CACHE_SHIFT 6
13 #define MAX_COPY_PREFETCH 4
14 #elif defined(CONFIG_PPC32)
15 #define MAX_COPY_PREFETCH 4
16 #if defined(CONFIG_PPC_47x)
17 #define L1_CACHE_SHIFT 7
19 #define L1_CACHE_SHIFT 5
21 #else /* CONFIG_PPC64 */
22 #define L1_CACHE_SHIFT 7
25 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
27 #define SMP_CACHE_BYTES L1_CACHE_BYTES
29 #if defined(__powerpc64__) && !defined(__ASSEMBLY__)
31 u32 dsize
; /* L1 d-cache size */
32 u32 dline_size
; /* L1 d-cache line size */
35 u32 isize
; /* L1 i-cache size */
36 u32 iline_size
; /* L1 i-cache line size */
41 extern struct ppc64_caches ppc64_caches
;
42 #endif /* __powerpc64__ && ! __ASSEMBLY__ */
44 #if !defined(__ASSEMBLY__)
46 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
49 extern long _get_L2CR(void);
50 extern long _get_L3CR(void);
51 extern void _set_L2CR(unsigned long);
52 extern void _set_L3CR(unsigned long);
54 #define _get_L2CR() 0L
55 #define _get_L3CR() 0L
56 #define _set_L2CR(val) do { } while(0)
57 #define _set_L3CR(val) do { } while(0)
60 extern void cacheable_memzero(void *p
, unsigned int nb
);
61 extern void *cacheable_memcpy(void *, const void *, unsigned int);
63 #endif /* !__ASSEMBLY__ */
64 #endif /* __KERNEL__ */
65 #endif /* _ASM_POWERPC_CACHE_H */