arch/powerpc/include/asm/eeh.h

   1 /*
   2  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3  * Copyright 2001-2012 IBM Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _POWERPC_EEH_H
  21 #define _POWERPC_EEH_H
  22 #ifdef __KERNEL__
  23
  24 #include <linux/init.h>
  25 #include <linux/list.h>
  26 #include <linux/string.h>
  27 #include <linux/time.h>
  28
  29 struct pci_dev;
  30 struct pci_bus;
  31 struct device_node;
  32
  33 #ifdef CONFIG_EEH
  34
  35 /*
  36  * The struct is used to trace PE related EEH functionality.
  37  * In theory, there will have one instance of the struct to
  38  * be created against particular PE. In nature, PEs corelate
  39  * to each other. the struct has to reflect that hierarchy in
  40  * order to easily pick up those affected PEs when one particular
  41  * PE has EEH errors.
  42  *
  43  * Also, one particular PE might be composed of PCI device, PCI
  44  * bus and its subordinate components. The struct also need ship
  45  * the information. Further more, one particular PE is only meaingful
  46  * in the corresponding PHB. Therefore, the root PEs should be created
  47  * against existing PHBs in on-to-one fashion.
  48  */
  49 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  50 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  51 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  52 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  53
  54 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  55 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  56 #define EEH_PE_PHB_DEAD         (1 << 2)        /* Dead PHB             */
  57
  58 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  59
  60 struct eeh_pe {
  61         int type;                       /* PE type: PHB/Bus/Device      */
  62         int state;                      /* PE EEH dependent mode        */
  63         int config_addr;                /* Traditional PCI address      */
  64         int addr;                       /* PE configuration address     */
  65         struct pci_controller *phb;     /* Associated PHB               */
  66         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  67         int check_count;                /* Times of ignored error       */
  68         int freeze_count;               /* Times of froze up            */
  69         struct timeval tstamp;          /* Time on first-time freeze    */
  70         int false_positives;            /* Times of reported #ff's      */
  71         struct eeh_pe *parent;          /* Parent PE                    */
  72         struct list_head child_list;    /* Link PE to the child list    */
  73         struct list_head edevs;         /* Link list of EEH devices     */
  74         struct list_head child;         /* Child PEs                    */
  75 };
  76
  77 #define eeh_pe_for_each_dev(pe, edev, tmp) \
  78                 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
  79
  80 /*
  81  * The struct is used to trace EEH state for the associated
  82  * PCI device node or PCI device. In future, it might
  83  * represent PE as well so that the EEH device to form
  84  * another tree except the currently existing tree of PCI
  85  * buses and PCI devices
  86  */
  87 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
  88 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
  89 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
  90 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
  91 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
  92
  93 #define EEH_DEV_SYSFS           (1 << 8)        /* Sysfs created        */
  94
  95 struct eeh_dev {
  96         int mode;                       /* EEH mode                     */
  97         int class_code;                 /* Class code of the device     */
  98         int config_addr;                /* Config address               */
  99         int pe_config_addr;             /* PE config address            */
 100         u32 config_space[16];           /* Saved PCI config space       */
 101         u8 pcie_cap;                    /* Saved PCIe capability        */
 102         struct eeh_pe *pe;              /* Associated PE                */
 103         struct list_head list;          /* Form link list in the PE     */
 104         struct pci_controller *phb;     /* Associated PHB               */
 105         struct device_node *dn;         /* Associated device node       */
 106         struct pci_dev *pdev;           /* Associated PCI device        */
 107         struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 108 };
 109
 110 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
 111 {
 112         return edev ? edev->dn : NULL;
 113 }
 114
 115 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 116 {
 117         return edev ? edev->pdev : NULL;
 118 }
 119
 120 /* Return values from eeh_ops::next_error */
 121 enum {
 122         EEH_NEXT_ERR_NONE = 0,
 123         EEH_NEXT_ERR_INF,
 124         EEH_NEXT_ERR_FROZEN_PE,
 125         EEH_NEXT_ERR_FENCED_PHB,
 126         EEH_NEXT_ERR_DEAD_PHB,
 127         EEH_NEXT_ERR_DEAD_IOC
 128 };
 129
 130 /*
 131  * The struct is used to trace the registered EEH operation
 132  * callback functions. Actually, those operation callback
 133  * functions are heavily platform dependent. That means the
 134  * platform should register its own EEH operation callback
 135  * functions before any EEH further operations.
 136  */
 137 #define EEH_OPT_DISABLE         0       /* EEH disable  */
 138 #define EEH_OPT_ENABLE          1       /* EEH enable   */
 139 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 140 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 141 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 142 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 143 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 144 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 145 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 146 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 147 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 148 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 149 #define EEH_RESET_HOT           1       /* Hot reset                    */
 150 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 151 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 152 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
 153
 154 struct eeh_ops {
 155         char *name;
 156         int (*init)(void);
 157         int (*post_init)(void);
 158         void* (*of_probe)(struct device_node *dn, void *flag);
 159         int (*dev_probe)(struct pci_dev *dev, void *flag);
 160         int (*set_option)(struct eeh_pe *pe, int option);
 161         int (*get_pe_addr)(struct eeh_pe *pe);
 162         int (*get_state)(struct eeh_pe *pe, int *state);
 163         int (*reset)(struct eeh_pe *pe, int option);
 164         int (*wait_state)(struct eeh_pe *pe, int max_wait);
 165         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 166         int (*configure_bridge)(struct eeh_pe *pe);
 167         int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
 168         int (*write_config)(struct device_node *dn, int where, int size, u32 val);
 169         int (*next_error)(struct eeh_pe **pe);
 170 };
 171
 172 extern struct eeh_ops *eeh_ops;
 173 extern int eeh_subsystem_enabled;
 174 extern raw_spinlock_t confirm_error_lock;
 175 extern int eeh_probe_mode;
 176
 177 #define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
 178 #define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
 179
 180 static inline void eeh_probe_mode_set(int flag)
 181 {
 182         eeh_probe_mode = flag;
 183 }
 184
 185 static inline int eeh_probe_mode_devtree(void)
 186 {
 187         return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
 188 }
 189
 190 static inline int eeh_probe_mode_dev(void)
 191 {
 192         return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
 193 }
 194
 195 static inline void eeh_serialize_lock(unsigned long *flags)
 196 {
 197         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 198 }
 199
 200 static inline void eeh_serialize_unlock(unsigned long flags)
 201 {
 202         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 203 }
 204
 205 /*
 206  * Max number of EEH freezes allowed before we consider the device
 207  * to be permanently disabled.
 208  */
 209 #define EEH_MAX_ALLOWED_FREEZES 5
 210
 211 typedef void *(*eeh_traverse_func)(void *data, void *flag);
 212 int eeh_phb_pe_create(struct pci_controller *phb);
 213 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 214 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 215 int eeh_add_to_parent_pe(struct eeh_dev *edev);
 216 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 217 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 218 void *eeh_pe_traverse(struct eeh_pe *root,
 219                 eeh_traverse_func fn, void *flag);
 220 void *eeh_pe_dev_traverse(struct eeh_pe *root,
 221                 eeh_traverse_func fn, void *flag);
 222 void eeh_pe_restore_bars(struct eeh_pe *pe);
 223 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 224
 225 void *eeh_dev_init(struct device_node *dn, void *data);
 226 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 227 int eeh_init(void);
 228 int __init eeh_ops_register(struct eeh_ops *ops);
 229 int __exit eeh_ops_unregister(const char *name);
 230 unsigned long eeh_check_failure(const volatile void __iomem *token,
 231                                 unsigned long val);
 232 int eeh_dev_check_failure(struct eeh_dev *edev);
 233 void eeh_addr_cache_build(void);
 234 void eeh_add_device_early(struct device_node *);
 235 void eeh_add_device_tree_early(struct device_node *);
 236 void eeh_add_device_late(struct pci_dev *);
 237 void eeh_add_device_tree_late(struct pci_bus *);
 238 void eeh_add_sysfs_files(struct pci_bus *);
 239 void eeh_remove_device(struct pci_dev *);
 240
 241 /**
 242  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 243  *
 244  * If this macro yields TRUE, the caller relays to eeh_check_failure()
 245  * which does further tests out of line.
 246  */
 247 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_subsystem_enabled)
 248
 249 /*
 250  * Reads from a device which has been isolated by EEH will return
 251  * all 1s.  This macro gives an all-1s value of the given size (in
 252  * bytes: 1, 2, or 4) for comparing with the result of a read.
 253  */
 254 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 255
 256 #else /* !CONFIG_EEH */
 257
 258 static inline int eeh_init(void)
 259 {
 260         return 0;
 261 }
 262
 263 static inline void *eeh_dev_init(struct device_node *dn, void *data)
 264 {
 265         return NULL;
 266 }
 267
 268 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 269
 270 static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 271 {
 272         return val;
 273 }
 274
 275 #define eeh_dev_check_failure(x) (0)
 276
 277 static inline void eeh_addr_cache_build(void) { }
 278
 279 static inline void eeh_add_device_early(struct device_node *dn) { }
 280
 281 static inline void eeh_add_device_tree_early(struct device_node *dn) { }
 282
 283 static inline void eeh_add_device_late(struct pci_dev *dev) { }
 284
 285 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 286
 287 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 288
 289 static inline void eeh_remove_device(struct pci_dev *dev) { }
 290
 291 #define EEH_POSSIBLE_ERROR(val, type) (0)
 292 #define EEH_IO_ERROR_VALUE(size) (-1UL)
 293 #endif /* CONFIG_EEH */
 294
 295 #ifdef CONFIG_PPC64
 296 /*
 297  * MMIO read/write operations with EEH support.
 298  */
 299 static inline u8 eeh_readb(const volatile void __iomem *addr)
 300 {
 301         u8 val = in_8(addr);
 302         if (EEH_POSSIBLE_ERROR(val, u8))
 303                 return eeh_check_failure(addr, val);
 304         return val;
 305 }
 306
 307 static inline u16 eeh_readw(const volatile void __iomem *addr)
 308 {
 309         u16 val = in_le16(addr);
 310         if (EEH_POSSIBLE_ERROR(val, u16))
 311                 return eeh_check_failure(addr, val);
 312         return val;
 313 }
 314
 315 static inline u32 eeh_readl(const volatile void __iomem *addr)
 316 {
 317         u32 val = in_le32(addr);
 318         if (EEH_POSSIBLE_ERROR(val, u32))
 319                 return eeh_check_failure(addr, val);
 320         return val;
 321 }
 322
 323 static inline u64 eeh_readq(const volatile void __iomem *addr)
 324 {
 325         u64 val = in_le64(addr);
 326         if (EEH_POSSIBLE_ERROR(val, u64))
 327                 return eeh_check_failure(addr, val);
 328         return val;
 329 }
 330
 331 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 332 {
 333         u16 val = in_be16(addr);
 334         if (EEH_POSSIBLE_ERROR(val, u16))
 335                 return eeh_check_failure(addr, val);
 336         return val;
 337 }
 338
 339 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 340 {
 341         u32 val = in_be32(addr);
 342         if (EEH_POSSIBLE_ERROR(val, u32))
 343                 return eeh_check_failure(addr, val);
 344         return val;
 345 }
 346
 347 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 348 {
 349         u64 val = in_be64(addr);
 350         if (EEH_POSSIBLE_ERROR(val, u64))
 351                 return eeh_check_failure(addr, val);
 352         return val;
 353 }
 354
 355 static inline void eeh_memcpy_fromio(void *dest, const
 356                                      volatile void __iomem *src,
 357                                      unsigned long n)
 358 {
 359         _memcpy_fromio(dest, src, n);
 360
 361         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 362          * were copied. Check all four bytes.
 363          */
 364         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 365                 eeh_check_failure(src, *((u32 *)(dest + n - 4)));
 366 }
 367
 368 /* in-string eeh macros */
 369 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 370                               int ns)
 371 {
 372         _insb(addr, buf, ns);
 373         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 374                 eeh_check_failure(addr, *(u8*)buf);
 375 }
 376
 377 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 378                               int ns)
 379 {
 380         _insw(addr, buf, ns);
 381         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 382                 eeh_check_failure(addr, *(u16*)buf);
 383 }
 384
 385 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 386                               int nl)
 387 {
 388         _insl(addr, buf, nl);
 389         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 390                 eeh_check_failure(addr, *(u32*)buf);
 391 }
 392
 393 #endif /* CONFIG_PPC64 */
 394 #endif /* __KERNEL__ */
 395 #endif /* _POWERPC_EEH_H */