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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / powerpc / include / asm / opal.h
blobc5cd72833d6e7f29daba00655296750b0c560b16
1 /*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_H
13 #define __OPAL_H
14
15 /****** Takeover interface ********/
16
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23 #ifndef __ASSEMBLY__
24
25 struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34 };
35
36 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
37
38 extern long opal_do_takeover(struct opal_takeover_args *args);
39
40 struct rtas_args;
41 extern int opal_enter_rtas(struct rtas_args *args,
42 unsigned long data,
43 unsigned long entry);
44
45 #endif /* __ASSEMBLY__ */
46
47 /****** OPAL APIs ******/
48
49 /* Return codes */
50 #define OPAL_SUCCESS 0
51 #define OPAL_PARAMETER -1
52 #define OPAL_BUSY -2
53 #define OPAL_PARTIAL -3
54 #define OPAL_CONSTRAINED -4
55 #define OPAL_CLOSED -5
56 #define OPAL_HARDWARE -6
57 #define OPAL_UNSUPPORTED -7
58 #define OPAL_PERMISSION -8
59 #define OPAL_NO_MEM -9
60 #define OPAL_RESOURCE -10
61 #define OPAL_INTERNAL_ERROR -11
62 #define OPAL_BUSY_EVENT -12
63 #define OPAL_HARDWARE_FROZEN -13
64
65 /* API Tokens (in r0) */
66 #define OPAL_CONSOLE_WRITE 1
67 #define OPAL_CONSOLE_READ 2
68 #define OPAL_RTC_READ 3
69 #define OPAL_RTC_WRITE 4
70 #define OPAL_CEC_POWER_DOWN 5
71 #define OPAL_CEC_REBOOT 6
72 #define OPAL_READ_NVRAM 7
73 #define OPAL_WRITE_NVRAM 8
74 #define OPAL_HANDLE_INTERRUPT 9
75 #define OPAL_POLL_EVENTS 10
76 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
77 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
78 #define OPAL_PCI_CONFIG_READ_BYTE 13
79 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
80 #define OPAL_PCI_CONFIG_READ_WORD 15
81 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
82 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
83 #define OPAL_PCI_CONFIG_WRITE_WORD 18
84 #define OPAL_SET_XIVE 19
85 #define OPAL_GET_XIVE 20
86 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
87 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
88 #define OPAL_PCI_EEH_FREEZE_STATUS 23
89 #define OPAL_PCI_SHPC 24
90 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
91 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
92 #define OPAL_PCI_PHB_MMIO_ENABLE 27
93 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
94 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
95 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
96 #define OPAL_PCI_SET_PE 31
97 #define OPAL_PCI_SET_PELTV 32
98 #define OPAL_PCI_SET_MVE 33
99 #define OPAL_PCI_SET_MVE_ENABLE 34
100 #define OPAL_PCI_GET_XIVE_REISSUE 35
101 #define OPAL_PCI_SET_XIVE_REISSUE 36
102 #define OPAL_PCI_SET_XIVE_PE 37
103 #define OPAL_GET_XIVE_SOURCE 38
104 #define OPAL_GET_MSI_32 39
105 #define OPAL_GET_MSI_64 40
106 #define OPAL_START_CPU 41
107 #define OPAL_QUERY_CPU_STATUS 42
108 #define OPAL_WRITE_OPPANEL 43
109 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111 #define OPAL_PCI_RESET 49
112 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
113 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
114 #define OPAL_PCI_FENCE_PHB 52
115 #define OPAL_PCI_REINIT 53
116 #define OPAL_PCI_MASK_PE_ERROR 54
117 #define OPAL_SET_SLOT_LED_STATUS 55
118 #define OPAL_GET_EPOW_STATUS 56
119 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
120 #define OPAL_RESERVED1 58
121 #define OPAL_RESERVED2 59
122 #define OPAL_PCI_NEXT_ERROR 60
123 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
124 #define OPAL_PCI_POLL 62
125 #define OPAL_PCI_MSI_EOI 63
126 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
127 #define OPAL_XSCOM_READ 65
128 #define OPAL_XSCOM_WRITE 66
129 #define OPAL_LPC_READ 67
130 #define OPAL_LPC_WRITE 68
131 #define OPAL_RETURN_CPU 69
132
133 #ifndef __ASSEMBLY__
134
135 /* Other enums */
136 enum OpalVendorApiTokens {
137 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
138 };
139
140 enum OpalFreezeState {
141 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
142 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
143 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
144 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
145 OPAL_EEH_STOPPED_RESET = 4,
146 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
147 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
148 };
149
150 enum OpalEehFreezeActionToken {
151 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
153 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
154 };
155
156 enum OpalPciStatusToken {
157 OPAL_EEH_NO_ERROR = 0,
158 OPAL_EEH_IOC_ERROR = 1,
159 OPAL_EEH_PHB_ERROR = 2,
160 OPAL_EEH_PE_ERROR = 3,
161 OPAL_EEH_PE_MMIO_ERROR = 4,
162 OPAL_EEH_PE_DMA_ERROR = 5
163 };
164
165 enum OpalPciErrorSeverity {
166 OPAL_EEH_SEV_NO_ERROR = 0,
167 OPAL_EEH_SEV_IOC_DEAD = 1,
168 OPAL_EEH_SEV_PHB_DEAD = 2,
169 OPAL_EEH_SEV_PHB_FENCED = 3,
170 OPAL_EEH_SEV_PE_ER = 4,
171 OPAL_EEH_SEV_INF = 5
172 };
173
174 enum OpalShpcAction {
175 OPAL_SHPC_GET_LINK_STATE = 0,
176 OPAL_SHPC_GET_SLOT_STATE = 1
177 };
178
179 enum OpalShpcLinkState {
180 OPAL_SHPC_LINK_DOWN = 0,
181 OPAL_SHPC_LINK_UP = 1
182 };
183
184 enum OpalMmioWindowType {
185 OPAL_M32_WINDOW_TYPE = 1,
186 OPAL_M64_WINDOW_TYPE = 2,
187 OPAL_IO_WINDOW_TYPE = 3
188 };
189
190 enum OpalShpcSlotState {
191 OPAL_SHPC_DEV_NOT_PRESENT = 0,
192 OPAL_SHPC_DEV_PRESENT = 1
193 };
194
195 enum OpalExceptionHandler {
196 OPAL_MACHINE_CHECK_HANDLER = 1,
197 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
198 OPAL_SOFTPATCH_HANDLER = 3
199 };
200
201 enum OpalPendingState {
202 OPAL_EVENT_OPAL_INTERNAL = 0x1,
203 OPAL_EVENT_NVRAM = 0x2,
204 OPAL_EVENT_RTC = 0x4,
205 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
206 OPAL_EVENT_CONSOLE_INPUT = 0x10,
207 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
208 OPAL_EVENT_ERROR_LOG = 0x40,
209 OPAL_EVENT_EPOW = 0x80,
210 OPAL_EVENT_LED_STATUS = 0x100,
211 OPAL_EVENT_PCI_ERROR = 0x200
212 };
213
214 /* Machine check related definitions */
215 enum OpalMCE_Version {
216 OpalMCE_V1 = 1,
217 };
218
219 enum OpalMCE_Severity {
220 OpalMCE_SEV_NO_ERROR = 0,
221 OpalMCE_SEV_WARNING = 1,
222 OpalMCE_SEV_ERROR_SYNC = 2,
223 OpalMCE_SEV_FATAL = 3,
224 };
225
226 enum OpalMCE_Disposition {
227 OpalMCE_DISPOSITION_RECOVERED = 0,
228 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
229 };
230
231 enum OpalMCE_Initiator {
232 OpalMCE_INITIATOR_UNKNOWN = 0,
233 OpalMCE_INITIATOR_CPU = 1,
234 };
235
236 enum OpalMCE_ErrorType {
237 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
238 OpalMCE_ERROR_TYPE_UE = 1,
239 OpalMCE_ERROR_TYPE_SLB = 2,
240 OpalMCE_ERROR_TYPE_ERAT = 3,
241 OpalMCE_ERROR_TYPE_TLB = 4,
242 };
243
244 enum OpalMCE_UeErrorType {
245 OpalMCE_UE_ERROR_INDETERMINATE = 0,
246 OpalMCE_UE_ERROR_IFETCH = 1,
247 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
248 OpalMCE_UE_ERROR_LOAD_STORE = 3,
249 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
250 };
251
252 enum OpalMCE_SlbErrorType {
253 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
254 OpalMCE_SLB_ERROR_PARITY = 1,
255 OpalMCE_SLB_ERROR_MULTIHIT = 2,
256 };
257
258 enum OpalMCE_EratErrorType {
259 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
260 OpalMCE_ERAT_ERROR_PARITY = 1,
261 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
262 };
263
264 enum OpalMCE_TlbErrorType {
265 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
266 OpalMCE_TLB_ERROR_PARITY = 1,
267 OpalMCE_TLB_ERROR_MULTIHIT = 2,
268 };
269
270 enum OpalThreadStatus {
271 OPAL_THREAD_INACTIVE = 0x0,
272 OPAL_THREAD_STARTED = 0x1,
273 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
274 };
275
276 enum OpalPciBusCompare {
277 OpalPciBusAny = 0, /* Any bus number match */
278 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
279 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
280 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
281 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
282 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
283 OpalPciBusAll = 7, /* Match bus number exactly */
284 };
285
286 enum OpalDeviceCompare {
287 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
288 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
289 };
290
291 enum OpalFuncCompare {
292 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
293 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
294 };
295
296 enum OpalPeAction {
297 OPAL_UNMAP_PE = 0,
298 OPAL_MAP_PE = 1
299 };
300
301 enum OpalPeltvAction {
302 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
303 OPAL_ADD_PE_TO_DOMAIN = 1
304 };
305
306 enum OpalMveEnableAction {
307 OPAL_DISABLE_MVE = 0,
308 OPAL_ENABLE_MVE = 1
309 };
310
311 enum OpalPciResetAndReinitScope {
312 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
313 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
314 OPAL_PCI_IODA_TABLE_RESET = 6,
315 };
316
317 enum OpalPciResetState {
318 OPAL_DEASSERT_RESET = 0,
319 OPAL_ASSERT_RESET = 1
320 };
321
322 enum OpalPciMaskAction {
323 OPAL_UNMASK_ERROR_TYPE = 0,
324 OPAL_MASK_ERROR_TYPE = 1
325 };
326
327 enum OpalSlotLedType {
328 OPAL_SLOT_LED_ID_TYPE = 0,
329 OPAL_SLOT_LED_FAULT_TYPE = 1
330 };
331
332 enum OpalLedAction {
333 OPAL_TURN_OFF_LED = 0,
334 OPAL_TURN_ON_LED = 1,
335 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
336 };
337
338 enum OpalEpowStatus {
339 OPAL_EPOW_NONE = 0,
340 OPAL_EPOW_UPS = 1,
341 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
342 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
343 };
344
345 /*
346 * Address cycle types for LPC accesses. These also correspond
347 * to the content of the first cell of the "reg" property for
348 * device nodes on the LPC bus
349 */
350 enum OpalLPCAddressType {
351 OPAL_LPC_MEM = 0,
352 OPAL_LPC_IO = 1,
353 OPAL_LPC_FW = 2,
354 };
355
356 struct opal_machine_check_event {
357 enum OpalMCE_Version version:8; /* 0x00 */
358 uint8_t in_use; /* 0x01 */
359 enum OpalMCE_Severity severity:8; /* 0x02 */
360 enum OpalMCE_Initiator initiator:8; /* 0x03 */
361 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
362 enum OpalMCE_Disposition disposition:8; /* 0x05 */
363 uint8_t reserved_1[2]; /* 0x06 */
364 uint64_t gpr3; /* 0x08 */
365 uint64_t srr0; /* 0x10 */
366 uint64_t srr1; /* 0x18 */
367 union { /* 0x20 */
368 struct {
369 enum OpalMCE_UeErrorType ue_error_type:8;
370 uint8_t effective_address_provided;
371 uint8_t physical_address_provided;
372 uint8_t reserved_1[5];
373 uint64_t effective_address;
374 uint64_t physical_address;
375 uint8_t reserved_2[8];
376 } ue_error;
377
378 struct {
379 enum OpalMCE_SlbErrorType slb_error_type:8;
380 uint8_t effective_address_provided;
381 uint8_t reserved_1[6];
382 uint64_t effective_address;
383 uint8_t reserved_2[16];
384 } slb_error;
385
386 struct {
387 enum OpalMCE_EratErrorType erat_error_type:8;
388 uint8_t effective_address_provided;
389 uint8_t reserved_1[6];
390 uint64_t effective_address;
391 uint8_t reserved_2[16];
392 } erat_error;
393
394 struct {
395 enum OpalMCE_TlbErrorType tlb_error_type:8;
396 uint8_t effective_address_provided;
397 uint8_t reserved_1[6];
398 uint64_t effective_address;
399 uint8_t reserved_2[16];
400 } tlb_error;
401 } u;
402 };
403
404 enum {
405 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
406 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
407 OPAL_P7IOC_DIAG_TYPE_BI = 2,
408 OPAL_P7IOC_DIAG_TYPE_CI = 3,
409 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
410 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
411 OPAL_P7IOC_DIAG_TYPE_LAST = 6
412 };
413
414 struct OpalIoP7IOCErrorData {
415 uint16_t type;
416
417 /* GEM */
418 uint64_t gemXfir;
419 uint64_t gemRfir;
420 uint64_t gemRirqfir;
421 uint64_t gemMask;
422 uint64_t gemRwof;
423
424 /* LEM */
425 uint64_t lemFir;
426 uint64_t lemErrMask;
427 uint64_t lemAction0;
428 uint64_t lemAction1;
429 uint64_t lemWof;
430
431 union {
432 struct OpalIoP7IOCRgcErrorData {
433 uint64_t rgcStatus; /* 3E1C10 */
434 uint64_t rgcLdcp; /* 3E1C18 */
435 }rgc;
436 struct OpalIoP7IOCBiErrorData {
437 uint64_t biLdcp0; /* 3C0100, 3C0118 */
438 uint64_t biLdcp1; /* 3C0108, 3C0120 */
439 uint64_t biLdcp2; /* 3C0110, 3C0128 */
440 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
441
442 uint8_t biDownbound; /* BI Downbound or Upbound */
443 }bi;
444 struct OpalIoP7IOCCiErrorData {
445 uint64_t ciPortStatus; /* 3Dn008 */
446 uint64_t ciPortLdcp; /* 3Dn010 */
447
448 uint8_t ciPort; /* Index of CI port: 0/1 */
449 }ci;
450 };
451 };
452
453 /**
454 * This structure defines the overlay which will be used to store PHB error
455 * data upon request.
456 */
457 enum {
458 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
459 };
460
461 enum {
462 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
463 };
464
465 enum {
466 OPAL_P7IOC_NUM_PEST_REGS = 128,
467 };
468
469 struct OpalIoPhbErrorCommon {
470 uint32_t version;
471 uint32_t ioType;
472 uint32_t len;
473 };
474
475 struct OpalIoP7IOCPhbErrorData {
476 struct OpalIoPhbErrorCommon common;
477
478 uint32_t brdgCtl;
479
480 // P7IOC utl regs
481 uint32_t portStatusReg;
482 uint32_t rootCmplxStatus;
483 uint32_t busAgentStatus;
484
485 // P7IOC cfg regs
486 uint32_t deviceStatus;
487 uint32_t slotStatus;
488 uint32_t linkStatus;
489 uint32_t devCmdStatus;
490 uint32_t devSecStatus;
491
492 // cfg AER regs
493 uint32_t rootErrorStatus;
494 uint32_t uncorrErrorStatus;
495 uint32_t corrErrorStatus;
496 uint32_t tlpHdr1;
497 uint32_t tlpHdr2;
498 uint32_t tlpHdr3;
499 uint32_t tlpHdr4;
500 uint32_t sourceId;
501
502 uint32_t rsv3;
503
504 // Record data about the call to allocate a buffer.
505 uint64_t errorClass;
506 uint64_t correlator;
507
508 //P7IOC MMIO Error Regs
509 uint64_t p7iocPlssr; // n120
510 uint64_t p7iocCsr; // n110
511 uint64_t lemFir; // nC00
512 uint64_t lemErrorMask; // nC18
513 uint64_t lemWOF; // nC40
514 uint64_t phbErrorStatus; // nC80
515 uint64_t phbFirstErrorStatus; // nC88
516 uint64_t phbErrorLog0; // nCC0
517 uint64_t phbErrorLog1; // nCC8
518 uint64_t mmioErrorStatus; // nD00
519 uint64_t mmioFirstErrorStatus; // nD08
520 uint64_t mmioErrorLog0; // nD40
521 uint64_t mmioErrorLog1; // nD48
522 uint64_t dma0ErrorStatus; // nD80
523 uint64_t dma0FirstErrorStatus; // nD88
524 uint64_t dma0ErrorLog0; // nDC0
525 uint64_t dma0ErrorLog1; // nDC8
526 uint64_t dma1ErrorStatus; // nE00
527 uint64_t dma1FirstErrorStatus; // nE08
528 uint64_t dma1ErrorLog0; // nE40
529 uint64_t dma1ErrorLog1; // nE48
530 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
531 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
532 };
533
534 typedef struct oppanel_line {
535 const char * line;
536 uint64_t line_len;
537 } oppanel_line_t;
538
539 /* API functions */
540 int64_t opal_console_write(int64_t term_number, int64_t *length,
541 const uint8_t *buffer);
542 int64_t opal_console_read(int64_t term_number, int64_t *length,
543 uint8_t *buffer);
544 int64_t opal_console_write_buffer_space(int64_t term_number,
545 int64_t *length);
546 int64_t opal_rtc_read(uint32_t *year_month_day,
547 uint64_t *hour_minute_second_millisecond);
548 int64_t opal_rtc_write(uint32_t year_month_day,
549 uint64_t hour_minute_second_millisecond);
550 int64_t opal_cec_power_down(uint64_t request);
551 int64_t opal_cec_reboot(void);
552 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
553 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
554 int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
555 int64_t opal_poll_events(uint64_t *outstanding_event_mask);
556 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
557 uint64_t tce_mem_size);
558 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
559 uint64_t tce_mem_size);
560 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
561 uint64_t offset, uint8_t *data);
562 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
563 uint64_t offset, uint16_t *data);
564 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
565 uint64_t offset, uint32_t *data);
566 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
567 uint64_t offset, uint8_t data);
568 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
569 uint64_t offset, uint16_t data);
570 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
571 uint64_t offset, uint32_t data);
572 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
573 int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
574 int64_t opal_register_exception_handler(uint64_t opal_exception,
575 uint64_t handler_address,
576 uint64_t glue_cache_line);
577 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
578 uint8_t *freeze_state,
579 uint16_t *pci_error_type,
580 uint64_t *phb_status);
581 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
582 uint64_t eeh_action_token);
583 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
584
585
586
587 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
588 uint16_t window_num, uint16_t enable);
589 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
590 uint16_t window_num,
591 uint64_t starting_real_address,
592 uint64_t starting_pci_address,
593 uint16_t segment_size);
594 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
595 uint16_t window_type, uint16_t window_num,
596 uint16_t segment_num);
597 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
598 uint64_t ivt_addr, uint64_t ivt_len,
599 uint64_t reject_array_addr,
600 uint64_t peltv_addr);
601 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
602 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
603 uint8_t pe_action);
604 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
605 uint8_t state);
606 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
607 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
608 uint32_t state);
609 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
610 uint8_t *p_bit, uint8_t *q_bit);
611 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
612 uint8_t p_bit, uint8_t q_bit);
613 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
614 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
615 uint32_t xive_num);
616 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
617 int32_t *interrupt_source_number);
618 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
619 uint8_t msi_range, uint32_t *msi_address,
620 uint32_t *message_data);
621 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
622 uint32_t xive_num, uint8_t msi_range,
623 uint64_t *msi_address, uint32_t *message_data);
624 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
625 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
626 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
627 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
628 uint16_t tce_levels, uint64_t tce_table_addr,
629 uint64_t tce_table_size, uint64_t tce_page_size);
630 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
631 uint16_t dma_window_number, uint64_t pci_start_addr,
632 uint64_t pci_mem_size);
633 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
634
635 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
636 uint64_t diag_buffer_len);
637 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
638 uint64_t diag_buffer_len);
639 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
640 uint64_t diag_buffer_len);
641 int64_t opal_pci_fence_phb(uint64_t phb_id);
642 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
643 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
644 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
645 int64_t opal_get_epow_status(uint64_t *status);
646 int64_t opal_set_system_attention_led(uint8_t led_action);
647 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
648 uint16_t *pci_error_type, uint16_t *severity);
649 int64_t opal_pci_poll(uint64_t phb_id);
650 int64_t opal_return_cpu(void);
651
652 int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
653 int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
654
655 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
656 uint32_t addr, uint32_t data, uint32_t sz);
657 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
658 uint32_t addr, uint32_t *data, uint32_t sz);
659
660 /* Internal functions */
661 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
662
663 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
664 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
665
666 extern void hvc_opal_init_early(void);
667
668 /* Internal functions */
669 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
670 int depth, void *data);
671
672 extern int opal_notifier_register(struct notifier_block *nb);
673 extern void opal_notifier_enable(void);
674 extern void opal_notifier_disable(void);
675 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
676
677 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
678 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
679
680 extern void hvc_opal_init_early(void);
681
682 struct rtc_time;
683 extern int opal_set_rtc_time(struct rtc_time *tm);
684 extern void opal_get_rtc_time(struct rtc_time *tm);
685 extern unsigned long opal_get_boot_time(void);
686 extern void opal_nvram_init(void);
687
688 extern int opal_machine_check(struct pt_regs *regs);
689
690 extern void opal_shutdown(void);
691
692 extern void opal_lpc_init(void);
693
694 #endif /* __ASSEMBLY__ */
695
696 #endif /* __OPAL_H */
Linux with added FPC-III support