arch/powerpc/include/asm/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * Simple spin lock operations.
   7  *
   8  * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   9  * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  10  * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
  11  *      Rework to support virtual processors
  12  *
  13  * Type of int is used as a full 64b word is not necessary.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  *
  20  * (the type definitions are in asm/spinlock_types.h)
  21  */
  22 #include <linux/irqflags.h>
  23 #ifdef CONFIG_PPC64
  24 #include <asm/paca.h>
  25 #include <asm/hvcall.h>
  26 #endif
  27 #include <asm/asm-compat.h>
  28 #include <asm/synch.h>
  29 #include <asm/ppc-opcode.h>
  30
  31 #define arch_spin_is_locked(x)          ((x)->slock != 0)
  32
  33 #ifdef CONFIG_PPC64
  34 /* use 0x800000yy when locked, where yy == CPU number */
  35 #ifdef __BIG_ENDIAN__
  36 #define LOCK_TOKEN      (*(u32 *)(&get_paca()->lock_token))
  37 #else
  38 #define LOCK_TOKEN      (*(u32 *)(&get_paca()->paca_index))
  39 #endif
  40 #else
  41 #define LOCK_TOKEN      1
  42 #endif
  43
  44 #if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
  45 #define CLEAR_IO_SYNC   (get_paca()->io_sync = 0)
  46 #define SYNC_IO         do {                                            \
  47                                 if (unlikely(get_paca()->io_sync)) {    \
  48                                         mb();                           \
  49                                         get_paca()->io_sync = 0;        \
  50                                 }                                       \
  51                         } while (0)
  52 #else
  53 #define CLEAR_IO_SYNC
  54 #define SYNC_IO
  55 #endif
  56
  57 /*
  58  * This returns the old value in the lock, so we succeeded
  59  * in getting the lock if the return value is 0.
  60  */
  61 static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
  62 {
  63         unsigned long tmp, token;
  64
  65         token = LOCK_TOKEN;
  66         __asm__ __volatile__(
  67 "1:     " PPC_LWARX(%0,0,%2,1) "\n\
  68         cmpwi           0,%0,0\n\
  69         bne-            2f\n\
  70         stwcx.          %1,0,%2\n\
  71         bne-            1b\n"
  72         PPC_ACQUIRE_BARRIER
  73 "2:"
  74         : "=&r" (tmp)
  75         : "r" (token), "r" (&lock->slock)
  76         : "cr0", "memory");
  77
  78         return tmp;
  79 }
  80
  81 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  82 {
  83         CLEAR_IO_SYNC;
  84         return __arch_spin_trylock(lock) == 0;
  85 }
  86
  87 /*
  88  * On a system with shared processors (that is, where a physical
  89  * processor is multiplexed between several virtual processors),
  90  * there is no point spinning on a lock if the holder of the lock
  91  * isn't currently scheduled on a physical processor.  Instead
  92  * we detect this situation and ask the hypervisor to give the
  93  * rest of our timeslice to the lock holder.
  94  *
  95  * So that we can tell which virtual processor is holding a lock,
  96  * we put 0x80000000 | smp_processor_id() in the lock when it is
  97  * held.  Conveniently, we have a word in the paca that holds this
  98  * value.
  99  */
 100
 101 #if defined(CONFIG_PPC_SPLPAR)
 102 /* We only yield to the hypervisor if we are in shared processor mode */
 103 #define SHARED_PROCESSOR (lppaca_shared_proc(local_paca->lppaca_ptr))
 104 extern void __spin_yield(arch_spinlock_t *lock);
 105 extern void __rw_yield(arch_rwlock_t *lock);
 106 #else /* SPLPAR */
 107 #define __spin_yield(x) barrier()
 108 #define __rw_yield(x)   barrier()
 109 #define SHARED_PROCESSOR        0
 110 #endif
 111
 112 static inline void arch_spin_lock(arch_spinlock_t *lock)
 113 {
 114         CLEAR_IO_SYNC;
 115         while (1) {
 116                 if (likely(__arch_spin_trylock(lock) == 0))
 117                         break;
 118                 do {
 119                         HMT_low();
 120                         if (SHARED_PROCESSOR)
 121                                 __spin_yield(lock);
 122                 } while (unlikely(lock->slock != 0));
 123                 HMT_medium();
 124         }
 125 }
 126
 127 static inline
 128 void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 129 {
 130         unsigned long flags_dis;
 131
 132         CLEAR_IO_SYNC;
 133         while (1) {
 134                 if (likely(__arch_spin_trylock(lock) == 0))
 135                         break;
 136                 local_save_flags(flags_dis);
 137                 local_irq_restore(flags);
 138                 do {
 139                         HMT_low();
 140                         if (SHARED_PROCESSOR)
 141                                 __spin_yield(lock);
 142                 } while (unlikely(lock->slock != 0));
 143                 HMT_medium();
 144                 local_irq_restore(flags_dis);
 145         }
 146 }
 147
 148 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 149 {
 150         SYNC_IO;
 151         __asm__ __volatile__("# arch_spin_unlock\n\t"
 152                                 PPC_RELEASE_BARRIER: : :"memory");
 153         lock->slock = 0;
 154 }
 155
 156 #ifdef CONFIG_PPC64
 157 extern void arch_spin_unlock_wait(arch_spinlock_t *lock);
 158 #else
 159 #define arch_spin_unlock_wait(lock) \
 160         do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 161 #endif
 162
 163 /*
 164  * Read-write spinlocks, allowing multiple readers
 165  * but only one writer.
 166  *
 167  * NOTE! it is quite common to have readers in interrupts
 168  * but no interrupt writers. For those circumstances we
 169  * can "mix" irq-safe locks - any writer needs to get a
 170  * irq-safe write-lock, but readers can get non-irqsafe
 171  * read-locks.
 172  */
 173
 174 #define arch_read_can_lock(rw)          ((rw)->lock >= 0)
 175 #define arch_write_can_lock(rw) (!(rw)->lock)
 176
 177 #ifdef CONFIG_PPC64
 178 #define __DO_SIGN_EXTEND        "extsw  %0,%0\n"
 179 #define WRLOCK_TOKEN            LOCK_TOKEN      /* it's negative */
 180 #else
 181 #define __DO_SIGN_EXTEND
 182 #define WRLOCK_TOKEN            (-1)
 183 #endif
 184
 185 /*
 186  * This returns the old value in the lock + 1,
 187  * so we got a read lock if the return value is > 0.
 188  */
 189 static inline long __arch_read_trylock(arch_rwlock_t *rw)
 190 {
 191         long tmp;
 192
 193         __asm__ __volatile__(
 194 "1:     " PPC_LWARX(%0,0,%1,1) "\n"
 195         __DO_SIGN_EXTEND
 196 "       addic.          %0,%0,1\n\
 197         ble-            2f\n"
 198         PPC405_ERR77(0,%1)
 199 "       stwcx.          %0,0,%1\n\
 200         bne-            1b\n"
 201         PPC_ACQUIRE_BARRIER
 202 "2:"    : "=&r" (tmp)
 203         : "r" (&rw->lock)
 204         : "cr0", "xer", "memory");
 205
 206         return tmp;
 207 }
 208
 209 /*
 210  * This returns the old value in the lock,
 211  * so we got the write lock if the return value is 0.
 212  */
 213 static inline long __arch_write_trylock(arch_rwlock_t *rw)
 214 {
 215         long tmp, token;
 216
 217         token = WRLOCK_TOKEN;
 218         __asm__ __volatile__(
 219 "1:     " PPC_LWARX(%0,0,%2,1) "\n\
 220         cmpwi           0,%0,0\n\
 221         bne-            2f\n"
 222         PPC405_ERR77(0,%1)
 223 "       stwcx.          %1,0,%2\n\
 224         bne-            1b\n"
 225         PPC_ACQUIRE_BARRIER
 226 "2:"    : "=&r" (tmp)
 227         : "r" (token), "r" (&rw->lock)
 228         : "cr0", "memory");
 229
 230         return tmp;
 231 }
 232
 233 static inline void arch_read_lock(arch_rwlock_t *rw)
 234 {
 235         while (1) {
 236                 if (likely(__arch_read_trylock(rw) > 0))
 237                         break;
 238                 do {
 239                         HMT_low();
 240                         if (SHARED_PROCESSOR)
 241                                 __rw_yield(rw);
 242                 } while (unlikely(rw->lock < 0));
 243                 HMT_medium();
 244         }
 245 }
 246
 247 static inline void arch_write_lock(arch_rwlock_t *rw)
 248 {
 249         while (1) {
 250                 if (likely(__arch_write_trylock(rw) == 0))
 251                         break;
 252                 do {
 253                         HMT_low();
 254                         if (SHARED_PROCESSOR)
 255                                 __rw_yield(rw);
 256                 } while (unlikely(rw->lock != 0));
 257                 HMT_medium();
 258         }
 259 }
 260
 261 static inline int arch_read_trylock(arch_rwlock_t *rw)
 262 {
 263         return __arch_read_trylock(rw) > 0;
 264 }
 265
 266 static inline int arch_write_trylock(arch_rwlock_t *rw)
 267 {
 268         return __arch_write_trylock(rw) == 0;
 269 }
 270
 271 static inline void arch_read_unlock(arch_rwlock_t *rw)
 272 {
 273         long tmp;
 274
 275         __asm__ __volatile__(
 276         "# read_unlock\n\t"
 277         PPC_RELEASE_BARRIER
 278 "1:     lwarx           %0,0,%1\n\
 279         addic           %0,%0,-1\n"
 280         PPC405_ERR77(0,%1)
 281 "       stwcx.          %0,0,%1\n\
 282         bne-            1b"
 283         : "=&r"(tmp)
 284         : "r"(&rw->lock)
 285         : "cr0", "xer", "memory");
 286 }
 287
 288 static inline void arch_write_unlock(arch_rwlock_t *rw)
 289 {
 290         __asm__ __volatile__("# write_unlock\n\t"
 291                                 PPC_RELEASE_BARRIER: : :"memory");
 292         rw->lock = 0;
 293 }
 294
 295 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 296 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 297
 298 #define arch_spin_relax(lock)   __spin_yield(lock)
 299 #define arch_read_relax(lock)   __rw_yield(lock)
 300 #define arch_write_relax(lock)  __rw_yield(lock)
 301
 302 #endif /* __KERNEL__ */
 303 #endif /* __ASM_SPINLOCK_H */