2 * The file intends to implement PE based on the information from
3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
4 * All the PEs should be organized as hierarchy tree. The first level
5 * of the tree will be associated to existing PHBs since the particular
6 * PE is only meaningful in one PHB domain.
8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/delay.h>
26 #include <linux/export.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/string.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/ppc-pci.h>
36 static LIST_HEAD(eeh_phb_pe
);
39 * eeh_pe_alloc - Allocate PE
40 * @phb: PCI controller
43 * Allocate PE instance dynamically.
45 static struct eeh_pe
*eeh_pe_alloc(struct pci_controller
*phb
, int type
)
50 pe
= kzalloc(sizeof(struct eeh_pe
), GFP_KERNEL
);
53 /* Initialize PHB PE */
56 INIT_LIST_HEAD(&pe
->child_list
);
57 INIT_LIST_HEAD(&pe
->child
);
58 INIT_LIST_HEAD(&pe
->edevs
);
64 * eeh_phb_pe_create - Create PHB PE
65 * @phb: PCI controller
67 * The function should be called while the PHB is detected during
68 * system boot or PCI hotplug in order to create PHB PE.
70 int eeh_phb_pe_create(struct pci_controller
*phb
)
75 pe
= eeh_pe_alloc(phb
, EEH_PE_PHB
);
77 pr_err("%s: out of memory!\n", __func__
);
81 /* Put it into the list */
82 list_add_tail(&pe
->child
, &eeh_phb_pe
);
84 pr_debug("EEH: Add PE for PHB#%d\n", phb
->global_number
);
90 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
91 * @phb: PCI controller
93 * The overall PEs form hierarchy tree. The first layer of the
94 * hierarchy tree is composed of PHB PEs. The function is used
95 * to retrieve the corresponding PHB PE according to the given PHB.
97 struct eeh_pe
*eeh_phb_pe_get(struct pci_controller
*phb
)
101 list_for_each_entry(pe
, &eeh_phb_pe
, child
) {
103 * Actually, we needn't check the type since
104 * the PE for PHB has been determined when that
107 if ((pe
->type
& EEH_PE_PHB
) && pe
->phb
== phb
)
115 * eeh_pe_next - Retrieve the next PE in the tree
119 * The function is used to retrieve the next PE in the
122 static struct eeh_pe
*eeh_pe_next(struct eeh_pe
*pe
,
125 struct list_head
*next
= pe
->child_list
.next
;
127 if (next
== &pe
->child_list
) {
131 next
= pe
->child
.next
;
132 if (next
!= &pe
->parent
->child_list
)
138 return list_entry(next
, struct eeh_pe
, child
);
142 * eeh_pe_traverse - Traverse PEs in the specified PHB
145 * @flag: extra parameter to callback
147 * The function is used to traverse the specified PE and its
148 * child PEs. The traversing is to be terminated once the
149 * callback returns something other than NULL, or no more PEs
152 void *eeh_pe_traverse(struct eeh_pe
*root
,
153 eeh_traverse_func fn
, void *flag
)
158 for (pe
= root
; pe
; pe
= eeh_pe_next(pe
, root
)) {
167 * eeh_pe_dev_traverse - Traverse the devices from the PE
169 * @fn: function callback
170 * @flag: extra parameter to callback
172 * The function is used to traverse the devices of the specified
173 * PE and its child PEs.
175 void *eeh_pe_dev_traverse(struct eeh_pe
*root
,
176 eeh_traverse_func fn
, void *flag
)
179 struct eeh_dev
*edev
, *tmp
;
183 pr_warning("%s: Invalid PE %p\n", __func__
, root
);
187 /* Traverse root PE */
188 for (pe
= root
; pe
; pe
= eeh_pe_next(pe
, root
)) {
189 eeh_pe_for_each_dev(pe
, edev
, tmp
) {
190 ret
= fn(edev
, flag
);
200 * __eeh_pe_get - Check the PE address
204 * For one particular PE, it can be identified by PE address
205 * or tranditional BDF address. BDF address is composed of
206 * Bus/Device/Function number. The extra data referred by flag
207 * indicates which type of address should be used.
209 static void *__eeh_pe_get(void *data
, void *flag
)
211 struct eeh_pe
*pe
= (struct eeh_pe
*)data
;
212 struct eeh_dev
*edev
= (struct eeh_dev
*)flag
;
214 /* Unexpected PHB PE */
215 if (pe
->type
& EEH_PE_PHB
)
218 /* We prefer PE address */
219 if (edev
->pe_config_addr
&&
220 (edev
->pe_config_addr
== pe
->addr
))
223 /* Try BDF address */
224 if (edev
->config_addr
&&
225 (edev
->config_addr
== pe
->config_addr
))
232 * eeh_pe_get - Search PE based on the given address
235 * Search the corresponding PE based on the specified address which
236 * is included in the eeh device. The function is used to check if
237 * the associated PE has been created against the PE address. It's
238 * notable that the PE address has 2 format: traditional PE address
239 * which is composed of PCI bus/device/function number, or unified
242 struct eeh_pe
*eeh_pe_get(struct eeh_dev
*edev
)
244 struct eeh_pe
*root
= eeh_phb_pe_get(edev
->phb
);
247 pe
= eeh_pe_traverse(root
, __eeh_pe_get
, edev
);
253 * eeh_pe_get_parent - Retrieve the parent PE
256 * The whole PEs existing in the system are organized as hierarchy
257 * tree. The function is used to retrieve the parent PE according
258 * to the parent EEH device.
260 static struct eeh_pe
*eeh_pe_get_parent(struct eeh_dev
*edev
)
262 struct device_node
*dn
;
263 struct eeh_dev
*parent
;
266 * It might have the case for the indirect parent
267 * EEH device already having associated PE, but
268 * the direct parent EEH device doesn't have yet.
270 dn
= edev
->dn
->parent
;
272 /* We're poking out of PCI territory */
273 if (!PCI_DN(dn
)) return NULL
;
275 parent
= of_node_to_eeh_dev(dn
);
276 /* We're poking out of PCI territory */
277 if (!parent
) return NULL
;
289 * eeh_add_to_parent_pe - Add EEH device to parent PE
292 * Add EEH device to the parent PE. If the parent PE already
293 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
294 * we have to create new PE to hold the EEH device and the new
295 * PE will be linked to its parent PE as well.
297 int eeh_add_to_parent_pe(struct eeh_dev
*edev
)
299 struct eeh_pe
*pe
, *parent
;
302 * Search the PE has been existing or not according
303 * to the PE address. If that has been existing, the
304 * PE should be composed of PCI bus and its subordinate
307 pe
= eeh_pe_get(edev
);
308 if (pe
&& !(pe
->type
& EEH_PE_INVALID
)) {
309 if (!edev
->pe_config_addr
) {
310 pr_err("%s: PE with addr 0x%x already exists\n",
311 __func__
, edev
->config_addr
);
315 /* Mark the PE as type of PCI bus */
316 pe
->type
= EEH_PE_BUS
;
319 /* Put the edev to PE */
320 list_add_tail(&edev
->list
, &pe
->edevs
);
321 pr_debug("EEH: Add %s to Bus PE#%x\n",
322 edev
->dn
->full_name
, pe
->addr
);
325 } else if (pe
&& (pe
->type
& EEH_PE_INVALID
)) {
326 list_add_tail(&edev
->list
, &pe
->edevs
);
329 * We're running to here because of PCI hotplug caused by
330 * EEH recovery. We need clear EEH_PE_INVALID until the top.
334 if (!(parent
->type
& EEH_PE_INVALID
))
336 parent
->type
&= ~(EEH_PE_INVALID
| EEH_PE_KEEP
);
337 parent
= parent
->parent
;
339 pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
340 edev
->dn
->full_name
, pe
->addr
, pe
->parent
->addr
);
345 /* Create a new EEH PE */
346 pe
= eeh_pe_alloc(edev
->phb
, EEH_PE_DEVICE
);
348 pr_err("%s: out of memory!\n", __func__
);
351 pe
->addr
= edev
->pe_config_addr
;
352 pe
->config_addr
= edev
->config_addr
;
355 * While doing PE reset, we probably hot-reset the
356 * upstream bridge. However, the PCI devices including
357 * the associated EEH devices might be removed when EEH
358 * core is doing recovery. So that won't safe to retrieve
359 * the bridge through downstream EEH device. We have to
360 * trace the parent PCI bus, then the upstream bridge.
362 if (eeh_probe_mode_dev())
363 pe
->bus
= eeh_dev_to_pci_dev(edev
)->bus
;
366 * Put the new EEH PE into hierarchy tree. If the parent
367 * can't be found, the newly created PE will be attached
368 * to PHB directly. Otherwise, we have to associate the
369 * PE with its parent.
371 parent
= eeh_pe_get_parent(edev
);
373 parent
= eeh_phb_pe_get(edev
->phb
);
375 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
376 __func__
, edev
->phb
->global_number
);
385 * Put the newly created PE into the child list and
386 * link the EEH device accordingly.
388 list_add_tail(&pe
->child
, &parent
->child_list
);
389 list_add_tail(&edev
->list
, &pe
->edevs
);
391 pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
392 edev
->dn
->full_name
, pe
->addr
, pe
->parent
->addr
);
398 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
401 * The PE hierarchy tree might be changed when doing PCI hotplug.
402 * Also, the PCI devices or buses could be removed from the system
403 * during EEH recovery. So we have to call the function remove the
404 * corresponding PE accordingly if necessary.
406 int eeh_rmv_from_parent_pe(struct eeh_dev
*edev
)
408 struct eeh_pe
*pe
, *parent
, *child
;
412 pr_debug("%s: No PE found for EEH device %s\n",
413 __func__
, edev
->dn
->full_name
);
417 /* Remove the EEH device */
420 list_del(&edev
->list
);
423 * Check if the parent PE includes any EEH devices.
424 * If not, we should delete that. Also, we should
425 * delete the parent PE if it doesn't have associated
426 * child PEs and EEH devices.
430 if (pe
->type
& EEH_PE_PHB
)
433 if (!(pe
->state
& EEH_PE_KEEP
)) {
434 if (list_empty(&pe
->edevs
) &&
435 list_empty(&pe
->child_list
)) {
436 list_del(&pe
->child
);
442 if (list_empty(&pe
->edevs
)) {
444 list_for_each_entry(child
, &pe
->child_list
, child
) {
445 if (!(child
->type
& EEH_PE_INVALID
)) {
452 pe
->type
|= EEH_PE_INVALID
;
465 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
468 * We have time stamp for each PE to trace its time of getting
469 * frozen in last hour. The function should be called to update
470 * the time stamp on first error of the specific PE. On the other
471 * handle, we needn't account for errors happened in last hour.
473 void eeh_pe_update_time_stamp(struct eeh_pe
*pe
)
475 struct timeval tstamp
;
479 if (pe
->freeze_count
<= 0) {
480 pe
->freeze_count
= 0;
481 do_gettimeofday(&pe
->tstamp
);
483 do_gettimeofday(&tstamp
);
484 if (tstamp
.tv_sec
- pe
->tstamp
.tv_sec
> 3600) {
486 pe
->freeze_count
= 0;
492 * __eeh_pe_state_mark - Mark the state for the PE
496 * The function is used to mark the indicated state for the given
497 * PE. Also, the associated PCI devices will be put into IO frozen
500 static void *__eeh_pe_state_mark(void *data
, void *flag
)
502 struct eeh_pe
*pe
= (struct eeh_pe
*)data
;
503 int state
= *((int *)flag
);
504 struct eeh_dev
*edev
, *tmp
;
505 struct pci_dev
*pdev
;
508 * Mark the PE with the indicated state. Also,
509 * the associated PCI device will be put into
510 * I/O frozen state to avoid I/O accesses from
511 * the PCI device driver.
514 eeh_pe_for_each_dev(pe
, edev
, tmp
) {
515 pdev
= eeh_dev_to_pci_dev(edev
);
517 pdev
->error_state
= pci_channel_io_frozen
;
524 * eeh_pe_state_mark - Mark specified state for PE and its associated device
527 * EEH error affects the current PE and its child PEs. The function
528 * is used to mark appropriate state for the affected PEs and the
529 * associated devices.
531 void eeh_pe_state_mark(struct eeh_pe
*pe
, int state
)
533 eeh_pe_traverse(pe
, __eeh_pe_state_mark
, &state
);
537 * __eeh_pe_state_clear - Clear state for the PE
541 * The function is used to clear the indicated state from the
542 * given PE. Besides, we also clear the check count of the PE
545 static void *__eeh_pe_state_clear(void *data
, void *flag
)
547 struct eeh_pe
*pe
= (struct eeh_pe
*)data
;
548 int state
= *((int *)flag
);
557 * eeh_pe_state_clear - Clear state for the PE and its children
559 * @state: state to be cleared
561 * When the PE and its children has been recovered from error,
562 * we need clear the error state for that. The function is used
565 void eeh_pe_state_clear(struct eeh_pe
*pe
, int state
)
567 eeh_pe_traverse(pe
, __eeh_pe_state_clear
, &state
);
571 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
572 * buses assigned explicitly by firmware, and we probably have
573 * lost that after reset. So we have to delay the check until
574 * the PCI-CFG registers have been restored for the parent
577 * Don't use normal PCI-CFG accessors, which probably has been
578 * blocked on normal path during the stage. So we need utilize
579 * eeh operations, which is always permitted.
581 static void eeh_bridge_check_link(struct eeh_dev
*edev
,
582 struct device_node
*dn
)
589 * We only check root port and downstream ports of
592 if (!(edev
->mode
& (EEH_DEV_ROOT_PORT
| EEH_DEV_DS_PORT
)))
595 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
596 __func__
, edev
->phb
->global_number
,
597 edev
->config_addr
>> 8,
598 PCI_SLOT(edev
->config_addr
& 0xFF),
599 PCI_FUNC(edev
->config_addr
& 0xFF));
601 /* Check slot status */
602 cap
= edev
->pcie_cap
;
603 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_SLTSTA
, 2, &val
);
604 if (!(val
& PCI_EXP_SLTSTA_PDS
)) {
605 pr_debug(" No card in the slot (0x%04x) !\n", val
);
609 /* Check power status if we have the capability */
610 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_SLTCAP
, 2, &val
);
611 if (val
& PCI_EXP_SLTCAP_PCP
) {
612 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_SLTCTL
, 2, &val
);
613 if (val
& PCI_EXP_SLTCTL_PCC
) {
614 pr_debug(" In power-off state, power it on ...\n");
615 val
&= ~(PCI_EXP_SLTCTL_PCC
| PCI_EXP_SLTCTL_PIC
);
616 val
|= (0x0100 & PCI_EXP_SLTCTL_PIC
);
617 eeh_ops
->write_config(dn
, cap
+ PCI_EXP_SLTCTL
, 2, val
);
623 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_LNKCTL
, 2, &val
);
624 val
&= ~PCI_EXP_LNKCTL_LD
;
625 eeh_ops
->write_config(dn
, cap
+ PCI_EXP_LNKCTL
, 2, val
);
628 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_LNKCAP
, 4, &val
);
629 if (!(val
& PCI_EXP_LNKCAP_DLLLARC
)) {
630 pr_debug(" No link reporting capability (0x%08x) \n", val
);
635 /* Wait the link is up until timeout (5s) */
637 while (timeout
< 5000) {
641 eeh_ops
->read_config(dn
, cap
+ PCI_EXP_LNKSTA
, 2, &val
);
642 if (val
& PCI_EXP_LNKSTA_DLLLA
)
646 if (val
& PCI_EXP_LNKSTA_DLLLA
)
647 pr_debug(" Link up (%s)\n",
648 (val
& PCI_EXP_LNKSTA_CLS_2_5GB
) ? "2.5GB" : "5GB");
650 pr_debug(" Link not ready (0x%04x)\n", val
);
653 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
654 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
656 static void eeh_restore_bridge_bars(struct eeh_dev
*edev
,
657 struct device_node
*dn
)
662 * Device BARs: 0x10 - 0x18
663 * Bus numbers and windows: 0x18 - 0x30
665 for (i
= 4; i
< 13; i
++)
666 eeh_ops
->write_config(dn
, i
*4, 4, edev
->config_space
[i
]);
668 eeh_ops
->write_config(dn
, 14*4, 4, edev
->config_space
[14]);
670 /* Cache line & Latency timer: 0xC 0xD */
671 eeh_ops
->write_config(dn
, PCI_CACHE_LINE_SIZE
, 1,
672 SAVED_BYTE(PCI_CACHE_LINE_SIZE
));
673 eeh_ops
->write_config(dn
, PCI_LATENCY_TIMER
, 1,
674 SAVED_BYTE(PCI_LATENCY_TIMER
));
675 /* Max latency, min grant, interrupt ping and line: 0x3C */
676 eeh_ops
->write_config(dn
, 15*4, 4, edev
->config_space
[15]);
678 /* PCI Command: 0x4 */
679 eeh_ops
->write_config(dn
, PCI_COMMAND
, 4, edev
->config_space
[1]);
681 /* Check the PCIe link is ready */
682 eeh_bridge_check_link(edev
, dn
);
685 static void eeh_restore_device_bars(struct eeh_dev
*edev
,
686 struct device_node
*dn
)
691 for (i
= 4; i
< 10; i
++)
692 eeh_ops
->write_config(dn
, i
*4, 4, edev
->config_space
[i
]);
693 /* 12 == Expansion ROM Address */
694 eeh_ops
->write_config(dn
, 12*4, 4, edev
->config_space
[12]);
696 eeh_ops
->write_config(dn
, PCI_CACHE_LINE_SIZE
, 1,
697 SAVED_BYTE(PCI_CACHE_LINE_SIZE
));
698 eeh_ops
->write_config(dn
, PCI_LATENCY_TIMER
, 1,
699 SAVED_BYTE(PCI_LATENCY_TIMER
));
701 /* max latency, min grant, interrupt pin and line */
702 eeh_ops
->write_config(dn
, 15*4, 4, edev
->config_space
[15]);
705 * Restore PERR & SERR bits, some devices require it,
706 * don't touch the other command bits
708 eeh_ops
->read_config(dn
, PCI_COMMAND
, 4, &cmd
);
709 if (edev
->config_space
[1] & PCI_COMMAND_PARITY
)
710 cmd
|= PCI_COMMAND_PARITY
;
712 cmd
&= ~PCI_COMMAND_PARITY
;
713 if (edev
->config_space
[1] & PCI_COMMAND_SERR
)
714 cmd
|= PCI_COMMAND_SERR
;
716 cmd
&= ~PCI_COMMAND_SERR
;
717 eeh_ops
->write_config(dn
, PCI_COMMAND
, 4, cmd
);
721 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
725 * Loads the PCI configuration space base address registers,
726 * the expansion ROM base address, the latency timer, and etc.
727 * from the saved values in the device node.
729 static void *eeh_restore_one_device_bars(void *data
, void *flag
)
731 struct eeh_dev
*edev
= (struct eeh_dev
*)data
;
732 struct device_node
*dn
= eeh_dev_to_of_node(edev
);
734 /* Do special restore for bridges */
735 if (edev
->mode
& EEH_DEV_BRIDGE
)
736 eeh_restore_bridge_bars(edev
, dn
);
738 eeh_restore_device_bars(edev
, dn
);
744 * eeh_pe_restore_bars - Restore the PCI config space info
747 * This routine performs a recursive walk to the children
748 * of this device as well.
750 void eeh_pe_restore_bars(struct eeh_pe
*pe
)
753 * We needn't take the EEH lock since eeh_pe_dev_traverse()
756 eeh_pe_dev_traverse(pe
, eeh_restore_one_device_bars
, NULL
);
760 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
763 * Retrieve the PCI bus according to the given PE. Basically,
764 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
765 * primary PCI bus will be retrieved. The parent bus will be
766 * returned for BUS PE. However, we don't have associated PCI
769 struct pci_bus
*eeh_pe_bus_get(struct eeh_pe
*pe
)
771 struct pci_bus
*bus
= NULL
;
772 struct eeh_dev
*edev
;
773 struct pci_dev
*pdev
;
775 if (pe
->type
& EEH_PE_PHB
) {
777 } else if (pe
->type
& EEH_PE_BUS
||
778 pe
->type
& EEH_PE_DEVICE
) {
784 edev
= list_first_entry(&pe
->edevs
, struct eeh_dev
, list
);
785 pdev
= eeh_dev_to_pci_dev(edev
);