| blob | ace34137a501116511a8832d5b4fefdca2928447 |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * kexec bits:
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 */
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
34 #include <asm/bug.h>
35 #include <asm/ptrace.h>
37 .text
39 /*
40 * We store the saved ksp_limit in the unused part
41 * of the STACK_FRAME_OVERHEAD
42 */
43 _GLOBAL(call_do_softirq)
44 mflr r0
45 stw r0,4(r1)
46 lwz r10,THREAD+KSP_LIMIT(r2)
47 addi r11,r3,THREAD_INFO_GAP
48 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
49 mr r1,r3
50 stw r10,8(r1)
51 stw r11,THREAD+KSP_LIMIT(r2)
52 bl __do_softirq
53 lwz r10,8(r1)
54 lwz r1,0(r1)
55 lwz r0,4(r1)
56 stw r10,THREAD+KSP_LIMIT(r2)
57 mtlr r0
58 blr
60 /*
61 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
62 */
63 _GLOBAL(call_do_irq)
64 mflr r0
65 stw r0,4(r1)
66 lwz r10,THREAD+KSP_LIMIT(r2)
67 addi r11,r4,THREAD_INFO_GAP
68 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
69 mr r1,r4
70 stw r10,8(r1)
71 stw r11,THREAD+KSP_LIMIT(r2)
72 bl __do_irq
73 lwz r10,8(r1)
74 lwz r1,0(r1)
75 lwz r0,4(r1)
76 stw r10,THREAD+KSP_LIMIT(r2)
77 mtlr r0
78 blr
80 /*
81 * This returns the high 64 bits of the product of two 64-bit numbers.
82 */
83 _GLOBAL(mulhdu)
84 cmpwi r6,0
85 cmpwi cr1,r3,0
86 mr r10,r4
87 mulhwu r4,r4,r5
88 beq 1f
89 mulhwu r0,r10,r6
90 mullw r7,r10,r5
91 addc r7,r0,r7
92 addze r4,r4
93 1: beqlr cr1 /* all done if high part of A is 0 */
94 mr r10,r3
95 mullw r9,r3,r5
96 mulhwu r3,r3,r5
97 beq 2f
98 mullw r0,r10,r6
99 mulhwu r8,r10,r6
100 addc r7,r0,r7
101 adde r4,r4,r8
102 addze r3,r3
103 2: addc r4,r4,r9
104 addze r3,r3
105 blr
107 /*
108 * sub_reloc_offset(x) returns x - reloc_offset().
109 */
110 _GLOBAL(sub_reloc_offset)
111 mflr r0
112 bl 1f
113 1: mflr r5
114 lis r4,1b@ha
115 addi r4,r4,1b@l
116 subf r5,r4,r5
117 subf r3,r5,r3
118 mtlr r0
119 blr
121 /*
122 * reloc_got2 runs through the .got2 section adding an offset
123 * to each entry.
124 */
125 _GLOBAL(reloc_got2)
126 mflr r11
127 lis r7,__got2_start@ha
128 addi r7,r7,__got2_start@l
129 lis r8,__got2_end@ha
130 addi r8,r8,__got2_end@l
131 subf r8,r7,r8
132 srwi. r8,r8,2
133 beqlr
134 mtctr r8
135 bl 1f
136 1: mflr r0
137 lis r4,1b@ha
138 addi r4,r4,1b@l
139 subf r0,r4,r0
140 add r7,r0,r7
141 2: lwz r0,0(r7)
142 add r0,r0,r3
143 stw r0,0(r7)
144 addi r7,r7,4
145 bdnz 2b
146 mtlr r11
147 blr
149 /*
150 * call_setup_cpu - call the setup_cpu function for this cpu
151 * r3 = data offset, r24 = cpu number
152 *
153 * Setup function is called with:
154 * r3 = data offset
155 * r4 = ptr to CPU spec (relocated)
156 */
157 _GLOBAL(call_setup_cpu)
158 addis r4,r3,cur_cpu_spec@ha
159 addi r4,r4,cur_cpu_spec@l
160 lwz r4,0(r4)
161 add r4,r4,r3
162 lwz r5,CPU_SPEC_SETUP(r4)
163 cmpwi 0,r5,0
164 add r5,r5,r3
165 beqlr
166 mtctr r5
167 bctr
169 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
171 /* This gets called by via-pmu.c to switch the PLL selection
172 * on 750fx CPU. This function should really be moved to some
173 * other place (as most of the cpufreq code in via-pmu
174 */
175 _GLOBAL(low_choose_750fx_pll)
176 /* Clear MSR:EE */
177 mfmsr r7
178 rlwinm r0,r7,0,17,15
179 mtmsr r0
181 /* If switching to PLL1, disable HID0:BTIC */
182 cmplwi cr0,r3,0
183 beq 1f
184 mfspr r5,SPRN_HID0
185 rlwinm r5,r5,0,27,25
186 sync
187 mtspr SPRN_HID0,r5
188 isync
189 sync
191 1:
192 /* Calc new HID1 value */
193 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
194 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
195 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
196 or r4,r4,r5
197 mtspr SPRN_HID1,r4
199 /* Store new HID1 image */
200 CURRENT_THREAD_INFO(r6, r1)
201 lwz r6,TI_CPU(r6)
202 slwi r6,r6,2
203 addis r6,r6,nap_save_hid1@ha
204 stw r4,nap_save_hid1@l(r6)
206 /* If switching to PLL0, enable HID0:BTIC */
207 cmplwi cr0,r3,0
208 bne 1f
209 mfspr r5,SPRN_HID0
210 ori r5,r5,HID0_BTIC
211 sync
212 mtspr SPRN_HID0,r5
213 isync
214 sync
216 1:
217 /* Return */
218 mtmsr r7
219 blr
221 _GLOBAL(low_choose_7447a_dfs)
222 /* Clear MSR:EE */
223 mfmsr r7
224 rlwinm r0,r7,0,17,15
225 mtmsr r0
227 /* Calc new HID1 value */
228 mfspr r4,SPRN_HID1
229 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
230 sync
231 mtspr SPRN_HID1,r4
232 sync
233 isync
235 /* Return */
236 mtmsr r7
237 blr
239 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
241 /*
242 * complement mask on the msr then "or" some values on.
243 * _nmask_and_or_msr(nmask, value_to_or)
244 */
245 _GLOBAL(_nmask_and_or_msr)
246 mfmsr r0 /* Get current msr */
247 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
248 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
249 SYNC /* Some chip revs have problems here... */
250 mtmsr r0 /* Update machine state */
251 isync
252 blr /* Done */
254 #ifdef CONFIG_40x
256 /*
257 * Do an IO access in real mode
258 */
259 _GLOBAL(real_readb)
260 mfmsr r7
261 ori r0,r7,MSR_DR
262 xori r0,r0,MSR_DR
263 sync
264 mtmsr r0
265 sync
266 isync
267 lbz r3,0(r3)
268 sync
269 mtmsr r7
270 sync
271 isync
272 blr
274 /*
275 * Do an IO access in real mode
276 */
277 _GLOBAL(real_writeb)
278 mfmsr r7
279 ori r0,r7,MSR_DR
280 xori r0,r0,MSR_DR
281 sync
282 mtmsr r0
283 sync
284 isync
285 stb r3,0(r4)
286 sync
287 mtmsr r7
288 sync
289 isync
290 blr
292 #endif /* CONFIG_40x */
295 /*
296 * Flush instruction cache.
297 * This is a no-op on the 601.
298 */
299 _GLOBAL(flush_instruction_cache)
300 #if defined(CONFIG_8xx)
301 isync
302 lis r5, IDC_INVALL@h
303 mtspr SPRN_IC_CST, r5
304 #elif defined(CONFIG_4xx)
305 #ifdef CONFIG_403GCX
306 li r3, 512
307 mtctr r3
308 lis r4, KERNELBASE@h
309 1: iccci 0, r4
310 addi r4, r4, 16
311 bdnz 1b
312 #else
313 lis r3, KERNELBASE@h
314 iccci 0,r3
315 #endif
316 #elif CONFIG_FSL_BOOKE
317 BEGIN_FTR_SECTION
318 mfspr r3,SPRN_L1CSR0
319 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
320 /* msync; isync recommended here */
321 mtspr SPRN_L1CSR0,r3
322 isync
323 blr
324 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
325 mfspr r3,SPRN_L1CSR1
326 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
327 mtspr SPRN_L1CSR1,r3
328 #else
329 mfspr r3,SPRN_PVR
330 rlwinm r3,r3,16,16,31
331 cmpwi 0,r3,1
332 beqlr /* for 601, do nothing */
333 /* 603/604 processor - use invalidate-all bit in HID0 */
334 mfspr r3,SPRN_HID0
335 ori r3,r3,HID0_ICFI
336 mtspr SPRN_HID0,r3
337 #endif /* CONFIG_8xx/4xx */
338 isync
339 blr
341 /*
342 * Write any modified data cache blocks out to memory
343 * and invalidate the corresponding instruction cache blocks.
344 * This is a no-op on the 601.
345 *
346 * flush_icache_range(unsigned long start, unsigned long stop)
347 */
348 _KPROBE(flush_icache_range)
349 BEGIN_FTR_SECTION
350 isync
351 blr /* for 601, do nothing */
352 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
353 li r5,L1_CACHE_BYTES-1
354 andc r3,r3,r5
355 subf r4,r3,r4
356 add r4,r4,r5
357 srwi. r4,r4,L1_CACHE_SHIFT
358 beqlr
359 mtctr r4
360 mr r6,r3
361 1: dcbst 0,r3
362 addi r3,r3,L1_CACHE_BYTES
363 bdnz 1b
364 sync /* wait for dcbst's to get to ram */
365 #ifndef CONFIG_44x
366 mtctr r4
367 2: icbi 0,r6
368 addi r6,r6,L1_CACHE_BYTES
369 bdnz 2b
370 #else
371 /* Flash invalidate on 44x because we are passed kmapped addresses and
372 this doesn't work for userspace pages due to the virtually tagged
373 icache. Sigh. */
374 iccci 0, r0
375 #endif
376 sync /* additional sync needed on g4 */
377 isync
378 blr
379 /*
380 * Write any modified data cache blocks out to memory.
381 * Does not invalidate the corresponding cache lines (especially for
382 * any corresponding instruction cache).
383 *
384 * clean_dcache_range(unsigned long start, unsigned long stop)
385 */
386 _GLOBAL(clean_dcache_range)
387 li r5,L1_CACHE_BYTES-1
388 andc r3,r3,r5
389 subf r4,r3,r4
390 add r4,r4,r5
391 srwi. r4,r4,L1_CACHE_SHIFT
392 beqlr
393 mtctr r4
395 1: dcbst 0,r3
396 addi r3,r3,L1_CACHE_BYTES
397 bdnz 1b
398 sync /* wait for dcbst's to get to ram */
399 blr
401 /*
402 * Write any modified data cache blocks out to memory and invalidate them.
403 * Does not invalidate the corresponding instruction cache blocks.
404 *
405 * flush_dcache_range(unsigned long start, unsigned long stop)
406 */
407 _GLOBAL(flush_dcache_range)
408 li r5,L1_CACHE_BYTES-1
409 andc r3,r3,r5
410 subf r4,r3,r4
411 add r4,r4,r5
412 srwi. r4,r4,L1_CACHE_SHIFT
413 beqlr
414 mtctr r4
416 1: dcbf 0,r3
417 addi r3,r3,L1_CACHE_BYTES
418 bdnz 1b
419 sync /* wait for dcbst's to get to ram */
420 blr
422 /*
423 * Like above, but invalidate the D-cache. This is used by the 8xx
424 * to invalidate the cache so the PPC core doesn't get stale data
425 * from the CPM (no cache snooping here :-).
426 *
427 * invalidate_dcache_range(unsigned long start, unsigned long stop)
428 */
429 _GLOBAL(invalidate_dcache_range)
430 li r5,L1_CACHE_BYTES-1
431 andc r3,r3,r5
432 subf r4,r3,r4
433 add r4,r4,r5
434 srwi. r4,r4,L1_CACHE_SHIFT
435 beqlr
436 mtctr r4
438 1: dcbi 0,r3
439 addi r3,r3,L1_CACHE_BYTES
440 bdnz 1b
441 sync /* wait for dcbi's to get to ram */
442 blr
444 /*
445 * Flush a particular page from the data cache to RAM.
446 * Note: this is necessary because the instruction cache does *not*
447 * snoop from the data cache.
448 * This is a no-op on the 601 which has a unified cache.
449 *
450 * void __flush_dcache_icache(void *page)
451 */
452 _GLOBAL(__flush_dcache_icache)
453 BEGIN_FTR_SECTION
454 blr
455 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
456 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
457 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
458 mtctr r4
459 mr r6,r3
460 0: dcbst 0,r3 /* Write line to ram */
461 addi r3,r3,L1_CACHE_BYTES
462 bdnz 0b
463 sync
464 #ifdef CONFIG_44x
465 /* We don't flush the icache on 44x. Those have a virtual icache
466 * and we don't have access to the virtual address here (it's
467 * not the page vaddr but where it's mapped in user space). The
468 * flushing of the icache on these is handled elsewhere, when
469 * a change in the address space occurs, before returning to
470 * user space
471 */
472 BEGIN_MMU_FTR_SECTION
473 blr
474 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
475 #endif /* CONFIG_44x */
476 mtctr r4
477 1: icbi 0,r6
478 addi r6,r6,L1_CACHE_BYTES
479 bdnz 1b
480 sync
481 isync
482 blr
484 #ifndef CONFIG_BOOKE
485 /*
486 * Flush a particular page from the data cache to RAM, identified
487 * by its physical address. We turn off the MMU so we can just use
488 * the physical address (this may be a highmem page without a kernel
489 * mapping).
490 *
491 * void __flush_dcache_icache_phys(unsigned long physaddr)
492 */
493 _GLOBAL(__flush_dcache_icache_phys)
494 BEGIN_FTR_SECTION
495 blr /* for 601, do nothing */
496 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
497 mfmsr r10
498 rlwinm r0,r10,0,28,26 /* clear DR */
499 mtmsr r0
500 isync
501 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
502 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
503 mtctr r4
504 mr r6,r3
505 0: dcbst 0,r3 /* Write line to ram */
506 addi r3,r3,L1_CACHE_BYTES
507 bdnz 0b
508 sync
509 mtctr r4
510 1: icbi 0,r6
511 addi r6,r6,L1_CACHE_BYTES
512 bdnz 1b
513 sync
514 mtmsr r10 /* restore DR */
515 isync
516 blr
517 #endif /* CONFIG_BOOKE */
519 /*
520 * Clear pages using the dcbz instruction, which doesn't cause any
521 * memory traffic (except to write out any cache lines which get
522 * displaced). This only works on cacheable memory.
523 *
524 * void clear_pages(void *page, int order) ;
525 */
526 _GLOBAL(clear_pages)
527 li r0,PAGE_SIZE/L1_CACHE_BYTES
528 slw r0,r0,r4
529 mtctr r0
530 1: dcbz 0,r3
531 addi r3,r3,L1_CACHE_BYTES
532 bdnz 1b
533 blr
535 /*
536 * Copy a whole page. We use the dcbz instruction on the destination
537 * to reduce memory traffic (it eliminates the unnecessary reads of
538 * the destination into cache). This requires that the destination
539 * is cacheable.
540 */
541 #define COPY_16_BYTES \
542 lwz r6,4(r4); \
543 lwz r7,8(r4); \
544 lwz r8,12(r4); \
545 lwzu r9,16(r4); \
546 stw r6,4(r3); \
547 stw r7,8(r3); \
548 stw r8,12(r3); \
549 stwu r9,16(r3)
551 _GLOBAL(copy_page)
552 addi r3,r3,-4
553 addi r4,r4,-4
555 li r5,4
557 #if MAX_COPY_PREFETCH > 1
558 li r0,MAX_COPY_PREFETCH
559 li r11,4
560 mtctr r0
561 11: dcbt r11,r4
562 addi r11,r11,L1_CACHE_BYTES
563 bdnz 11b
564 #else /* MAX_COPY_PREFETCH == 1 */
565 dcbt r5,r4
566 li r11,L1_CACHE_BYTES+4
567 #endif /* MAX_COPY_PREFETCH */
568 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
569 crclr 4*cr0+eq
570 2:
571 mtctr r0
572 1:
573 dcbt r11,r4
574 dcbz r5,r3
575 COPY_16_BYTES
576 #if L1_CACHE_BYTES >= 32
577 COPY_16_BYTES
578 #if L1_CACHE_BYTES >= 64
579 COPY_16_BYTES
580 COPY_16_BYTES
581 #if L1_CACHE_BYTES >= 128
582 COPY_16_BYTES
583 COPY_16_BYTES
584 COPY_16_BYTES
585 COPY_16_BYTES
586 #endif
587 #endif
588 #endif
589 bdnz 1b
590 beqlr
591 crnot 4*cr0+eq,4*cr0+eq
592 li r0,MAX_COPY_PREFETCH
593 li r11,4
594 b 2b
596 /*
597 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
598 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
599 */
600 _GLOBAL(atomic_clear_mask)
601 10: lwarx r5,0,r4
602 andc r5,r5,r3
603 PPC405_ERR77(0,r4)
604 stwcx. r5,0,r4
605 bne- 10b
606 blr
607 _GLOBAL(atomic_set_mask)
608 10: lwarx r5,0,r4
609 or r5,r5,r3
610 PPC405_ERR77(0,r4)
611 stwcx. r5,0,r4
612 bne- 10b
613 blr
615 /*
616 * Extended precision shifts.
617 *
618 * Updated to be valid for shift counts from 0 to 63 inclusive.
619 * -- Gabriel
620 *
621 * R3/R4 has 64 bit value
622 * R5 has shift count
623 * result in R3/R4
624 *
625 * ashrdi3: arithmetic right shift (sign propagation)
626 * lshrdi3: logical right shift
627 * ashldi3: left shift
628 */
629 _GLOBAL(__ashrdi3)
630 subfic r6,r5,32
631 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
632 addi r7,r5,32 # could be xori, or addi with -32
633 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
634 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
635 sraw r7,r3,r7 # t2 = MSW >> (count-32)
636 or r4,r4,r6 # LSW |= t1
637 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
638 sraw r3,r3,r5 # MSW = MSW >> count
639 or r4,r4,r7 # LSW |= t2
640 blr
642 _GLOBAL(__ashldi3)
643 subfic r6,r5,32
644 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
645 addi r7,r5,32 # could be xori, or addi with -32
646 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
647 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
648 or r3,r3,r6 # MSW |= t1
649 slw r4,r4,r5 # LSW = LSW << count
650 or r3,r3,r7 # MSW |= t2
651 blr
653 _GLOBAL(__lshrdi3)
654 subfic r6,r5,32
655 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
656 addi r7,r5,32 # could be xori, or addi with -32
657 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
658 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
659 or r4,r4,r6 # LSW |= t1
660 srw r3,r3,r5 # MSW = MSW >> count
661 or r4,r4,r7 # LSW |= t2
662 blr
664 /*
665 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
666 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
667 */
668 _GLOBAL(__ucmpdi2)
669 cmplw r3,r5
670 li r3,1
671 bne 1f
672 cmplw r4,r6
673 beqlr
674 1: li r3,0
675 bltlr
676 li r3,2
677 blr
679 _GLOBAL(__bswapdi2)
680 rotlwi r9,r4,8
681 rotlwi r10,r3,8
682 rlwimi r9,r4,24,0,7
683 rlwimi r10,r3,24,0,7
684 rlwimi r9,r4,24,16,23
685 rlwimi r10,r3,24,16,23
686 mr r3,r9
687 mr r4,r10
688 blr
690 _GLOBAL(abs)
691 srawi r4,r3,31
692 xor r3,r3,r4
693 sub r3,r3,r4
694 blr
696 #ifdef CONFIG_SMP
697 _GLOBAL(start_secondary_resume)
698 /* Reset stack */
699 CURRENT_THREAD_INFO(r1, r1)
700 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
701 li r3,0
702 stw r3,0(r1) /* Zero the stack frame pointer */
703 bl start_secondary
704 b .
705 #endif /* CONFIG_SMP */
707 /*
708 * This routine is just here to keep GCC happy - sigh...
709 */
710 _GLOBAL(__main)
711 blr
713 #ifdef CONFIG_KEXEC
714 /*
715 * Must be relocatable PIC code callable as a C function.
716 */
717 .globl relocate_new_kernel
718 relocate_new_kernel:
719 /* r3 = page_list */
720 /* r4 = reboot_code_buffer */
721 /* r5 = start_address */
723 #ifdef CONFIG_FSL_BOOKE
725 mr r29, r3
726 mr r30, r4
727 mr r31, r5
729 #define ENTRY_MAPPING_KEXEC_SETUP
730 #include "fsl_booke_entry_mapping.S"
731 #undef ENTRY_MAPPING_KEXEC_SETUP
733 mr r3, r29
734 mr r4, r30
735 mr r5, r31
737 li r0, 0
738 #elif defined(CONFIG_44x)
740 /* Save our parameters */
741 mr r29, r3
742 mr r30, r4
743 mr r31, r5
745 #ifdef CONFIG_PPC_47x
746 /* Check for 47x cores */
747 mfspr r3,SPRN_PVR
748 srwi r3,r3,16
749 cmplwi cr0,r3,PVR_476@h
750 beq setup_map_47x
751 cmplwi cr0,r3,PVR_476_ISS@h
752 beq setup_map_47x
753 #endif /* CONFIG_PPC_47x */
755 /*
756 * Code for setting up 1:1 mapping for PPC440x for KEXEC
757 *
758 * We cannot switch off the MMU on PPC44x.
759 * So we:
760 * 1) Invalidate all the mappings except the one we are running from.
761 * 2) Create a tmp mapping for our code in the other address space(TS) and
762 * jump to it. Invalidate the entry we started in.
763 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
764 * 4) Jump to the 1:1 mapping in original TS.
765 * 5) Invalidate the tmp mapping.
766 *
767 * - Based on the kexec support code for FSL BookE
768 *
769 */
771 /*
772 * Load the PID with kernel PID (0).
773 * Also load our MSR_IS and TID to MMUCR for TLB search.
774 */
775 li r3, 0
776 mtspr SPRN_PID, r3
777 mfmsr r4
778 andi. r4,r4,MSR_IS@l
779 beq wmmucr
780 oris r3,r3,PPC44x_MMUCR_STS@h
781 wmmucr:
782 mtspr SPRN_MMUCR,r3
783 sync
785 /*
786 * Invalidate all the TLB entries except the current entry
787 * where we are running from
788 */
789 bl 0f /* Find our address */
790 0: mflr r5 /* Make it accessible */
791 tlbsx r23,0,r5 /* Find entry we are in */
792 li r4,0 /* Start at TLB entry 0 */
793 li r3,0 /* Set PAGEID inval value */
794 1: cmpw r23,r4 /* Is this our entry? */
795 beq skip /* If so, skip the inval */
796 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
797 skip:
798 addi r4,r4,1 /* Increment */
799 cmpwi r4,64 /* Are we done? */
800 bne 1b /* If not, repeat */
801 isync
803 /* Create a temp mapping and jump to it */
804 andi. r6, r23, 1 /* Find the index to use */
805 addi r24, r6, 1 /* r24 will contain 1 or 2 */
807 mfmsr r9 /* get the MSR */
808 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
809 xori r7, r5, 1 /* Use the other address space */
811 /* Read the current mapping entries */
812 tlbre r3, r23, PPC44x_TLB_PAGEID
813 tlbre r4, r23, PPC44x_TLB_XLAT
814 tlbre r5, r23, PPC44x_TLB_ATTRIB
816 /* Save our current XLAT entry */
817 mr r25, r4
819 /* Extract the TLB PageSize */
820 li r10, 1 /* r10 will hold PageSize */
821 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
823 /* XXX: As of now we use 256M, 4K pages */
824 cmpwi r11, PPC44x_TLB_256M
825 bne tlb_4k
826 rotlwi r10, r10, 28 /* r10 = 256M */
827 b write_out
828 tlb_4k:
829 cmpwi r11, PPC44x_TLB_4K
830 bne default
831 rotlwi r10, r10, 12 /* r10 = 4K */
832 b write_out
833 default:
834 rotlwi r10, r10, 10 /* r10 = 1K */
836 write_out:
837 /*
838 * Write out the tmp 1:1 mapping for this code in other address space
839 * Fixup EPN = RPN , TS=other address space
840 */
841 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
843 /* Write out the tmp mapping entries */
844 tlbwe r3, r24, PPC44x_TLB_PAGEID
845 tlbwe r4, r24, PPC44x_TLB_XLAT
846 tlbwe r5, r24, PPC44x_TLB_ATTRIB
848 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
849 not r10, r11 /* Mask for PageNum */
851 /* Switch to other address space in MSR */
852 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
854 bl 1f
855 1: mflr r8
856 addi r8, r8, (2f-1b) /* Find the target offset */
858 /* Jump to the tmp mapping */
859 mtspr SPRN_SRR0, r8
860 mtspr SPRN_SRR1, r9
861 rfi
863 2:
864 /* Invalidate the entry we were executing from */
865 li r3, 0
866 tlbwe r3, r23, PPC44x_TLB_PAGEID
868 /* attribute fields. rwx for SUPERVISOR mode */
869 li r5, 0
870 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
872 /* Create 1:1 mapping in 256M pages */
873 xori r7, r7, 1 /* Revert back to Original TS */
875 li r8, 0 /* PageNumber */
876 li r6, 3 /* TLB Index, start at 3 */
878 next_tlb:
879 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
880 mr r4, r3 /* RPN = EPN */
881 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
882 insrwi r3, r7, 1, 23 /* Set TS from r7 */
884 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
885 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
886 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
888 addi r8, r8, 1 /* Increment PN */
889 addi r6, r6, 1 /* Increment TLB Index */
890 cmpwi r8, 8 /* Are we done ? */
891 bne next_tlb
892 isync
894 /* Jump to the new mapping 1:1 */
895 li r9,0
896 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
898 bl 1f
899 1: mflr r8
900 and r8, r8, r11 /* Get our offset within page */
901 addi r8, r8, (2f-1b)
903 and r5, r25, r10 /* Get our target PageNum */
904 or r8, r8, r5 /* Target jump address */
906 mtspr SPRN_SRR0, r8
907 mtspr SPRN_SRR1, r9
908 rfi
909 2:
910 /* Invalidate the tmp entry we used */
911 li r3, 0
912 tlbwe r3, r24, PPC44x_TLB_PAGEID
913 sync
914 b ppc44x_map_done
916 #ifdef CONFIG_PPC_47x
918 /* 1:1 mapping for 47x */
920 setup_map_47x:
922 /*
923 * Load the kernel pid (0) to PID and also to MMUCR[TID].
924 * Also set the MSR IS->MMUCR STS
925 */
926 li r3, 0
927 mtspr SPRN_PID, r3 /* Set PID */
928 mfmsr r4 /* Get MSR */
929 andi. r4, r4, MSR_IS@l /* TS=1? */
930 beq 1f /* If not, leave STS=0 */
931 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
932 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
933 sync
935 /* Find the entry we are running from */
936 bl 2f
937 2: mflr r23
938 tlbsx r23, 0, r23
939 tlbre r24, r23, 0 /* TLB Word 0 */
940 tlbre r25, r23, 1 /* TLB Word 1 */
941 tlbre r26, r23, 2 /* TLB Word 2 */
944 /*
945 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
946 * of 4k page size in all 4 ways (0-3 in r3).
947 * This would invalidate the entire UTLB including the one we are
948 * running from. However the shadow TLB entries would help us
949 * to continue the execution, until we flush them (rfi/isync).
950 */
951 addis r3, 0, 0x8000 /* specify the way */
952 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
953 addi r5, 0, 0
954 b clear_utlb_entry
956 /* Align the loop to speed things up. from head_44x.S */
957 .align 6
959 clear_utlb_entry:
961 tlbwe r4, r3, 0
962 tlbwe r5, r3, 1
963 tlbwe r5, r3, 2
964 addis r3, r3, 0x2000 /* Increment the way */
965 cmpwi r3, 0
966 bne clear_utlb_entry
967 addis r3, 0, 0x8000
968 addis r4, r4, 0x100 /* Increment the EPN */
969 cmpwi r4, 0
970 bne clear_utlb_entry
972 /* Create the entries in the other address space */
973 mfmsr r5
974 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
975 xori r7, r7, 1 /* r7 = !TS */
977 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
979 /*
980 * write out the TLB entries for the tmp mapping
981 * Use way '0' so that we could easily invalidate it later.
982 */
983 lis r3, 0x8000 /* Way '0' */
985 tlbwe r24, r3, 0
986 tlbwe r25, r3, 1
987 tlbwe r26, r3, 2
989 /* Update the msr to the new TS */
990 insrwi r5, r7, 1, 26
992 bl 1f
993 1: mflr r6
994 addi r6, r6, (2f-1b)
996 mtspr SPRN_SRR0, r6
997 mtspr SPRN_SRR1, r5
998 rfi
1000 /*
1001 * Now we are in the tmp address space.
1002 * Create a 1:1 mapping for 0-2GiB in the original TS.
1003 */
1004 2:
1005 li r3, 0
1006 li r4, 0 /* TLB Word 0 */
1007 li r5, 0 /* TLB Word 1 */
1008 li r6, 0
1009 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
1011 li r8, 0 /* PageIndex */
1013 xori r7, r7, 1 /* revert back to original TS */
1015 write_utlb:
1016 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
1017 /* ERPN = 0 as we don't use memory above 2G */
1019 mr r4, r5 /* EPN = RPN */
1020 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1021 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1023 tlbwe r4, r3, 0 /* Write out the entries */
1024 tlbwe r5, r3, 1
1025 tlbwe r6, r3, 2
1026 addi r8, r8, 1
1027 cmpwi r8, 8 /* Have we completed ? */
1028 bne write_utlb
1030 /* make sure we complete the TLB write up */
1031 isync
1033 /*
1034 * Prepare to jump to the 1:1 mapping.
1035 * 1) Extract page size of the tmp mapping
1036 * DSIZ = TLB_Word0[22:27]
1037 * 2) Calculate the physical address of the address
1038 * to jump to.
1039 */
1040 rlwinm r10, r24, 0, 22, 27
1042 cmpwi r10, PPC47x_TLB0_4K
1043 bne 0f
1044 li r10, 0x1000 /* r10 = 4k */
1045 bl 1f
1047 0:
1048 /* Defaults to 256M */
1049 lis r10, 0x1000
1051 bl 1f
1052 1: mflr r4
1053 addi r4, r4, (2f-1b) /* virtual address of 2f */
1055 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
1056 not r10, r11 /* Pagemask = ~(offsetmask) */
1058 and r5, r25, r10 /* Physical page */
1059 and r6, r4, r11 /* offset within the current page */
1061 or r5, r5, r6 /* Physical address for 2f */
1063 /* Switch the TS in MSR to the original one */
1064 mfmsr r8
1065 insrwi r8, r7, 1, 26
1067 mtspr SPRN_SRR1, r8
1068 mtspr SPRN_SRR0, r5
1069 rfi
1071 2:
1072 /* Invalidate the tmp mapping */
1073 lis r3, 0x8000 /* Way '0' */
1075 clrrwi r24, r24, 12 /* Clear the valid bit */
1076 tlbwe r24, r3, 0
1077 tlbwe r25, r3, 1
1078 tlbwe r26, r3, 2
1080 /* Make sure we complete the TLB write and flush the shadow TLB */
1081 isync
1083 #endif
1085 ppc44x_map_done:
1088 /* Restore the parameters */
1089 mr r3, r29
1090 mr r4, r30
1091 mr r5, r31
1093 li r0, 0
1094 #else
1095 li r0, 0
1097 /*
1098 * Set Machine Status Register to a known status,
1099 * switch the MMU off and jump to 1: in a single step.
1100 */
1102 mr r8, r0
1103 ori r8, r8, MSR_RI|MSR_ME
1104 mtspr SPRN_SRR1, r8
1105 addi r8, r4, 1f - relocate_new_kernel
1106 mtspr SPRN_SRR0, r8
1107 sync
1108 rfi
1110 1:
1111 #endif
1112 /* from this point address translation is turned off */
1113 /* and interrupts are disabled */
1115 /* set a new stack at the bottom of our page... */
1116 /* (not really needed now) */
1117 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1118 stw r0, 0(r1)
1120 /* Do the copies */
1121 li r6, 0 /* checksum */
1122 mr r0, r3
1123 b 1f
1125 0: /* top, read another word for the indirection page */
1126 lwzu r0, 4(r3)
1128 1:
1129 /* is it a destination page? (r8) */
1130 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1131 beq 2f
1133 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1134 b 0b
1136 2: /* is it an indirection page? (r3) */
1137 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1138 beq 2f
1140 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1141 subi r3, r3, 4
1142 b 0b
1144 2: /* are we done? */
1145 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1146 beq 2f
1147 b 3f
1149 2: /* is it a source page? (r9) */
1150 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1151 beq 0b
1153 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1155 li r7, PAGE_SIZE / 4
1156 mtctr r7
1157 subi r9, r9, 4
1158 subi r8, r8, 4
1159 9:
1160 lwzu r0, 4(r9) /* do the copy */
1161 xor r6, r6, r0
1162 stwu r0, 4(r8)
1163 dcbst 0, r8
1164 sync
1165 icbi 0, r8
1166 bdnz 9b
1168 addi r9, r9, 4
1169 addi r8, r8, 4
1170 b 0b
1172 3:
1174 /* To be certain of avoiding problems with self-modifying code
1175 * execute a serializing instruction here.
1176 */
1177 isync
1178 sync
1180 mfspr r3, SPRN_PIR /* current core we are running on */
1181 mr r4, r5 /* load physical address of chunk called */
1183 /* jump to the entry point, usually the setup routine */
1184 mtlr r5
1185 blrl
1187 1: b 1b
1189 relocate_new_kernel_end:
1191 .globl relocate_new_kernel_size
1192 relocate_new_kernel_size:
1193 .long relocate_new_kernel_end - relocate_new_kernel
1194 #endif