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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / powerpc / sysdev / fsl_pci.c
blobccfb50ddfe38f7242b071c6519aaa1eb43daf6a2
1 /*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
29 #include <linux/uaccess.h>
30
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/ppc-pci.h>
35 #include <asm/machdep.h>
36 #include <asm/disassemble.h>
37 #include <asm/ppc-opcode.h>
38 #include <sysdev/fsl_soc.h>
39 #include <sysdev/fsl_pci.h>
40
41 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
42
43 static void quirk_fsl_pcie_header(struct pci_dev *dev)
44 {
45 u8 hdr_type;
46
47 /* if we aren't a PCIe don't bother */
48 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
49 return;
50
51 /* if we aren't in host mode don't bother */
52 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
53 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
54 return;
55
56 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
57 fsl_pcie_bus_fixup = 1;
58 return;
59 }
60
61 static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
62 int, int, u32 *);
63
64 static int fsl_pcie_check_link(struct pci_controller *hose)
65 {
66 u32 val = 0;
67
68 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
69 if (hose->ops->read == fsl_indirect_read_config) {
70 struct pci_bus bus;
71 bus.number = hose->first_busno;
72 bus.sysdata = hose;
73 bus.ops = hose->ops;
74 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
75 } else
76 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
77 if (val < PCIE_LTSSM_L0)
78 return 1;
79 } else {
80 struct ccsr_pci __iomem *pci = hose->private_data;
81 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
82 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
83 >> PEX_CSR0_LTSSM_SHIFT;
84 if (val != PEX_CSR0_LTSSM_L0)
85 return 1;
86 }
87
88 return 0;
89 }
90
91 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
92 int offset, int len, u32 *val)
93 {
94 struct pci_controller *hose = pci_bus_to_host(bus);
95
96 if (fsl_pcie_check_link(hose))
97 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
98 else
99 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
100
101 return indirect_read_config(bus, devfn, offset, len, val);
102 }
103
104 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
105
106 static struct pci_ops fsl_indirect_pcie_ops =
107 {
108 .read = fsl_indirect_read_config,
109 .write = indirect_write_config,
110 };
111
112 #define MAX_PHYS_ADDR_BITS 40
113 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
114
115 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
116 {
117 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
118 return -EIO;
119
120 /*
121 * Fixup PCI devices that are able to DMA to above the physical
122 * address width of the SoC such that we can address any internal
123 * SoC address from across PCI if needed
124 */
125 if ((dev->bus == &pci_bus_type) &&
126 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
127 set_dma_ops(dev, &dma_direct_ops);
128 set_dma_offset(dev, pci64_dma_offset);
129 }
130
131 *dev->dma_mask = dma_mask;
132 return 0;
133 }
134
135 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
136 unsigned int index, const struct resource *res,
137 resource_size_t offset)
138 {
139 resource_size_t pci_addr = res->start - offset;
140 resource_size_t phys_addr = res->start;
141 resource_size_t size = resource_size(res);
142 u32 flags = 0x80044000; /* enable & mem R/W */
143 unsigned int i;
144
145 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
146 (u64)res->start, (u64)size);
147
148 if (res->flags & IORESOURCE_PREFETCH)
149 flags |= 0x10000000; /* enable relaxed ordering */
150
151 for (i = 0; size > 0; i++) {
152 unsigned int bits = min(ilog2(size),
153 __ffs(pci_addr | phys_addr));
154
155 if (index + i >= 5)
156 return -1;
157
158 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
159 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
160 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
161 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
162
163 pci_addr += (resource_size_t)1U << bits;
164 phys_addr += (resource_size_t)1U << bits;
165 size -= (resource_size_t)1U << bits;
166 }
167
168 return i;
169 }
170
171 /* atmu setup for fsl pci/pcie controller */
172 static void setup_pci_atmu(struct pci_controller *hose)
173 {
174 struct ccsr_pci __iomem *pci = hose->private_data;
175 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
176 u64 mem, sz, paddr_hi = 0;
177 u64 offset = 0, paddr_lo = ULLONG_MAX;
178 u32 pcicsrbar = 0, pcicsrbar_sz;
179 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
180 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
181 const char *name = hose->dn->full_name;
182 const u64 *reg;
183 int len;
184
185 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
186 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
187 win_idx = 2;
188 start_idx = 0;
189 end_idx = 3;
190 }
191 }
192
193 /* Disable all windows (except powar0 since it's ignored) */
194 for(i = 1; i < 5; i++)
195 out_be32(&pci->pow[i].powar, 0);
196 for (i = start_idx; i < end_idx; i++)
197 out_be32(&pci->piw[i].piwar, 0);
198
199 /* Setup outbound MEM window */
200 for(i = 0, j = 1; i < 3; i++) {
201 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
202 continue;
203
204 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
205 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
206
207 /* We assume all memory resources have the same offset */
208 offset = hose->mem_offset[i];
209 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
210
211 if (n < 0 || j >= 5) {
212 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
213 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
214 } else
215 j += n;
216 }
217
218 /* Setup outbound IO window */
219 if (hose->io_resource.flags & IORESOURCE_IO) {
220 if (j >= 5) {
221 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
222 } else {
223 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
224 "phy base 0x%016llx.\n",
225 (u64)hose->io_resource.start,
226 (u64)resource_size(&hose->io_resource),
227 (u64)hose->io_base_phys);
228 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
229 out_be32(&pci->pow[j].potear, 0);
230 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
231 /* Enable, IO R/W */
232 out_be32(&pci->pow[j].powar, 0x80088000
233 | (ilog2(hose->io_resource.end
234 - hose->io_resource.start + 1) - 1));
235 }
236 }
237
238 /* convert to pci address space */
239 paddr_hi -= offset;
240 paddr_lo -= offset;
241
242 if (paddr_hi == paddr_lo) {
243 pr_err("%s: No outbound window space\n", name);
244 return;
245 }
246
247 if (paddr_lo == 0) {
248 pr_err("%s: No space for inbound window\n", name);
249 return;
250 }
251
252 /* setup PCSRBAR/PEXCSRBAR */
253 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
254 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
255 pcicsrbar_sz = ~pcicsrbar_sz + 1;
256
257 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
258 (paddr_lo > 0x100000000ull))
259 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
260 else
261 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
262 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
263
264 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
265
266 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
267
268 /* Setup inbound mem window */
269 mem = memblock_end_of_DRAM();
270
271 /*
272 * The msi-address-64 property, if it exists, indicates the physical
273 * address of the MSIIR register. Normally, this register is located
274 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
275 * this property exists, then we normally need to create a new ATMU
276 * for it. For now, however, we cheat. The only entity that creates
277 * this property is the Freescale hypervisor, and the address is
278 * specified in the partition configuration. Typically, the address
279 * is located in the page immediately after the end of DDR. If so, we
280 * can avoid allocating a new ATMU by extending the DDR ATMU by one
281 * page.
282 */
283 reg = of_get_property(hose->dn, "msi-address-64", &len);
284 if (reg && (len == sizeof(u64))) {
285 u64 address = be64_to_cpup(reg);
286
287 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
288 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
289 mem += PAGE_SIZE;
290 } else {
291 /* TODO: Create a new ATMU for MSIIR */
292 pr_warn("%s: msi-address-64 address of %llx is "
293 "unsupported\n", name, address);
294 }
295 }
296
297 sz = min(mem, paddr_lo);
298 mem_log = ilog2(sz);
299
300 /* PCIe can overmap inbound & outbound since RX & TX are separated */
301 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
302 /* Size window to exact size if power-of-two or one size up */
303 if ((1ull << mem_log) != mem) {
304 mem_log++;
305 if ((1ull << mem_log) > mem)
306 pr_info("%s: Setting PCI inbound window "
307 "greater than memory size\n", name);
308 }
309
310 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
311
312 /* Setup inbound memory window */
313 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
314 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
315 out_be32(&pci->piw[win_idx].piwar, piwar);
316 win_idx--;
317
318 hose->dma_window_base_cur = 0x00000000;
319 hose->dma_window_size = (resource_size_t)sz;
320
321 /*
322 * if we have >4G of memory setup second PCI inbound window to
323 * let devices that are 64-bit address capable to work w/o
324 * SWIOTLB and access the full range of memory
325 */
326 if (sz != mem) {
327 mem_log = ilog2(mem);
328
329 /* Size window up if we dont fit in exact power-of-2 */
330 if ((1ull << mem_log) != mem)
331 mem_log++;
332
333 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
334
335 /* Setup inbound memory window */
336 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
337 out_be32(&pci->piw[win_idx].piwbear,
338 pci64_dma_offset >> 44);
339 out_be32(&pci->piw[win_idx].piwbar,
340 pci64_dma_offset >> 12);
341 out_be32(&pci->piw[win_idx].piwar, piwar);
342
343 /*
344 * install our own dma_set_mask handler to fixup dma_ops
345 * and dma_offset
346 */
347 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
348
349 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
350 }
351 } else {
352 u64 paddr = 0;
353
354 /* Setup inbound memory window */
355 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
356 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
357 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
358 win_idx--;
359
360 paddr += 1ull << mem_log;
361 sz -= 1ull << mem_log;
362
363 if (sz) {
364 mem_log = ilog2(sz);
365 piwar |= (mem_log - 1);
366
367 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
368 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
369 out_be32(&pci->piw[win_idx].piwar, piwar);
370 win_idx--;
371
372 paddr += 1ull << mem_log;
373 }
374
375 hose->dma_window_base_cur = 0x00000000;
376 hose->dma_window_size = (resource_size_t)paddr;
377 }
378
379 if (hose->dma_window_size < mem) {
380 #ifdef CONFIG_SWIOTLB
381 ppc_swiotlb_enable = 1;
382 #else
383 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
384 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
385 name);
386 #endif
387 /* adjusting outbound windows could reclaim space in mem map */
388 if (paddr_hi < 0xffffffffull)
389 pr_warning("%s: WARNING: Outbound window cfg leaves "
390 "gaps in memory map. Adjusting the memory map "
391 "could reduce unnecessary bounce buffering.\n",
392 name);
393
394 pr_info("%s: DMA window size is 0x%llx\n", name,
395 (u64)hose->dma_window_size);
396 }
397 }
398
399 static void __init setup_pci_cmd(struct pci_controller *hose)
400 {
401 u16 cmd;
402 int cap_x;
403
404 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
405 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
406 | PCI_COMMAND_IO;
407 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
408
409 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
410 if (cap_x) {
411 int pci_x_cmd = cap_x + PCI_X_CMD;
412 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
413 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
414 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
415 } else {
416 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
417 }
418 }
419
420 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
421 {
422 struct pci_controller *hose = pci_bus_to_host(bus);
423 int i, is_pcie = 0, no_link;
424
425 /* The root complex bridge comes up with bogus resources,
426 * we copy the PHB ones in.
427 *
428 * With the current generic PCI code, the PHB bus no longer
429 * has bus->resource[0..4] set, so things are a bit more
430 * tricky.
431 */
432
433 if (fsl_pcie_bus_fixup)
434 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
435 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
436
437 if (bus->parent == hose->bus && (is_pcie || no_link)) {
438 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
439 struct resource *res = bus->resource[i];
440 struct resource *par;
441
442 if (!res)
443 continue;
444 if (i == 0)
445 par = &hose->io_resource;
446 else if (i < 4)
447 par = &hose->mem_resources[i-1];
448 else par = NULL;
449
450 res->start = par ? par->start : 0;
451 res->end = par ? par->end : 0;
452 res->flags = par ? par->flags : 0;
453 }
454 }
455 }
456
457 int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
458 {
459 int len;
460 struct pci_controller *hose;
461 struct resource rsrc;
462 const int *bus_range;
463 u8 hdr_type, progif;
464 struct device_node *dev;
465 struct ccsr_pci __iomem *pci;
466
467 dev = pdev->dev.of_node;
468
469 if (!of_device_is_available(dev)) {
470 pr_warning("%s: disabled\n", dev->full_name);
471 return -ENODEV;
472 }
473
474 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
475
476 /* Fetch host bridge registers address */
477 if (of_address_to_resource(dev, 0, &rsrc)) {
478 printk(KERN_WARNING "Can't get pci register base!");
479 return -ENOMEM;
480 }
481
482 /* Get bus range if any */
483 bus_range = of_get_property(dev, "bus-range", &len);
484 if (bus_range == NULL || len < 2 * sizeof(int))
485 printk(KERN_WARNING "Can't get bus-range for %s, assume"
486 " bus 0\n", dev->full_name);
487
488 pci_add_flags(PCI_REASSIGN_ALL_BUS);
489 hose = pcibios_alloc_controller(dev);
490 if (!hose)
491 return -ENOMEM;
492
493 /* set platform device as the parent */
494 hose->parent = &pdev->dev;
495 hose->first_busno = bus_range ? bus_range[0] : 0x0;
496 hose->last_busno = bus_range ? bus_range[1] : 0xff;
497
498 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
499 (u64)rsrc.start, (u64)resource_size(&rsrc));
500
501 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
502 if (!hose->private_data)
503 goto no_bridge;
504
505 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
506 PPC_INDIRECT_TYPE_BIG_ENDIAN);
507
508 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
509 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
510
511 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
512 /* use fsl_indirect_read_config for PCIe */
513 hose->ops = &fsl_indirect_pcie_ops;
514 /* For PCIE read HEADER_TYPE to identify controler mode */
515 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
516 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
517 goto no_bridge;
518
519 } else {
520 /* For PCI read PROG to identify controller mode */
521 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
522 if ((progif & 1) == 1)
523 goto no_bridge;
524 }
525
526 setup_pci_cmd(hose);
527
528 /* check PCI express link status */
529 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
530 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
531 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
532 if (fsl_pcie_check_link(hose))
533 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
534 }
535
536 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
537 "Firmware bus number: %d->%d\n",
538 (unsigned long long)rsrc.start, hose->first_busno,
539 hose->last_busno);
540
541 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
542 hose, hose->cfg_addr, hose->cfg_data);
543
544 /* Interpret the "ranges" property */
545 /* This also maps the I/O region and sets isa_io/mem_base */
546 pci_process_bridge_OF_ranges(hose, dev, is_primary);
547
548 /* Setup PEX window registers */
549 setup_pci_atmu(hose);
550
551 return 0;
552
553 no_bridge:
554 iounmap(hose->private_data);
555 /* unmap cfg_data & cfg_addr separately if not on same page */
556 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
557 ((unsigned long)hose->cfg_addr & PAGE_MASK))
558 iounmap(hose->cfg_data);
559 iounmap(hose->cfg_addr);
560 pcibios_free_controller(hose);
561 return -ENODEV;
562 }
563 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
564
565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
566
567 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
568 struct mpc83xx_pcie_priv {
569 void __iomem *cfg_type0;
570 void __iomem *cfg_type1;
571 u32 dev_base;
572 };
573
574 struct pex_inbound_window {
575 u32 ar;
576 u32 tar;
577 u32 barl;
578 u32 barh;
579 };
580
581 /*
582 * With the convention of u-boot, the PCIE outbound window 0 serves
583 * as configuration transactions outbound.
584 */
585 #define PEX_OUTWIN0_BAR 0xCA4
586 #define PEX_OUTWIN0_TAL 0xCA8
587 #define PEX_OUTWIN0_TAH 0xCAC
588 #define PEX_RC_INWIN_BASE 0xE60
589 #define PEX_RCIWARn_EN 0x1
590
591 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
592 {
593 struct pci_controller *hose = pci_bus_to_host(bus);
594
595 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
596 return PCIBIOS_DEVICE_NOT_FOUND;
597 /*
598 * Workaround for the HW bug: for Type 0 configure transactions the
599 * PCI-E controller does not check the device number bits and just
600 * assumes that the device number bits are 0.
601 */
602 if (bus->number == hose->first_busno ||
603 bus->primary == hose->first_busno) {
604 if (devfn & 0xf8)
605 return PCIBIOS_DEVICE_NOT_FOUND;
606 }
607
608 if (ppc_md.pci_exclude_device) {
609 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
610 return PCIBIOS_DEVICE_NOT_FOUND;
611 }
612
613 return PCIBIOS_SUCCESSFUL;
614 }
615
616 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
617 unsigned int devfn, int offset)
618 {
619 struct pci_controller *hose = pci_bus_to_host(bus);
620 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
621 u32 dev_base = bus->number << 24 | devfn << 16;
622 int ret;
623
624 ret = mpc83xx_pcie_exclude_device(bus, devfn);
625 if (ret)
626 return NULL;
627
628 offset &= 0xfff;
629
630 /* Type 0 */
631 if (bus->number == hose->first_busno)
632 return pcie->cfg_type0 + offset;
633
634 if (pcie->dev_base == dev_base)
635 goto mapped;
636
637 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
638
639 pcie->dev_base = dev_base;
640 mapped:
641 return pcie->cfg_type1 + offset;
642 }
643
644 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
645 int offset, int len, u32 *val)
646 {
647 void __iomem *cfg_addr;
648
649 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
650 if (!cfg_addr)
651 return PCIBIOS_DEVICE_NOT_FOUND;
652
653 switch (len) {
654 case 1:
655 *val = in_8(cfg_addr);
656 break;
657 case 2:
658 *val = in_le16(cfg_addr);
659 break;
660 default:
661 *val = in_le32(cfg_addr);
662 break;
663 }
664
665 return PCIBIOS_SUCCESSFUL;
666 }
667
668 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
669 int offset, int len, u32 val)
670 {
671 struct pci_controller *hose = pci_bus_to_host(bus);
672 void __iomem *cfg_addr;
673
674 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
675 if (!cfg_addr)
676 return PCIBIOS_DEVICE_NOT_FOUND;
677
678 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
679 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
680 val &= 0xffffff00;
681
682 switch (len) {
683 case 1:
684 out_8(cfg_addr, val);
685 break;
686 case 2:
687 out_le16(cfg_addr, val);
688 break;
689 default:
690 out_le32(cfg_addr, val);
691 break;
692 }
693
694 return PCIBIOS_SUCCESSFUL;
695 }
696
697 static struct pci_ops mpc83xx_pcie_ops = {
698 .read = mpc83xx_pcie_read_config,
699 .write = mpc83xx_pcie_write_config,
700 };
701
702 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
703 struct resource *reg)
704 {
705 struct mpc83xx_pcie_priv *pcie;
706 u32 cfg_bar;
707 int ret = -ENOMEM;
708
709 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
710 if (!pcie)
711 return ret;
712
713 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
714 if (!pcie->cfg_type0)
715 goto err0;
716
717 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
718 if (!cfg_bar) {
719 /* PCI-E isn't configured. */
720 ret = -ENODEV;
721 goto err1;
722 }
723
724 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
725 if (!pcie->cfg_type1)
726 goto err1;
727
728 WARN_ON(hose->dn->data);
729 hose->dn->data = pcie;
730 hose->ops = &mpc83xx_pcie_ops;
731 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
732
733 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
734 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
735
736 if (fsl_pcie_check_link(hose))
737 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
738
739 return 0;
740 err1:
741 iounmap(pcie->cfg_type0);
742 err0:
743 kfree(pcie);
744 return ret;
745
746 }
747
748 int __init mpc83xx_add_bridge(struct device_node *dev)
749 {
750 int ret;
751 int len;
752 struct pci_controller *hose;
753 struct resource rsrc_reg;
754 struct resource rsrc_cfg;
755 const int *bus_range;
756 int primary;
757
758 is_mpc83xx_pci = 1;
759
760 if (!of_device_is_available(dev)) {
761 pr_warning("%s: disabled by the firmware.\n",
762 dev->full_name);
763 return -ENODEV;
764 }
765 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
766
767 /* Fetch host bridge registers address */
768 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
769 printk(KERN_WARNING "Can't get pci register base!\n");
770 return -ENOMEM;
771 }
772
773 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
774
775 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
776 printk(KERN_WARNING
777 "No pci config register base in dev tree, "
778 "using default\n");
779 /*
780 * MPC83xx supports up to two host controllers
781 * one at 0x8500 has config space registers at 0x8300
782 * one at 0x8600 has config space registers at 0x8380
783 */
784 if ((rsrc_reg.start & 0xfffff) == 0x8500)
785 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
786 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
787 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
788 }
789 /*
790 * Controller at offset 0x8500 is primary
791 */
792 if ((rsrc_reg.start & 0xfffff) == 0x8500)
793 primary = 1;
794 else
795 primary = 0;
796
797 /* Get bus range if any */
798 bus_range = of_get_property(dev, "bus-range", &len);
799 if (bus_range == NULL || len < 2 * sizeof(int)) {
800 printk(KERN_WARNING "Can't get bus-range for %s, assume"
801 " bus 0\n", dev->full_name);
802 }
803
804 pci_add_flags(PCI_REASSIGN_ALL_BUS);
805 hose = pcibios_alloc_controller(dev);
806 if (!hose)
807 return -ENOMEM;
808
809 hose->first_busno = bus_range ? bus_range[0] : 0;
810 hose->last_busno = bus_range ? bus_range[1] : 0xff;
811
812 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
813 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
814 if (ret)
815 goto err0;
816 } else {
817 setup_indirect_pci(hose, rsrc_cfg.start,
818 rsrc_cfg.start + 4, 0);
819 }
820
821 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
822 "Firmware bus number: %d->%d\n",
823 (unsigned long long)rsrc_reg.start, hose->first_busno,
824 hose->last_busno);
825
826 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
827 hose, hose->cfg_addr, hose->cfg_data);
828
829 /* Interpret the "ranges" property */
830 /* This also maps the I/O region and sets isa_io/mem_base */
831 pci_process_bridge_OF_ranges(hose, dev, primary);
832
833 return 0;
834 err0:
835 pcibios_free_controller(hose);
836 return ret;
837 }
838 #endif /* CONFIG_PPC_83xx */
839
840 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
841 {
842 #ifdef CONFIG_PPC_83xx
843 if (is_mpc83xx_pci) {
844 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
845 struct pex_inbound_window *in;
846 int i;
847
848 /* Walk the Root Complex Inbound windows to match IMMR base */
849 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
850 for (i = 0; i < 4; i++) {
851 /* not enabled, skip */
852 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
853 continue;
854
855 if (get_immrbase() == in_le32(&in[i].tar))
856 return (u64)in_le32(&in[i].barh) << 32 |
857 in_le32(&in[i].barl);
858 }
859
860 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
861 }
862 #endif
863
864 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
865 if (!is_mpc83xx_pci) {
866 u32 base;
867
868 pci_bus_read_config_dword(hose->bus,
869 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
870 return base;
871 }
872 #endif
873
874 return 0;
875 }
876
877 #ifdef CONFIG_E500
878 static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
879 {
880 unsigned int rd, ra, rb, d;
881
882 rd = get_rt(inst);
883 ra = get_ra(inst);
884 rb = get_rb(inst);
885 d = get_d(inst);
886
887 switch (get_op(inst)) {
888 case 31:
889 switch (get_xop(inst)) {
890 case OP_31_XOP_LWZX:
891 case OP_31_XOP_LWBRX:
892 regs->gpr[rd] = 0xffffffff;
893 break;
894
895 case OP_31_XOP_LWZUX:
896 regs->gpr[rd] = 0xffffffff;
897 regs->gpr[ra] += regs->gpr[rb];
898 break;
899
900 case OP_31_XOP_LBZX:
901 regs->gpr[rd] = 0xff;
902 break;
903
904 case OP_31_XOP_LBZUX:
905 regs->gpr[rd] = 0xff;
906 regs->gpr[ra] += regs->gpr[rb];
907 break;
908
909 case OP_31_XOP_LHZX:
910 case OP_31_XOP_LHBRX:
911 regs->gpr[rd] = 0xffff;
912 break;
913
914 case OP_31_XOP_LHZUX:
915 regs->gpr[rd] = 0xffff;
916 regs->gpr[ra] += regs->gpr[rb];
917 break;
918
919 case OP_31_XOP_LHAX:
920 regs->gpr[rd] = ~0UL;
921 break;
922
923 case OP_31_XOP_LHAUX:
924 regs->gpr[rd] = ~0UL;
925 regs->gpr[ra] += regs->gpr[rb];
926 break;
927
928 default:
929 return 0;
930 }
931 break;
932
933 case OP_LWZ:
934 regs->gpr[rd] = 0xffffffff;
935 break;
936
937 case OP_LWZU:
938 regs->gpr[rd] = 0xffffffff;
939 regs->gpr[ra] += (s16)d;
940 break;
941
942 case OP_LBZ:
943 regs->gpr[rd] = 0xff;
944 break;
945
946 case OP_LBZU:
947 regs->gpr[rd] = 0xff;
948 regs->gpr[ra] += (s16)d;
949 break;
950
951 case OP_LHZ:
952 regs->gpr[rd] = 0xffff;
953 break;
954
955 case OP_LHZU:
956 regs->gpr[rd] = 0xffff;
957 regs->gpr[ra] += (s16)d;
958 break;
959
960 case OP_LHA:
961 regs->gpr[rd] = ~0UL;
962 break;
963
964 case OP_LHAU:
965 regs->gpr[rd] = ~0UL;
966 regs->gpr[ra] += (s16)d;
967 break;
968
969 default:
970 return 0;
971 }
972
973 return 1;
974 }
975
976 static int is_in_pci_mem_space(phys_addr_t addr)
977 {
978 struct pci_controller *hose;
979 struct resource *res;
980 int i;
981
982 list_for_each_entry(hose, &hose_list, list_node) {
983 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
984 continue;
985
986 for (i = 0; i < 3; i++) {
987 res = &hose->mem_resources[i];
988 if ((res->flags & IORESOURCE_MEM) &&
989 addr >= res->start && addr <= res->end)
990 return 1;
991 }
992 }
993 return 0;
994 }
995
996 int fsl_pci_mcheck_exception(struct pt_regs *regs)
997 {
998 u32 inst;
999 int ret;
1000 phys_addr_t addr = 0;
1001
1002 /* Let KVM/QEMU deal with the exception */
1003 if (regs->msr & MSR_GS)
1004 return 0;
1005
1006 #ifdef CONFIG_PHYS_64BIT
1007 addr = mfspr(SPRN_MCARU);
1008 addr <<= 32;
1009 #endif
1010 addr += mfspr(SPRN_MCAR);
1011
1012 if (is_in_pci_mem_space(addr)) {
1013 if (user_mode(regs)) {
1014 pagefault_disable();
1015 ret = get_user(regs->nip, &inst);
1016 pagefault_enable();
1017 } else {
1018 ret = probe_kernel_address(regs->nip, inst);
1019 }
1020
1021 if (mcheck_handle_load(regs, inst)) {
1022 regs->nip += 4;
1023 return 1;
1024 }
1025 }
1026
1027 return 0;
1028 }
1029 #endif
1030
1031 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1032 static const struct of_device_id pci_ids[] = {
1033 { .compatible = "fsl,mpc8540-pci", },
1034 { .compatible = "fsl,mpc8548-pcie", },
1035 { .compatible = "fsl,mpc8610-pci", },
1036 { .compatible = "fsl,mpc8641-pcie", },
1037 { .compatible = "fsl,qoriq-pcie-v2.1", },
1038 { .compatible = "fsl,qoriq-pcie-v2.2", },
1039 { .compatible = "fsl,qoriq-pcie-v2.3", },
1040 { .compatible = "fsl,qoriq-pcie-v2.4", },
1041 { .compatible = "fsl,qoriq-pcie-v3.0", },
1042
1043 /*
1044 * The following entries are for compatibility with older device
1045 * trees.
1046 */
1047 { .compatible = "fsl,p1022-pcie", },
1048 { .compatible = "fsl,p4080-pcie", },
1049
1050 {},
1051 };
1052
1053 struct device_node *fsl_pci_primary;
1054
1055 void fsl_pci_assign_primary(void)
1056 {
1057 struct device_node *np;
1058
1059 /* Callers can specify the primary bus using other means. */
1060 if (fsl_pci_primary)
1061 return;
1062
1063 /* If a PCI host bridge contains an ISA node, it's primary. */
1064 np = of_find_node_by_type(NULL, "isa");
1065 while ((fsl_pci_primary = of_get_parent(np))) {
1066 of_node_put(np);
1067 np = fsl_pci_primary;
1068
1069 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1070 return;
1071 }
1072
1073 /*
1074 * If there's no PCI host bridge with ISA, arbitrarily
1075 * designate one as primary. This can go away once
1076 * various bugs with primary-less systems are fixed.
1077 */
1078 for_each_matching_node(np, pci_ids) {
1079 if (of_device_is_available(np)) {
1080 fsl_pci_primary = np;
1081 of_node_put(np);
1082 return;
1083 }
1084 }
1085 }
1086
1087 static int fsl_pci_probe(struct platform_device *pdev)
1088 {
1089 int ret;
1090 struct device_node *node;
1091
1092 node = pdev->dev.of_node;
1093 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1094
1095 mpc85xx_pci_err_probe(pdev);
1096
1097 return 0;
1098 }
1099
1100 #ifdef CONFIG_PM
1101 static int fsl_pci_resume(struct device *dev)
1102 {
1103 struct pci_controller *hose;
1104 struct resource pci_rsrc;
1105
1106 hose = pci_find_hose_for_OF_device(dev->of_node);
1107 if (!hose)
1108 return -ENODEV;
1109
1110 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
1111 dev_err(dev, "Get pci register base failed.");
1112 return -ENODEV;
1113 }
1114
1115 setup_pci_atmu(hose);
1116
1117 return 0;
1118 }
1119
1120 static const struct dev_pm_ops pci_pm_ops = {
1121 .resume = fsl_pci_resume,
1122 };
1123
1124 #define PCI_PM_OPS (&pci_pm_ops)
1125
1126 #else
1127
1128 #define PCI_PM_OPS NULL
1129
1130 #endif
1131
1132 static struct platform_driver fsl_pci_driver = {
1133 .driver = {
1134 .name = "fsl-pci",
1135 .pm = PCI_PM_OPS,
1136 .of_match_table = pci_ids,
1137 },
1138 .probe = fsl_pci_probe,
1139 };
1140
1141 static int __init fsl_pci_init(void)
1142 {
1143 return platform_driver_register(&fsl_pci_driver);
1144 }
1145 arch_initcall(fsl_pci_init);
1146 #endif
Linux with added FPC-III support