x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / powerpc / sysdev / i8259.c
blob997df6a7ab5d19fd1aeac65d020f51d2d17ba482
1 /*
2 * i8259 interrupt controller driver.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9 #undef DEBUG
11 #include <linux/init.h>
12 #include <linux/ioport.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <asm/io.h>
17 #include <asm/i8259.h>
18 #include <asm/prom.h>
20 static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
22 static unsigned char cached_8259[2] = { 0xff, 0xff };
23 #define cached_A1 (cached_8259[0])
24 #define cached_21 (cached_8259[1])
26 static DEFINE_RAW_SPINLOCK(i8259_lock);
28 static struct irq_domain *i8259_host;
31 * Acknowledge the IRQ using either the PCI host bridge's interrupt
32 * acknowledge feature or poll. How i8259_init() is called determines
33 * which is called. It should be noted that polling is broken on some
34 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
36 unsigned int i8259_irq(void)
38 int irq;
39 int lock = 0;
41 /* Either int-ack or poll for the IRQ */
42 if (pci_intack)
43 irq = readb(pci_intack);
44 else {
45 raw_spin_lock(&i8259_lock);
46 lock = 1;
48 /* Perform an interrupt acknowledge cycle on controller 1. */
49 outb(0x0C, 0x20); /* prepare for poll */
50 irq = inb(0x20) & 7;
51 if (irq == 2 ) {
53 * Interrupt is cascaded so perform interrupt
54 * acknowledge on controller 2.
56 outb(0x0C, 0xA0); /* prepare for poll */
57 irq = (inb(0xA0) & 7) + 8;
61 if (irq == 7) {
63 * This may be a spurious interrupt.
65 * Read the interrupt status register (ISR). If the most
66 * significant bit is not set then there is no valid
67 * interrupt.
69 if (!pci_intack)
70 outb(0x0B, 0x20); /* ISR register */
71 if(~inb(0x20) & 0x80)
72 irq = NO_IRQ;
73 } else if (irq == 0xff)
74 irq = NO_IRQ;
76 if (lock)
77 raw_spin_unlock(&i8259_lock);
78 return irq;
81 static void i8259_mask_and_ack_irq(struct irq_data *d)
83 unsigned long flags;
85 raw_spin_lock_irqsave(&i8259_lock, flags);
86 if (d->irq > 7) {
87 cached_A1 |= 1 << (d->irq-8);
88 inb(0xA1); /* DUMMY */
89 outb(cached_A1, 0xA1);
90 outb(0x20, 0xA0); /* Non-specific EOI */
91 outb(0x20, 0x20); /* Non-specific EOI to cascade */
92 } else {
93 cached_21 |= 1 << d->irq;
94 inb(0x21); /* DUMMY */
95 outb(cached_21, 0x21);
96 outb(0x20, 0x20); /* Non-specific EOI */
98 raw_spin_unlock_irqrestore(&i8259_lock, flags);
101 static void i8259_set_irq_mask(int irq_nr)
103 outb(cached_A1,0xA1);
104 outb(cached_21,0x21);
107 static void i8259_mask_irq(struct irq_data *d)
109 unsigned long flags;
111 pr_debug("i8259_mask_irq(%d)\n", d->irq);
113 raw_spin_lock_irqsave(&i8259_lock, flags);
114 if (d->irq < 8)
115 cached_21 |= 1 << d->irq;
116 else
117 cached_A1 |= 1 << (d->irq-8);
118 i8259_set_irq_mask(d->irq);
119 raw_spin_unlock_irqrestore(&i8259_lock, flags);
122 static void i8259_unmask_irq(struct irq_data *d)
124 unsigned long flags;
126 pr_debug("i8259_unmask_irq(%d)\n", d->irq);
128 raw_spin_lock_irqsave(&i8259_lock, flags);
129 if (d->irq < 8)
130 cached_21 &= ~(1 << d->irq);
131 else
132 cached_A1 &= ~(1 << (d->irq-8));
133 i8259_set_irq_mask(d->irq);
134 raw_spin_unlock_irqrestore(&i8259_lock, flags);
137 static struct irq_chip i8259_pic = {
138 .name = "i8259",
139 .irq_mask = i8259_mask_irq,
140 .irq_disable = i8259_mask_irq,
141 .irq_unmask = i8259_unmask_irq,
142 .irq_mask_ack = i8259_mask_and_ack_irq,
145 static struct resource pic1_iores = {
146 .name = "8259 (master)",
147 .start = 0x20,
148 .end = 0x21,
149 .flags = IORESOURCE_BUSY,
152 static struct resource pic2_iores = {
153 .name = "8259 (slave)",
154 .start = 0xa0,
155 .end = 0xa1,
156 .flags = IORESOURCE_BUSY,
159 static struct resource pic_edgectrl_iores = {
160 .name = "8259 edge control",
161 .start = 0x4d0,
162 .end = 0x4d1,
163 .flags = IORESOURCE_BUSY,
166 static int i8259_host_match(struct irq_domain *h, struct device_node *node)
168 return h->of_node == NULL || h->of_node == node;
171 static int i8259_host_map(struct irq_domain *h, unsigned int virq,
172 irq_hw_number_t hw)
174 pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw);
176 /* We block the internal cascade */
177 if (hw == 2)
178 irq_set_status_flags(virq, IRQ_NOREQUEST);
180 /* We use the level handler only for now, we might want to
181 * be more cautious here but that works for now
183 irq_set_status_flags(virq, IRQ_LEVEL);
184 irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
185 return 0;
188 static int i8259_host_xlate(struct irq_domain *h, struct device_node *ct,
189 const u32 *intspec, unsigned int intsize,
190 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
192 static unsigned char map_isa_senses[4] = {
193 IRQ_TYPE_LEVEL_LOW,
194 IRQ_TYPE_LEVEL_HIGH,
195 IRQ_TYPE_EDGE_FALLING,
196 IRQ_TYPE_EDGE_RISING,
199 *out_hwirq = intspec[0];
200 if (intsize > 1 && intspec[1] < 4)
201 *out_flags = map_isa_senses[intspec[1]];
202 else
203 *out_flags = IRQ_TYPE_NONE;
205 return 0;
208 static struct irq_domain_ops i8259_host_ops = {
209 .match = i8259_host_match,
210 .map = i8259_host_map,
211 .xlate = i8259_host_xlate,
214 struct irq_domain *i8259_get_host(void)
216 return i8259_host;
220 * i8259_init - Initialize the legacy controller
221 * @node: device node of the legacy PIC (can be NULL, but then, it will match
222 * all interrupts, so beware)
223 * @intack_addr: PCI interrupt acknowledge (real) address which will return
224 * the active irq from the 8259
226 void i8259_init(struct device_node *node, unsigned long intack_addr)
228 unsigned long flags;
230 /* initialize the controller */
231 raw_spin_lock_irqsave(&i8259_lock, flags);
233 /* Mask all first */
234 outb(0xff, 0xA1);
235 outb(0xff, 0x21);
237 /* init master interrupt controller */
238 outb(0x11, 0x20); /* Start init sequence */
239 outb(0x00, 0x21); /* Vector base */
240 outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
241 outb(0x01, 0x21); /* Select 8086 mode */
243 /* init slave interrupt controller */
244 outb(0x11, 0xA0); /* Start init sequence */
245 outb(0x08, 0xA1); /* Vector base */
246 outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
247 outb(0x01, 0xA1); /* Select 8086 mode */
249 /* That thing is slow */
250 udelay(100);
252 /* always read ISR */
253 outb(0x0B, 0x20);
254 outb(0x0B, 0xA0);
256 /* Unmask the internal cascade */
257 cached_21 &= ~(1 << 2);
259 /* Set interrupt masks */
260 outb(cached_A1, 0xA1);
261 outb(cached_21, 0x21);
263 raw_spin_unlock_irqrestore(&i8259_lock, flags);
265 /* create a legacy host */
266 i8259_host = irq_domain_add_legacy_isa(node, &i8259_host_ops, NULL);
267 if (i8259_host == NULL) {
268 printk(KERN_ERR "i8259: failed to allocate irq host !\n");
269 return;
272 /* reserve our resources */
273 /* XXX should we continue doing that ? it seems to cause problems
274 * with further requesting of PCI IO resources for that range...
275 * need to look into it.
277 request_resource(&ioport_resource, &pic1_iores);
278 request_resource(&ioport_resource, &pic2_iores);
279 request_resource(&ioport_resource, &pic_edgectrl_iores);
281 if (intack_addr != 0)
282 pci_intack = ioremap(intack_addr, 1);
284 printk(KERN_INFO "i8259 legacy interrupt controller initialized\n");