4 * Copyright 2013 Freescale Semiconductor, Inc.
5 * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
6 * Li Yang <leoli@freescale.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
22 #include <linux/of_device.h>
23 #include <linux/syscore_ops.h>
24 #include <sysdev/fsl_soc.h>
27 #include <asm/mpic_timer.h>
29 #define FSL_GLOBAL_TIMER 0x1
32 * Divide by 64 0x00000300
33 * Divide by 32 0x00000200
34 * Divide by 16 0x00000100
35 * Divide by 8 0x00000000 (Hardware default div)
37 #define MPIC_TIMER_TCR_CLKDIV 0x00000300
39 #define MPIC_TIMER_TCR_ROVR_OFFSET 24
41 #define TIMER_STOP 0x80000000
42 #define TIMERS_PER_GROUP 4
43 #define MAX_TICKS (~0U >> 1)
44 #define MAX_TICKS_CASCADE (~0U)
45 #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
47 /* tv_usec should be less than ONE_SECOND, otherwise use tv_sec */
48 #define ONE_SECOND 1000000
62 u32 tcr_value
; /* TCR register: CASC & ROVR value */
63 unsigned int cascade_map
; /* cascade map */
64 unsigned int timer_num
; /* cascade control timer */
67 struct timer_group_priv
{
68 struct timer_regs __iomem
*regs
;
69 struct mpic_timer timer
[TIMERS_PER_GROUP
];
70 struct list_head node
;
71 unsigned int timerfreq
;
75 void __iomem
*group_tcr
;
78 static struct cascade_priv cascade_timer
[] = {
79 /* cascade timer 0 and 1 */
81 /* cascade timer 1 and 2 */
83 /* cascade timer 2 and 3 */
87 static LIST_HEAD(timer_group_list
);
89 static void convert_ticks_to_time(struct timer_group_priv
*priv
,
90 const u64 ticks
, struct timeval
*time
)
94 time
->tv_sec
= (__kernel_time_t
)div_u64(ticks
, priv
->timerfreq
);
95 tmp_sec
= (u64
)time
->tv_sec
* (u64
)priv
->timerfreq
;
97 time
->tv_usec
= (__kernel_suseconds_t
)
98 div_u64((ticks
- tmp_sec
) * 1000000, priv
->timerfreq
);
103 /* the time set by the user is converted to "ticks" */
104 static int convert_time_to_ticks(struct timer_group_priv
*priv
,
105 const struct timeval
*time
, u64
*ticks
)
107 u64 max_value
; /* prevent u64 overflow */
114 max_value
= div_u64(ULLONG_MAX
, priv
->timerfreq
);
116 if (time
->tv_sec
> max_value
||
117 (time
->tv_sec
== max_value
&& time
->tv_usec
> 0))
120 tmp_sec
= (u64
)time
->tv_sec
* (u64
)priv
->timerfreq
;
123 tmp_ms
= time
->tv_usec
/ 1000;
124 tmp_ms
= div_u64((u64
)tmp_ms
* (u64
)priv
->timerfreq
, 1000);
127 tmp_us
= time
->tv_usec
% 1000;
128 tmp_us
= div_u64((u64
)tmp_us
* (u64
)priv
->timerfreq
, 1000000);
136 /* detect whether there is a cascade timer available */
137 static struct mpic_timer
*detect_idle_cascade_timer(
138 struct timer_group_priv
*priv
)
140 struct cascade_priv
*casc_priv
;
142 unsigned int array_size
= ARRAY_SIZE(cascade_timer
);
147 casc_priv
= cascade_timer
;
148 for (i
= 0; i
< array_size
; i
++) {
149 spin_lock_irqsave(&priv
->lock
, flags
);
150 map
= casc_priv
->cascade_map
& priv
->idle
;
151 if (map
== casc_priv
->cascade_map
) {
152 num
= casc_priv
->timer_num
;
153 priv
->timer
[num
].cascade_handle
= casc_priv
;
156 priv
->idle
&= ~casc_priv
->cascade_map
;
157 spin_unlock_irqrestore(&priv
->lock
, flags
);
158 return &priv
->timer
[num
];
160 spin_unlock_irqrestore(&priv
->lock
, flags
);
167 static int set_cascade_timer(struct timer_group_priv
*priv
, u64 ticks
,
170 struct cascade_priv
*casc_priv
;
175 /* set group tcr reg for cascade */
176 casc_priv
= priv
->timer
[num
].cascade_handle
;
180 tcr
= casc_priv
->tcr_value
|
181 (casc_priv
->tcr_value
<< MPIC_TIMER_TCR_ROVR_OFFSET
);
182 setbits32(priv
->group_tcr
, tcr
);
184 tmp_ticks
= div_u64_rem(ticks
, MAX_TICKS_CASCADE
, &rem_ticks
);
186 out_be32(&priv
->regs
[num
].gtccr
, 0);
187 out_be32(&priv
->regs
[num
].gtbcr
, tmp_ticks
| TIMER_STOP
);
189 out_be32(&priv
->regs
[num
- 1].gtccr
, 0);
190 out_be32(&priv
->regs
[num
- 1].gtbcr
, rem_ticks
);
195 static struct mpic_timer
*get_cascade_timer(struct timer_group_priv
*priv
,
198 struct mpic_timer
*allocated_timer
;
200 /* Two cascade timers: Support the maximum time */
201 const u64 max_ticks
= (u64
)MAX_TICKS
* (u64
)MAX_TICKS_CASCADE
;
204 if (ticks
> max_ticks
)
207 /* detect idle timer */
208 allocated_timer
= detect_idle_cascade_timer(priv
);
209 if (!allocated_timer
)
212 /* set ticks to timer */
213 ret
= set_cascade_timer(priv
, ticks
, allocated_timer
->num
);
217 return allocated_timer
;
220 static struct mpic_timer
*get_timer(const struct timeval
*time
)
222 struct timer_group_priv
*priv
;
223 struct mpic_timer
*timer
;
231 list_for_each_entry(priv
, &timer_group_list
, node
) {
232 ret
= convert_time_to_ticks(priv
, time
, &ticks
);
236 if (ticks
> MAX_TICKS
) {
237 if (!(priv
->flags
& FSL_GLOBAL_TIMER
))
240 timer
= get_cascade_timer(priv
, ticks
);
247 for (i
= 0; i
< TIMERS_PER_GROUP
; i
++) {
248 /* one timer: Reverse allocation */
249 num
= TIMERS_PER_GROUP
- 1 - i
;
250 spin_lock_irqsave(&priv
->lock
, flags
);
251 if (priv
->idle
& (1 << i
)) {
253 priv
->idle
&= ~(1 << i
);
254 /* set ticks & stop timer */
255 out_be32(&priv
->regs
[num
].gtbcr
,
257 out_be32(&priv
->regs
[num
].gtccr
, 0);
258 priv
->timer
[num
].cascade_handle
= NULL
;
259 spin_unlock_irqrestore(&priv
->lock
, flags
);
260 return &priv
->timer
[num
];
262 spin_unlock_irqrestore(&priv
->lock
, flags
);
270 * mpic_start_timer - start hardware timer
271 * @handle: the timer to be started.
273 * It will do ->fn(->dev) callback from the hardware interrupt at
274 * the ->timeval point in the future.
276 void mpic_start_timer(struct mpic_timer
*handle
)
278 struct timer_group_priv
*priv
= container_of(handle
,
279 struct timer_group_priv
, timer
[handle
->num
]);
281 clrbits32(&priv
->regs
[handle
->num
].gtbcr
, TIMER_STOP
);
283 EXPORT_SYMBOL(mpic_start_timer
);
286 * mpic_stop_timer - stop hardware timer
287 * @handle: the timer to be stoped
289 * The timer periodically generates an interrupt. Unless user stops the timer.
291 void mpic_stop_timer(struct mpic_timer
*handle
)
293 struct timer_group_priv
*priv
= container_of(handle
,
294 struct timer_group_priv
, timer
[handle
->num
]);
295 struct cascade_priv
*casc_priv
;
297 setbits32(&priv
->regs
[handle
->num
].gtbcr
, TIMER_STOP
);
299 casc_priv
= priv
->timer
[handle
->num
].cascade_handle
;
301 out_be32(&priv
->regs
[handle
->num
].gtccr
, 0);
302 out_be32(&priv
->regs
[handle
->num
- 1].gtccr
, 0);
304 out_be32(&priv
->regs
[handle
->num
].gtccr
, 0);
307 EXPORT_SYMBOL(mpic_stop_timer
);
310 * mpic_get_remain_time - get timer time
311 * @handle: the timer to be selected.
312 * @time: time for timer
314 * Query timer remaining time.
316 void mpic_get_remain_time(struct mpic_timer
*handle
, struct timeval
*time
)
318 struct timer_group_priv
*priv
= container_of(handle
,
319 struct timer_group_priv
, timer
[handle
->num
]);
320 struct cascade_priv
*casc_priv
;
325 casc_priv
= priv
->timer
[handle
->num
].cascade_handle
;
327 tmp_ticks
= in_be32(&priv
->regs
[handle
->num
].gtccr
);
328 ticks
= ((u64
)tmp_ticks
& UINT_MAX
) * (u64
)MAX_TICKS_CASCADE
;
329 tmp_ticks
= in_be32(&priv
->regs
[handle
->num
- 1].gtccr
);
332 ticks
= in_be32(&priv
->regs
[handle
->num
].gtccr
);
335 convert_ticks_to_time(priv
, ticks
, time
);
337 EXPORT_SYMBOL(mpic_get_remain_time
);
340 * mpic_free_timer - free hardware timer
341 * @handle: the timer to be removed.
345 * Note: can not be used in interrupt context.
347 void mpic_free_timer(struct mpic_timer
*handle
)
349 struct timer_group_priv
*priv
= container_of(handle
,
350 struct timer_group_priv
, timer
[handle
->num
]);
352 struct cascade_priv
*casc_priv
;
355 mpic_stop_timer(handle
);
357 casc_priv
= priv
->timer
[handle
->num
].cascade_handle
;
359 free_irq(priv
->timer
[handle
->num
].irq
, priv
->timer
[handle
->num
].dev
);
361 spin_lock_irqsave(&priv
->lock
, flags
);
364 tcr
= casc_priv
->tcr_value
| (casc_priv
->tcr_value
<<
365 MPIC_TIMER_TCR_ROVR_OFFSET
);
366 clrbits32(priv
->group_tcr
, tcr
);
367 priv
->idle
|= casc_priv
->cascade_map
;
368 priv
->timer
[handle
->num
].cascade_handle
= NULL
;
370 priv
->idle
|= TIMER_OFFSET(handle
->num
);
372 spin_unlock_irqrestore(&priv
->lock
, flags
);
374 EXPORT_SYMBOL(mpic_free_timer
);
377 * mpic_request_timer - get a hardware timer
378 * @fn: interrupt handler function
379 * @dev: callback function of the data
380 * @time: time for timer
382 * This executes the "request_irq", returning NULL
383 * else "handle" on success.
385 struct mpic_timer
*mpic_request_timer(irq_handler_t fn
, void *dev
,
386 const struct timeval
*time
)
388 struct mpic_timer
*allocated_timer
;
391 if (list_empty(&timer_group_list
))
394 if (!(time
->tv_sec
+ time
->tv_usec
) ||
395 time
->tv_sec
< 0 || time
->tv_usec
< 0)
398 if (time
->tv_usec
> ONE_SECOND
)
401 allocated_timer
= get_timer(time
);
402 if (!allocated_timer
)
405 ret
= request_irq(allocated_timer
->irq
, fn
,
406 IRQF_TRIGGER_LOW
, "global-timer", dev
);
408 mpic_free_timer(allocated_timer
);
412 allocated_timer
->dev
= dev
;
414 return allocated_timer
;
416 EXPORT_SYMBOL(mpic_request_timer
);
418 static int timer_group_get_freq(struct device_node
*np
,
419 struct timer_group_priv
*priv
)
423 if (priv
->flags
& FSL_GLOBAL_TIMER
) {
424 struct device_node
*dn
;
426 dn
= of_find_compatible_node(NULL
, NULL
, "fsl,mpic");
428 of_property_read_u32(dn
, "clock-frequency",
434 if (priv
->timerfreq
<= 0)
437 if (priv
->flags
& FSL_GLOBAL_TIMER
) {
438 div
= (1 << (MPIC_TIMER_TCR_CLKDIV
>> 8)) * 8;
439 priv
->timerfreq
/= div
;
445 static int timer_group_get_irq(struct device_node
*np
,
446 struct timer_group_priv
*priv
)
448 const u32 all_timer
[] = { 0, TIMERS_PER_GROUP
};
455 unsigned int irq_index
= 0;
459 p
= of_get_property(np
, "fsl,available-ranges", &len
);
460 if (p
&& len
% (2 * sizeof(u32
)) != 0) {
461 pr_err("%s: malformed available-ranges property.\n",
468 len
= sizeof(all_timer
);
471 len
/= 2 * sizeof(u32
);
473 for (i
= 0; i
< len
; i
++) {
475 count
= p
[i
* 2 + 1];
476 for (j
= 0; j
< count
; j
++) {
477 irq
= irq_of_parse_and_map(np
, irq_index
);
479 pr_err("%s: irq parse and map failed.\n",
485 priv
->idle
|= TIMER_OFFSET((offset
+ j
));
486 priv
->timer
[offset
+ j
].irq
= irq
;
487 priv
->timer
[offset
+ j
].num
= offset
+ j
;
495 static void timer_group_init(struct device_node
*np
)
497 struct timer_group_priv
*priv
;
501 priv
= kzalloc(sizeof(struct timer_group_priv
), GFP_KERNEL
);
503 pr_err("%s: cannot allocate memory for group.\n",
508 if (of_device_is_compatible(np
, "fsl,mpic-global-timer"))
509 priv
->flags
|= FSL_GLOBAL_TIMER
;
511 priv
->regs
= of_iomap(np
, i
++);
513 pr_err("%s: cannot ioremap timer register address.\n",
518 if (priv
->flags
& FSL_GLOBAL_TIMER
) {
519 priv
->group_tcr
= of_iomap(np
, i
++);
520 if (!priv
->group_tcr
) {
521 pr_err("%s: cannot ioremap tcr address.\n",
527 ret
= timer_group_get_freq(np
, priv
);
529 pr_err("%s: cannot get timer frequency.\n", np
->full_name
);
533 ret
= timer_group_get_irq(np
, priv
);
535 pr_err("%s: cannot get timer irqs.\n", np
->full_name
);
539 spin_lock_init(&priv
->lock
);
541 /* Init FSL timer hardware */
542 if (priv
->flags
& FSL_GLOBAL_TIMER
)
543 setbits32(priv
->group_tcr
, MPIC_TIMER_TCR_CLKDIV
);
545 list_add_tail(&priv
->node
, &timer_group_list
);
554 iounmap(priv
->group_tcr
);
559 static void mpic_timer_resume(void)
561 struct timer_group_priv
*priv
;
563 list_for_each_entry(priv
, &timer_group_list
, node
) {
564 /* Init FSL timer hardware */
565 if (priv
->flags
& FSL_GLOBAL_TIMER
)
566 setbits32(priv
->group_tcr
, MPIC_TIMER_TCR_CLKDIV
);
570 static const struct of_device_id mpic_timer_ids
[] = {
571 { .compatible
= "fsl,mpic-global-timer", },
575 static struct syscore_ops mpic_timer_syscore_ops
= {
576 .resume
= mpic_timer_resume
,
579 static int __init
mpic_timer_init(void)
581 struct device_node
*np
= NULL
;
583 for_each_matching_node(np
, mpic_timer_ids
)
584 timer_group_init(np
);
586 register_syscore_ops(&mpic_timer_syscore_ops
);
588 if (list_empty(&timer_group_list
))
593 subsys_initcall(mpic_timer_init
);