2 * arch/sh/drivers/dma/dma-sh.c
4 * SuperH On-chip DMAC Support
6 * Copyright (C) 2000 Takashi YOSHII
7 * Copyright (C) 2003, 2004 Paul Mundt
8 * Copyright (C) 2005 Andriy Skulysh
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
18 #include <mach-dreamcast/mach/dma.h>
20 #include <asm/dma-register.h>
21 #include <cpu/dma-register.h>
25 * Define the default configuration for dual address memory-memory transfer.
26 * The 0x400 value represents auto-request, external->external.
28 #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
30 static unsigned long dma_find_base(unsigned int chan
)
32 unsigned long base
= SH_DMAC_BASE0
;
42 static unsigned long dma_base_addr(unsigned int chan
)
44 unsigned long base
= dma_find_base(chan
);
46 /* Normalize offset calculation */
52 return base
+ (chan
* 0x10);
55 #ifdef CONFIG_SH_DMA_IRQ_MULTI
56 static inline unsigned int get_dmte_irq(unsigned int chan
)
58 return chan
>= 6 ? DMTE6_IRQ
: DMTE0_IRQ
;
62 static unsigned int dmte_irq_map
[] = {
63 DMTE0_IRQ
, DMTE0_IRQ
+ 1, DMTE0_IRQ
+ 2, DMTE0_IRQ
+ 3,
66 DMTE4_IRQ
, DMTE4_IRQ
+ 1,
70 DMTE6_IRQ
, DMTE6_IRQ
+ 1,
74 DMTE8_IRQ
, DMTE9_IRQ
, DMTE10_IRQ
, DMTE11_IRQ
,
78 static inline unsigned int get_dmte_irq(unsigned int chan
)
80 return dmte_irq_map
[chan
];
85 * We determine the correct shift size based off of the CHCR transmit size
86 * for the given channel. Since we know that it will take:
88 * info->count >> ts_shift[transmit_size]
90 * iterations to complete the transfer.
92 static unsigned int ts_shift
[] = TS_SHIFT
;
94 static inline unsigned int calc_xmit_shift(struct dma_channel
*chan
)
96 u32 chcr
= __raw_readl(dma_base_addr(chan
->chan
) + CHCR
);
97 int cnt
= ((chcr
& CHCR_TS_LOW_MASK
) >> CHCR_TS_LOW_SHIFT
) |
98 ((chcr
& CHCR_TS_HIGH_MASK
) >> CHCR_TS_HIGH_SHIFT
);
100 return ts_shift
[cnt
];
104 * The transfer end interrupt must read the chcr register to end the
105 * hardware interrupt active condition.
106 * Besides that it needs to waken any waiting process, which should handle
107 * setting up the next transfer.
109 static irqreturn_t
dma_tei(int irq
, void *dev_id
)
111 struct dma_channel
*chan
= dev_id
;
114 chcr
= __raw_readl(dma_base_addr(chan
->chan
) + CHCR
);
116 if (!(chcr
& CHCR_TE
))
119 chcr
&= ~(CHCR_IE
| CHCR_DE
);
120 __raw_writel(chcr
, (dma_base_addr(chan
->chan
) + CHCR
));
122 wake_up(&chan
->wait_queue
);
127 static int sh_dmac_request_dma(struct dma_channel
*chan
)
129 if (unlikely(!(chan
->flags
& DMA_TEI_CAPABLE
)))
132 return request_irq(get_dmte_irq(chan
->chan
), dma_tei
, IRQF_SHARED
,
136 static void sh_dmac_free_dma(struct dma_channel
*chan
)
138 free_irq(get_dmte_irq(chan
->chan
), chan
);
142 sh_dmac_configure_channel(struct dma_channel
*chan
, unsigned long chcr
)
145 chcr
= RS_DUAL
| CHCR_IE
;
147 if (chcr
& CHCR_IE
) {
149 chan
->flags
|= DMA_TEI_CAPABLE
;
151 chan
->flags
&= ~DMA_TEI_CAPABLE
;
154 __raw_writel(chcr
, (dma_base_addr(chan
->chan
) + CHCR
));
156 chan
->flags
|= DMA_CONFIGURED
;
160 static void sh_dmac_enable_dma(struct dma_channel
*chan
)
165 chcr
= __raw_readl(dma_base_addr(chan
->chan
) + CHCR
);
168 if (chan
->flags
& DMA_TEI_CAPABLE
)
171 __raw_writel(chcr
, (dma_base_addr(chan
->chan
) + CHCR
));
173 if (chan
->flags
& DMA_TEI_CAPABLE
) {
174 irq
= get_dmte_irq(chan
->chan
);
179 static void sh_dmac_disable_dma(struct dma_channel
*chan
)
184 if (chan
->flags
& DMA_TEI_CAPABLE
) {
185 irq
= get_dmte_irq(chan
->chan
);
189 chcr
= __raw_readl(dma_base_addr(chan
->chan
) + CHCR
);
190 chcr
&= ~(CHCR_DE
| CHCR_TE
| CHCR_IE
);
191 __raw_writel(chcr
, (dma_base_addr(chan
->chan
) + CHCR
));
194 static int sh_dmac_xfer_dma(struct dma_channel
*chan
)
197 * If we haven't pre-configured the channel with special flags, use
200 if (unlikely(!(chan
->flags
& DMA_CONFIGURED
)))
201 sh_dmac_configure_channel(chan
, 0);
203 sh_dmac_disable_dma(chan
);
206 * Single-address mode usage note!
208 * It's important that we don't accidentally write any value to SAR/DAR
209 * (this includes 0) that hasn't been directly specified by the user if
210 * we're in single-address mode.
212 * In this case, only one address can be defined, anything else will
213 * result in a DMA address error interrupt (at least on the SH-4),
214 * which will subsequently halt the transfer.
216 * Channel 2 on the Dreamcast is a special case, as this is used for
217 * cascading to the PVR2 DMAC. In this case, we still need to write
218 * SAR and DAR, regardless of value, in order for cascading to work.
220 if (chan
->sar
|| (mach_is_dreamcast() &&
221 chan
->chan
== PVR2_CASCADE_CHAN
))
222 __raw_writel(chan
->sar
, (dma_base_addr(chan
->chan
) + SAR
));
223 if (chan
->dar
|| (mach_is_dreamcast() &&
224 chan
->chan
== PVR2_CASCADE_CHAN
))
225 __raw_writel(chan
->dar
, (dma_base_addr(chan
->chan
) + DAR
));
227 __raw_writel(chan
->count
>> calc_xmit_shift(chan
),
228 (dma_base_addr(chan
->chan
) + TCR
));
230 sh_dmac_enable_dma(chan
);
235 static int sh_dmac_get_dma_residue(struct dma_channel
*chan
)
237 if (!(__raw_readl(dma_base_addr(chan
->chan
) + CHCR
) & CHCR_DE
))
240 return __raw_readl(dma_base_addr(chan
->chan
) + TCR
)
241 << calc_xmit_shift(chan
);
247 #if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
248 defined(CONFIG_CPU_SUBTYPE_SH7724) || \
249 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7785)
257 * DMAOR bases are broken out amongst channel groups. DMAOR0 manages
258 * channels 0 - 5, DMAOR1 6 - 11 (optional).
260 #define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6))
261 #define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6)
263 static inline int dmaor_reset(int no
)
265 unsigned long dmaor
= dmaor_read_reg(no
);
267 /* Try to clear the error flags first, incase they are set */
268 dmaor
&= ~(DMAOR_NMIF
| DMAOR_AE
);
269 dmaor_write_reg(no
, dmaor
);
272 dmaor_write_reg(no
, dmaor
);
274 /* See if we got an error again */
275 if ((dmaor_read_reg(no
) & (DMAOR_AE
| DMAOR_NMIF
))) {
276 printk(KERN_ERR
"dma-sh: Can't initialize DMAOR.\n");
286 #ifdef CONFIG_CPU_SH4
288 #if defined(DMAE1_IRQ)
294 static const char *dmae_name
[] = {
295 "DMAC Address Error0",
296 "DMAC Address Error1"
299 #ifdef CONFIG_SH_DMA_IRQ_MULTI
300 static inline unsigned int get_dma_error_irq(int n
)
302 return get_dmte_irq(n
* 6);
306 static unsigned int dmae_irq_map
[] = {
314 static inline unsigned int get_dma_error_irq(int n
)
316 return dmae_irq_map
[n
];
320 static irqreturn_t
dma_err(int irq
, void *dummy
)
324 for (i
= 0; i
< NR_DMAOR
; i
++)
332 static int dmae_irq_init(void)
336 for (n
= 0; n
< NR_DMAE
; n
++) {
337 int i
= request_irq(get_dma_error_irq(n
), dma_err
,
338 IRQF_SHARED
, dmae_name
[n
], (void *)dmae_name
[n
]);
339 if (unlikely(i
< 0)) {
340 printk(KERN_ERR
"%s request_irq fail\n", dmae_name
[n
]);
348 static void dmae_irq_free(void)
352 for (n
= 0; n
< NR_DMAE
; n
++)
353 free_irq(get_dma_error_irq(n
), NULL
);
356 static inline int dmae_irq_init(void)
361 static void dmae_irq_free(void)
366 static struct dma_ops sh_dmac_ops
= {
367 .request
= sh_dmac_request_dma
,
368 .free
= sh_dmac_free_dma
,
369 .get_residue
= sh_dmac_get_dma_residue
,
370 .xfer
= sh_dmac_xfer_dma
,
371 .configure
= sh_dmac_configure_channel
,
374 static struct dma_info sh_dmac_info
= {
376 .nr_channels
= CONFIG_NR_ONCHIP_DMA_CHANNELS
,
378 .flags
= DMAC_CHANNELS_TEI_CAPABLE
,
381 static int __init
sh_dmac_init(void)
383 struct dma_info
*info
= &sh_dmac_info
;
387 * Initialize DMAE, for parts that support it.
389 rc
= dmae_irq_init();
390 if (unlikely(rc
!= 0))
394 * Initialize DMAOR, and clean up any error flags that may have
397 for (i
= 0; i
< NR_DMAOR
; i
++) {
399 if (unlikely(rc
!= 0))
403 return register_dmac(info
);
406 static void __exit
sh_dmac_exit(void)
409 unregister_dmac(&sh_dmac_info
);
412 subsys_initcall(sh_dmac_init
);
413 module_exit(sh_dmac_exit
);
415 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
416 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
417 MODULE_LICENSE("GPL");