1 #ifndef _SPARC_CONTREGS_H
2 #define _SPARC_CONTREGS_H
4 /* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
5 * space. These are for the mmu's context register, etc.
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
10 /* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
11 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
12 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
13 #define AC_M_CXR 0x0200 /* shv Context Register */
14 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
15 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
16 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
17 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
18 #define AC_M_RESET 0x0700 /* hv Reset Reg */
19 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
20 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
21 #define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
22 #define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
23 #define AC_M_ITR 0x1300 /* hv Index Tag Register */
24 #define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
25 #define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
26 #define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
27 #define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
28 #define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
29 #define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
31 #endif /* _SPARC_CONTREGS_H */
