arch/sparc/include/asm/pgtable_64.h

   1 /*
   2  * pgtable.h: SpitFire page table operations.
   3  *
   4  * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #ifndef _SPARC64_PGTABLE_H
   9 #define _SPARC64_PGTABLE_H
  10
  11 /* This file contains the functions and defines necessary to modify and use
  12  * the SpitFire page tables.
  13  */
  14
  15 #include <linux/compiler.h>
  16 #include <linux/const.h>
  17 #include <asm/types.h>
  18 #include <asm/spitfire.h>
  19 #include <asm/asi.h>
  20 #include <asm/page.h>
  21 #include <asm/processor.h>
  22
  23 #include <asm-generic/pgtable-nopud.h>
  24
  25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
  26  * The page copy blockops can use 0x6000000 to 0x8000000.
  27  * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
  28  * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
  29  * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
  30  * The vmalloc area spans 0x100000000 to 0x200000000.
  31  * Since modules need to be in the lowest 32-bits of the address space,
  32  * we place them right before the OBP area from 0x10000000 to 0xf0000000.
  33  * There is a single static kernel PMD which maps from 0x0 to address
  34  * 0x400000000.
  35  */
  36 #define TLBTEMP_BASE            _AC(0x0000000006000000,UL)
  37 #define TSBMAP_8K_BASE          _AC(0x0000000008000000,UL)
  38 #define TSBMAP_4M_BASE          _AC(0x0000000008400000,UL)
  39 #define MODULES_VADDR           _AC(0x0000000010000000,UL)
  40 #define MODULES_LEN             _AC(0x00000000e0000000,UL)
  41 #define MODULES_END             _AC(0x00000000f0000000,UL)
  42 #define LOW_OBP_ADDRESS         _AC(0x00000000f0000000,UL)
  43 #define HI_OBP_ADDRESS          _AC(0x0000000100000000,UL)
  44 #define VMALLOC_START           _AC(0x0000000100000000,UL)
  45 #define VMALLOC_END             _AC(0x0000010000000000,UL)
  46 #define VMEMMAP_BASE            _AC(0x0000010000000000,UL)
  47
  48 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
  49
  50 /* PMD_SHIFT determines the size of the area a second-level page
  51  * table can map
  52  */
  53 #define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-4))
  54 #define PMD_SIZE        (_AC(1,UL) << PMD_SHIFT)
  55 #define PMD_MASK        (~(PMD_SIZE-1))
  56 #define PMD_BITS        (PAGE_SHIFT - 2)
  57
  58 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  59 #define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-4) + PMD_BITS)
  60 #define PGDIR_SIZE      (_AC(1,UL) << PGDIR_SHIFT)
  61 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  62 #define PGDIR_BITS      (PAGE_SHIFT - 2)
  63
  64 #if (PGDIR_SHIFT + PGDIR_BITS) != 44
  65 #error Page table parameters do not cover virtual address space properly.
  66 #endif
  67
  68 #if (PMD_SHIFT != HPAGE_SHIFT)
  69 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
  70 #endif
  71
  72 /* PMDs point to PTE tables which are 4K aligned.  */
  73 #define PMD_PADDR       _AC(0xfffffffe,UL)
  74 #define PMD_PADDR_SHIFT _AC(11,UL)
  75
  76 #define PMD_ISHUGE      _AC(0x00000001,UL)
  77
  78 /* This is the PMD layout when PMD_ISHUGE is set.  With 4MB huge
  79  * pages, this frees up a bunch of bits in the layout that we can
  80  * use for the protection settings and software metadata.
  81  */
  82 #define PMD_HUGE_PADDR          _AC(0xfffff800,UL)
  83 #define PMD_HUGE_PROTBITS       _AC(0x000007ff,UL)
  84 #define PMD_HUGE_PRESENT        _AC(0x00000400,UL)
  85 #define PMD_HUGE_WRITE          _AC(0x00000200,UL)
  86 #define PMD_HUGE_DIRTY          _AC(0x00000100,UL)
  87 #define PMD_HUGE_ACCESSED       _AC(0x00000080,UL)
  88 #define PMD_HUGE_EXEC           _AC(0x00000040,UL)
  89 #define PMD_HUGE_SPLITTING      _AC(0x00000020,UL)
  90
  91 /* PGDs point to PMD tables which are 8K aligned.  */
  92 #define PGD_PADDR       _AC(0xfffffffc,UL)
  93 #define PGD_PADDR_SHIFT _AC(11,UL)
  94
  95 #ifndef __ASSEMBLY__
  96
  97 #include <linux/sched.h>
  98
  99 /* Entries per page directory level. */
 100 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-4))
 101 #define PTRS_PER_PMD    (1UL << PMD_BITS)
 102 #define PTRS_PER_PGD    (1UL << PGDIR_BITS)
 103
 104 /* Kernel has a separate 44bit address space. */
 105 #define FIRST_USER_ADDRESS      0
 106
 107 #define pmd_ERROR(e)                                                    \
 108         pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n",             \
 109                __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0))
 110 #define pgd_ERROR(e)                                                    \
 111         pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n",             \
 112                __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0))
 113
 114 #endif /* !(__ASSEMBLY__) */
 115
 116 /* PTE bits which are the same in SUN4U and SUN4V format.  */
 117 #define _PAGE_VALID       _AC(0x8000000000000000,UL) /* Valid TTE            */
 118 #define _PAGE_R           _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
 119 #define _PAGE_SPECIAL     _AC(0x0200000000000000,UL) /* Special page         */
 120
 121 /* Advertise support for _PAGE_SPECIAL */
 122 #define __HAVE_ARCH_PTE_SPECIAL
 123
 124 /* SUN4U pte bits... */
 125 #define _PAGE_SZ4MB_4U    _AC(0x6000000000000000,UL) /* 4MB Page             */
 126 #define _PAGE_SZ512K_4U   _AC(0x4000000000000000,UL) /* 512K Page            */
 127 #define _PAGE_SZ64K_4U    _AC(0x2000000000000000,UL) /* 64K Page             */
 128 #define _PAGE_SZ8K_4U     _AC(0x0000000000000000,UL) /* 8K Page              */
 129 #define _PAGE_NFO_4U      _AC(0x1000000000000000,UL) /* No Fault Only        */
 130 #define _PAGE_IE_4U       _AC(0x0800000000000000,UL) /* Invert Endianness    */
 131 #define _PAGE_SOFT2_4U    _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
 132 #define _PAGE_SPECIAL_4U  _AC(0x0200000000000000,UL) /* Special page         */
 133 #define _PAGE_RES1_4U     _AC(0x0002000000000000,UL) /* Reserved             */
 134 #define _PAGE_SZ32MB_4U   _AC(0x0001000000000000,UL) /* (Panther) 32MB page  */
 135 #define _PAGE_SZ256MB_4U  _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
 136 #define _PAGE_SZALL_4U    _AC(0x6001000000000000,UL) /* All pgsz bits        */
 137 #define _PAGE_SN_4U       _AC(0x0000800000000000,UL) /* (Cheetah) Snoop      */
 138 #define _PAGE_RES2_4U     _AC(0x0000780000000000,UL) /* Reserved             */
 139 #define _PAGE_PADDR_4U    _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13]  */
 140 #define _PAGE_SOFT_4U     _AC(0x0000000000001F80,UL) /* Software bits:       */
 141 #define _PAGE_EXEC_4U     _AC(0x0000000000001000,UL) /* Executable SW bit    */
 142 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty)     */
 143 #define _PAGE_FILE_4U     _AC(0x0000000000000800,UL) /* Pagecache page       */
 144 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd)     */
 145 #define _PAGE_READ_4U     _AC(0x0000000000000200,UL) /* Readable SW Bit      */
 146 #define _PAGE_WRITE_4U    _AC(0x0000000000000100,UL) /* Writable SW Bit      */
 147 #define _PAGE_PRESENT_4U  _AC(0x0000000000000080,UL) /* Present              */
 148 #define _PAGE_L_4U        _AC(0x0000000000000040,UL) /* Locked TTE           */
 149 #define _PAGE_CP_4U       _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
 150 #define _PAGE_CV_4U       _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
 151 #define _PAGE_E_4U        _AC(0x0000000000000008,UL) /* side-Effect          */
 152 #define _PAGE_P_4U        _AC(0x0000000000000004,UL) /* Privileged Page      */
 153 #define _PAGE_W_4U        _AC(0x0000000000000002,UL) /* Writable             */
 154
 155 /* SUN4V pte bits... */
 156 #define _PAGE_NFO_4V      _AC(0x4000000000000000,UL) /* No Fault Only        */
 157 #define _PAGE_SOFT2_4V    _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
 158 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty)     */
 159 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd)     */
 160 #define _PAGE_READ_4V     _AC(0x0800000000000000,UL) /* Readable SW Bit      */
 161 #define _PAGE_WRITE_4V    _AC(0x0400000000000000,UL) /* Writable SW Bit      */
 162 #define _PAGE_SPECIAL_4V  _AC(0x0200000000000000,UL) /* Special page         */
 163 #define _PAGE_PADDR_4V    _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13]         */
 164 #define _PAGE_IE_4V       _AC(0x0000000000001000,UL) /* Invert Endianness    */
 165 #define _PAGE_E_4V        _AC(0x0000000000000800,UL) /* side-Effect          */
 166 #define _PAGE_CP_4V       _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
 167 #define _PAGE_CV_4V       _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
 168 #define _PAGE_P_4V        _AC(0x0000000000000100,UL) /* Privileged Page      */
 169 #define _PAGE_EXEC_4V     _AC(0x0000000000000080,UL) /* Executable Page      */
 170 #define _PAGE_W_4V        _AC(0x0000000000000040,UL) /* Writable             */
 171 #define _PAGE_SOFT_4V     _AC(0x0000000000000030,UL) /* Software bits        */
 172 #define _PAGE_FILE_4V     _AC(0x0000000000000020,UL) /* Pagecache page       */
 173 #define _PAGE_PRESENT_4V  _AC(0x0000000000000010,UL) /* Present              */
 174 #define _PAGE_RESV_4V     _AC(0x0000000000000008,UL) /* Reserved             */
 175 #define _PAGE_SZ16GB_4V   _AC(0x0000000000000007,UL) /* 16GB Page            */
 176 #define _PAGE_SZ2GB_4V    _AC(0x0000000000000006,UL) /* 2GB Page             */
 177 #define _PAGE_SZ256MB_4V  _AC(0x0000000000000005,UL) /* 256MB Page           */
 178 #define _PAGE_SZ32MB_4V   _AC(0x0000000000000004,UL) /* 32MB Page            */
 179 #define _PAGE_SZ4MB_4V    _AC(0x0000000000000003,UL) /* 4MB Page             */
 180 #define _PAGE_SZ512K_4V   _AC(0x0000000000000002,UL) /* 512K Page            */
 181 #define _PAGE_SZ64K_4V    _AC(0x0000000000000001,UL) /* 64K Page             */
 182 #define _PAGE_SZ8K_4V     _AC(0x0000000000000000,UL) /* 8K Page              */
 183 #define _PAGE_SZALL_4V    _AC(0x0000000000000007,UL) /* All pgsz bits        */
 184
 185 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
 186 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
 187
 188 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
 189 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
 190
 191 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
 192 #define __P000  __pgprot(0)
 193 #define __P001  __pgprot(0)
 194 #define __P010  __pgprot(0)
 195 #define __P011  __pgprot(0)
 196 #define __P100  __pgprot(0)
 197 #define __P101  __pgprot(0)
 198 #define __P110  __pgprot(0)
 199 #define __P111  __pgprot(0)
 200
 201 #define __S000  __pgprot(0)
 202 #define __S001  __pgprot(0)
 203 #define __S010  __pgprot(0)
 204 #define __S011  __pgprot(0)
 205 #define __S100  __pgprot(0)
 206 #define __S101  __pgprot(0)
 207 #define __S110  __pgprot(0)
 208 #define __S111  __pgprot(0)
 209
 210 #ifndef __ASSEMBLY__
 211
 212 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
 213
 214 extern unsigned long pte_sz_bits(unsigned long size);
 215
 216 extern pgprot_t PAGE_KERNEL;
 217 extern pgprot_t PAGE_KERNEL_LOCKED;
 218 extern pgprot_t PAGE_COPY;
 219 extern pgprot_t PAGE_SHARED;
 220
 221 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
 222 extern unsigned long _PAGE_IE;
 223 extern unsigned long _PAGE_E;
 224 extern unsigned long _PAGE_CACHE;
 225
 226 extern unsigned long pg_iobits;
 227 extern unsigned long _PAGE_ALL_SZ_BITS;
 228
 229 extern struct page *mem_map_zero;
 230 #define ZERO_PAGE(vaddr)        (mem_map_zero)
 231
 232 /* PFNs are real physical page numbers.  However, mem_map only begins to record
 233  * per-page information starting at pfn_base.  This is to handle systems where
 234  * the first physical page in the machine is at some huge physical address,
 235  * such as 4GB.   This is common on a partitioned E10000, for example.
 236  */
 237 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 238 {
 239         unsigned long paddr = pfn << PAGE_SHIFT;
 240
 241         BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
 242         return __pte(paddr | pgprot_val(prot));
 243 }
 244 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 245
 246 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 247 extern pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot);
 248 #define mk_pmd(page, pgprot)    pfn_pmd(page_to_pfn(page), (pgprot))
 249
 250 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
 251
 252 static inline pmd_t pmd_mkhuge(pmd_t pmd)
 253 {
 254         /* Do nothing, mk_pmd() does this part.  */
 255         return pmd;
 256 }
 257 #endif
 258
 259 /* This one can be done with two shifts.  */
 260 static inline unsigned long pte_pfn(pte_t pte)
 261 {
 262         unsigned long ret;
 263
 264         __asm__ __volatile__(
 265         "\n661: sllx            %1, %2, %0\n"
 266         "       srlx            %0, %3, %0\n"
 267         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 268         "       .word           661b\n"
 269         "       sllx            %1, %4, %0\n"
 270         "       srlx            %0, %5, %0\n"
 271         "       .previous\n"
 272         : "=r" (ret)
 273         : "r" (pte_val(pte)),
 274           "i" (21), "i" (21 + PAGE_SHIFT),
 275           "i" (8), "i" (8 + PAGE_SHIFT));
 276
 277         return ret;
 278 }
 279 #define pte_page(x) pfn_to_page(pte_pfn(x))
 280
 281 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
 282 {
 283         unsigned long mask, tmp;
 284
 285         /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
 286          * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
 287          *
 288          * Even if we use negation tricks the result is still a 6
 289          * instruction sequence, so don't try to play fancy and just
 290          * do the most straightforward implementation.
 291          *
 292          * Note: We encode this into 3 sun4v 2-insn patch sequences.
 293          */
 294
 295         BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
 296         __asm__ __volatile__(
 297         "\n661: sethi           %%uhi(%2), %1\n"
 298         "       sethi           %%hi(%2), %0\n"
 299         "\n662: or              %1, %%ulo(%2), %1\n"
 300         "       or              %0, %%lo(%2), %0\n"
 301         "\n663: sllx            %1, 32, %1\n"
 302         "       or              %0, %1, %0\n"
 303         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 304         "       .word           661b\n"
 305         "       sethi           %%uhi(%3), %1\n"
 306         "       sethi           %%hi(%3), %0\n"
 307         "       .word           662b\n"
 308         "       or              %1, %%ulo(%3), %1\n"
 309         "       or              %0, %%lo(%3), %0\n"
 310         "       .word           663b\n"
 311         "       sllx            %1, 32, %1\n"
 312         "       or              %0, %1, %0\n"
 313         "       .previous\n"
 314         : "=r" (mask), "=r" (tmp)
 315         : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
 316                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
 317                _PAGE_SPECIAL),
 318           "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
 319                _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
 320                _PAGE_SPECIAL));
 321
 322         return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
 323 }
 324
 325 static inline pte_t pgoff_to_pte(unsigned long off)
 326 {
 327         off <<= PAGE_SHIFT;
 328
 329         __asm__ __volatile__(
 330         "\n661: or              %0, %2, %0\n"
 331         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 332         "       .word           661b\n"
 333         "       or              %0, %3, %0\n"
 334         "       .previous\n"
 335         : "=r" (off)
 336         : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 337
 338         return __pte(off);
 339 }
 340
 341 static inline pgprot_t pgprot_noncached(pgprot_t prot)
 342 {
 343         unsigned long val = pgprot_val(prot);
 344
 345         __asm__ __volatile__(
 346         "\n661: andn            %0, %2, %0\n"
 347         "       or              %0, %3, %0\n"
 348         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 349         "       .word           661b\n"
 350         "       andn            %0, %4, %0\n"
 351         "       or              %0, %5, %0\n"
 352         "       .previous\n"
 353         : "=r" (val)
 354         : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
 355                      "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
 356
 357         return __pgprot(val);
 358 }
 359 /* Various pieces of code check for platform support by ifdef testing
 360  * on "pgprot_noncached".  That's broken and should be fixed, but for
 361  * now...
 362  */
 363 #define pgprot_noncached pgprot_noncached
 364
 365 #ifdef CONFIG_HUGETLB_PAGE
 366 static inline pte_t pte_mkhuge(pte_t pte)
 367 {
 368         unsigned long mask;
 369
 370         __asm__ __volatile__(
 371         "\n661: sethi           %%uhi(%1), %0\n"
 372         "       sllx            %0, 32, %0\n"
 373         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 374         "       .word           661b\n"
 375         "       mov             %2, %0\n"
 376         "       nop\n"
 377         "       .previous\n"
 378         : "=r" (mask)
 379         : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
 380
 381         return __pte(pte_val(pte) | mask);
 382 }
 383 #endif
 384
 385 static inline pte_t pte_mkdirty(pte_t pte)
 386 {
 387         unsigned long val = pte_val(pte), tmp;
 388
 389         __asm__ __volatile__(
 390         "\n661: or              %0, %3, %0\n"
 391         "       nop\n"
 392         "\n662: nop\n"
 393         "       nop\n"
 394         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 395         "       .word           661b\n"
 396         "       sethi           %%uhi(%4), %1\n"
 397         "       sllx            %1, 32, %1\n"
 398         "       .word           662b\n"
 399         "       or              %1, %%lo(%4), %1\n"
 400         "       or              %0, %1, %0\n"
 401         "       .previous\n"
 402         : "=r" (val), "=r" (tmp)
 403         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 404           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 405
 406         return __pte(val);
 407 }
 408
 409 static inline pte_t pte_mkclean(pte_t pte)
 410 {
 411         unsigned long val = pte_val(pte), tmp;
 412
 413         __asm__ __volatile__(
 414         "\n661: andn            %0, %3, %0\n"
 415         "       nop\n"
 416         "\n662: nop\n"
 417         "       nop\n"
 418         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 419         "       .word           661b\n"
 420         "       sethi           %%uhi(%4), %1\n"
 421         "       sllx            %1, 32, %1\n"
 422         "       .word           662b\n"
 423         "       or              %1, %%lo(%4), %1\n"
 424         "       andn            %0, %1, %0\n"
 425         "       .previous\n"
 426         : "=r" (val), "=r" (tmp)
 427         : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
 428           "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
 429
 430         return __pte(val);
 431 }
 432
 433 static inline pte_t pte_mkwrite(pte_t pte)
 434 {
 435         unsigned long val = pte_val(pte), mask;
 436
 437         __asm__ __volatile__(
 438         "\n661: mov             %1, %0\n"
 439         "       nop\n"
 440         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 441         "       .word           661b\n"
 442         "       sethi           %%uhi(%2), %0\n"
 443         "       sllx            %0, 32, %0\n"
 444         "       .previous\n"
 445         : "=r" (mask)
 446         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 447
 448         return __pte(val | mask);
 449 }
 450
 451 static inline pte_t pte_wrprotect(pte_t pte)
 452 {
 453         unsigned long val = pte_val(pte), tmp;
 454
 455         __asm__ __volatile__(
 456         "\n661: andn            %0, %3, %0\n"
 457         "       nop\n"
 458         "\n662: nop\n"
 459         "       nop\n"
 460         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 461         "       .word           661b\n"
 462         "       sethi           %%uhi(%4), %1\n"
 463         "       sllx            %1, 32, %1\n"
 464         "       .word           662b\n"
 465         "       or              %1, %%lo(%4), %1\n"
 466         "       andn            %0, %1, %0\n"
 467         "       .previous\n"
 468         : "=r" (val), "=r" (tmp)
 469         : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
 470           "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
 471
 472         return __pte(val);
 473 }
 474
 475 static inline pte_t pte_mkold(pte_t pte)
 476 {
 477         unsigned long mask;
 478
 479         __asm__ __volatile__(
 480         "\n661: mov             %1, %0\n"
 481         "       nop\n"
 482         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 483         "       .word           661b\n"
 484         "       sethi           %%uhi(%2), %0\n"
 485         "       sllx            %0, 32, %0\n"
 486         "       .previous\n"
 487         : "=r" (mask)
 488         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 489
 490         mask |= _PAGE_R;
 491
 492         return __pte(pte_val(pte) & ~mask);
 493 }
 494
 495 static inline pte_t pte_mkyoung(pte_t pte)
 496 {
 497         unsigned long mask;
 498
 499         __asm__ __volatile__(
 500         "\n661: mov             %1, %0\n"
 501         "       nop\n"
 502         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 503         "       .word           661b\n"
 504         "       sethi           %%uhi(%2), %0\n"
 505         "       sllx            %0, 32, %0\n"
 506         "       .previous\n"
 507         : "=r" (mask)
 508         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 509
 510         mask |= _PAGE_R;
 511
 512         return __pte(pte_val(pte) | mask);
 513 }
 514
 515 static inline pte_t pte_mkspecial(pte_t pte)
 516 {
 517         pte_val(pte) |= _PAGE_SPECIAL;
 518         return pte;
 519 }
 520
 521 static inline unsigned long pte_young(pte_t pte)
 522 {
 523         unsigned long mask;
 524
 525         __asm__ __volatile__(
 526         "\n661: mov             %1, %0\n"
 527         "       nop\n"
 528         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 529         "       .word           661b\n"
 530         "       sethi           %%uhi(%2), %0\n"
 531         "       sllx            %0, 32, %0\n"
 532         "       .previous\n"
 533         : "=r" (mask)
 534         : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
 535
 536         return (pte_val(pte) & mask);
 537 }
 538
 539 static inline unsigned long pte_dirty(pte_t pte)
 540 {
 541         unsigned long mask;
 542
 543         __asm__ __volatile__(
 544         "\n661: mov             %1, %0\n"
 545         "       nop\n"
 546         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 547         "       .word           661b\n"
 548         "       sethi           %%uhi(%2), %0\n"
 549         "       sllx            %0, 32, %0\n"
 550         "       .previous\n"
 551         : "=r" (mask)
 552         : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
 553
 554         return (pte_val(pte) & mask);
 555 }
 556
 557 static inline unsigned long pte_write(pte_t pte)
 558 {
 559         unsigned long mask;
 560
 561         __asm__ __volatile__(
 562         "\n661: mov             %1, %0\n"
 563         "       nop\n"
 564         "       .section        .sun4v_2insn_patch, \"ax\"\n"
 565         "       .word           661b\n"
 566         "       sethi           %%uhi(%2), %0\n"
 567         "       sllx            %0, 32, %0\n"
 568         "       .previous\n"
 569         : "=r" (mask)
 570         : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
 571
 572         return (pte_val(pte) & mask);
 573 }
 574
 575 static inline unsigned long pte_exec(pte_t pte)
 576 {
 577         unsigned long mask;
 578
 579         __asm__ __volatile__(
 580         "\n661: sethi           %%hi(%1), %0\n"
 581         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 582         "       .word           661b\n"
 583         "       mov             %2, %0\n"
 584         "       .previous\n"
 585         : "=r" (mask)
 586         : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
 587
 588         return (pte_val(pte) & mask);
 589 }
 590
 591 static inline unsigned long pte_file(pte_t pte)
 592 {
 593         unsigned long val = pte_val(pte);
 594
 595         __asm__ __volatile__(
 596         "\n661: and             %0, %2, %0\n"
 597         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 598         "       .word           661b\n"
 599         "       and             %0, %3, %0\n"
 600         "       .previous\n"
 601         : "=r" (val)
 602         : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
 603
 604         return val;
 605 }
 606
 607 static inline unsigned long pte_present(pte_t pte)
 608 {
 609         unsigned long val = pte_val(pte);
 610
 611         __asm__ __volatile__(
 612         "\n661: and             %0, %2, %0\n"
 613         "       .section        .sun4v_1insn_patch, \"ax\"\n"
 614         "       .word           661b\n"
 615         "       and             %0, %3, %0\n"
 616         "       .previous\n"
 617         : "=r" (val)
 618         : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
 619
 620         return val;
 621 }
 622
 623 #define pte_accessible pte_accessible
 624 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
 625 {
 626         return pte_val(a) & _PAGE_VALID;
 627 }
 628
 629 static inline unsigned long pte_special(pte_t pte)
 630 {
 631         return pte_val(pte) & _PAGE_SPECIAL;
 632 }
 633
 634 static inline int pmd_large(pmd_t pmd)
 635 {
 636         return (pmd_val(pmd) & (PMD_ISHUGE | PMD_HUGE_PRESENT)) ==
 637                 (PMD_ISHUGE | PMD_HUGE_PRESENT);
 638 }
 639
 640 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 641 static inline int pmd_young(pmd_t pmd)
 642 {
 643         return pmd_val(pmd) & PMD_HUGE_ACCESSED;
 644 }
 645
 646 static inline int pmd_write(pmd_t pmd)
 647 {
 648         return pmd_val(pmd) & PMD_HUGE_WRITE;
 649 }
 650
 651 static inline unsigned long pmd_pfn(pmd_t pmd)
 652 {
 653         unsigned long val = pmd_val(pmd) & PMD_HUGE_PADDR;
 654
 655         return val >> (PAGE_SHIFT - PMD_PADDR_SHIFT);
 656 }
 657
 658 static inline int pmd_trans_splitting(pmd_t pmd)
 659 {
 660         return (pmd_val(pmd) & (PMD_ISHUGE|PMD_HUGE_SPLITTING)) ==
 661                 (PMD_ISHUGE|PMD_HUGE_SPLITTING);
 662 }
 663
 664 static inline int pmd_trans_huge(pmd_t pmd)
 665 {
 666         return pmd_val(pmd) & PMD_ISHUGE;
 667 }
 668
 669 #define has_transparent_hugepage() 1
 670
 671 static inline pmd_t pmd_mkold(pmd_t pmd)
 672 {
 673         pmd_val(pmd) &= ~PMD_HUGE_ACCESSED;
 674         return pmd;
 675 }
 676
 677 static inline pmd_t pmd_wrprotect(pmd_t pmd)
 678 {
 679         pmd_val(pmd) &= ~PMD_HUGE_WRITE;
 680         return pmd;
 681 }
 682
 683 static inline pmd_t pmd_mkdirty(pmd_t pmd)
 684 {
 685         pmd_val(pmd) |= PMD_HUGE_DIRTY;
 686         return pmd;
 687 }
 688
 689 static inline pmd_t pmd_mkyoung(pmd_t pmd)
 690 {
 691         pmd_val(pmd) |= PMD_HUGE_ACCESSED;
 692         return pmd;
 693 }
 694
 695 static inline pmd_t pmd_mkwrite(pmd_t pmd)
 696 {
 697         pmd_val(pmd) |= PMD_HUGE_WRITE;
 698         return pmd;
 699 }
 700
 701 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
 702 {
 703         pmd_val(pmd) &= ~PMD_HUGE_PRESENT;
 704         return pmd;
 705 }
 706
 707 static inline pmd_t pmd_mksplitting(pmd_t pmd)
 708 {
 709         pmd_val(pmd) |= PMD_HUGE_SPLITTING;
 710         return pmd;
 711 }
 712
 713 extern pgprot_t pmd_pgprot(pmd_t entry);
 714 #endif
 715
 716 static inline int pmd_present(pmd_t pmd)
 717 {
 718         return pmd_val(pmd) != 0U;
 719 }
 720
 721 #define pmd_none(pmd)                   (!pmd_val(pmd))
 722
 723 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 724 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
 725                        pmd_t *pmdp, pmd_t pmd);
 726 #else
 727 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
 728                               pmd_t *pmdp, pmd_t pmd)
 729 {
 730         *pmdp = pmd;
 731 }
 732 #endif
 733
 734 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 735 {
 736         unsigned long val = __pa((unsigned long) (ptep)) >> PMD_PADDR_SHIFT;
 737
 738         pmd_val(*pmdp) = val;
 739 }
 740
 741 #define pud_set(pudp, pmdp)     \
 742         (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> PGD_PADDR_SHIFT))
 743 static inline unsigned long __pmd_page(pmd_t pmd)
 744 {
 745         unsigned long paddr = (unsigned long) pmd_val(pmd);
 746 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 747         if (pmd_val(pmd) & PMD_ISHUGE)
 748                 paddr &= PMD_HUGE_PADDR;
 749 #endif
 750         paddr <<= PMD_PADDR_SHIFT;
 751         return ((unsigned long) __va(paddr));
 752 }
 753 #define pmd_page(pmd)                   virt_to_page((void *)__pmd_page(pmd))
 754 #define pud_page_vaddr(pud)             \
 755         ((unsigned long) __va((((unsigned long)pud_val(pud))<<PGD_PADDR_SHIFT)))
 756 #define pud_page(pud)                   virt_to_page((void *)pud_page_vaddr(pud))
 757 #define pmd_bad(pmd)                    (0)
 758 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0U)
 759 #define pud_none(pud)                   (!pud_val(pud))
 760 #define pud_bad(pud)                    (0)
 761 #define pud_present(pud)                (pud_val(pud) != 0U)
 762 #define pud_clear(pudp)                 (pud_val(*(pudp)) = 0U)
 763
 764 /* Same in both SUN4V and SUN4U.  */
 765 #define pte_none(pte)                   (!pte_val(pte))
 766
 767 /* to find an entry in a page-table-directory. */
 768 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 769 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 770
 771 /* to find an entry in a kernel page-table-directory */
 772 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 773
 774 /* Find an entry in the second-level page table.. */
 775 #define pmd_offset(pudp, address)       \
 776         ((pmd_t *) pud_page_vaddr(*(pudp)) + \
 777          (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
 778
 779 /* Find an entry in the third-level page table.. */
 780 #define pte_index(dir, address) \
 781         ((pte_t *) __pmd_page(*(dir)) + \
 782          ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 783 #define pte_offset_kernel               pte_index
 784 #define pte_offset_map                  pte_index
 785 #define pte_unmap(pte)                  do { } while (0)
 786
 787 /* Actual page table PTE updates.  */
 788 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
 789                           pte_t *ptep, pte_t orig, int fullmm);
 790
 791 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
 792 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
 793                                        unsigned long addr,
 794                                        pmd_t *pmdp)
 795 {
 796         pmd_t pmd = *pmdp;
 797         set_pmd_at(mm, addr, pmdp, __pmd(0U));
 798         return pmd;
 799 }
 800
 801 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 802                              pte_t *ptep, pte_t pte, int fullmm)
 803 {
 804         pte_t orig = *ptep;
 805
 806         *ptep = pte;
 807
 808         /* It is more efficient to let flush_tlb_kernel_range()
 809          * handle init_mm tlb flushes.
 810          *
 811          * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
 812          *             and SUN4V pte layout, so this inline test is fine.
 813          */
 814         if (likely(mm != &init_mm) && pte_accessible(mm, orig))
 815                 tlb_batch_add(mm, addr, ptep, orig, fullmm);
 816 }
 817
 818 #define set_pte_at(mm,addr,ptep,pte)    \
 819         __set_pte_at((mm), (addr), (ptep), (pte), 0)
 820
 821 #define pte_clear(mm,addr,ptep)         \
 822         set_pte_at((mm), (addr), (ptep), __pte(0UL))
 823
 824 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
 825 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
 826         __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
 827
 828 #ifdef DCACHE_ALIASING_POSSIBLE
 829 #define __HAVE_ARCH_MOVE_PTE
 830 #define move_pte(pte, prot, old_addr, new_addr)                         \
 831 ({                                                                      \
 832         pte_t newpte = (pte);                                           \
 833         if (tlb_type != hypervisor && pte_present(pte)) {               \
 834                 unsigned long this_pfn = pte_pfn(pte);                  \
 835                                                                         \
 836                 if (pfn_valid(this_pfn) &&                              \
 837                     (((old_addr) ^ (new_addr)) & (1 << 13)))            \
 838                         flush_dcache_page_all(current->mm,              \
 839                                               pfn_to_page(this_pfn));   \
 840         }                                                               \
 841         newpte;                                                         \
 842 })
 843 #endif
 844
 845 extern pgd_t swapper_pg_dir[2048];
 846 extern pmd_t swapper_low_pmd_dir[2048];
 847
 848 extern void paging_init(void);
 849 extern unsigned long find_ecache_flush_span(unsigned long size);
 850
 851 struct seq_file;
 852 extern void mmu_info(struct seq_file *);
 853
 854 struct vm_area_struct;
 855 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 856 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 857 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
 858                                  pmd_t *pmd);
 859
 860 #define __HAVE_ARCH_PGTABLE_DEPOSIT
 861 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 862                                        pgtable_t pgtable);
 863
 864 #define __HAVE_ARCH_PGTABLE_WITHDRAW
 865 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 866 #endif
 867
 868 /* Encode and de-code a swap entry */
 869 #define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
 870 #define __swp_offset(entry)     ((entry).val >> (PAGE_SHIFT + 8UL))
 871 #define __swp_entry(type, offset)       \
 872         ( (swp_entry_t) \
 873           { \
 874                 (((long)(type) << PAGE_SHIFT) | \
 875                  ((long)(offset) << (PAGE_SHIFT + 8UL))) \
 876           } )
 877 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 878 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 879
 880 /* File offset in PTE support. */
 881 extern unsigned long pte_file(pte_t);
 882 #define pte_to_pgoff(pte)       (pte_val(pte) >> PAGE_SHIFT)
 883 extern pte_t pgoff_to_pte(unsigned long);
 884 #define PTE_FILE_MAX_BITS       (64UL - PAGE_SHIFT - 1UL)
 885
 886 extern unsigned long sparc64_valid_addr_bitmap[];
 887
 888 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 889 static inline bool kern_addr_valid(unsigned long addr)
 890 {
 891         unsigned long paddr = __pa(addr);
 892
 893         if ((paddr >> 41UL) != 0UL)
 894                 return false;
 895         return test_bit(paddr >> 22, sparc64_valid_addr_bitmap);
 896 }
 897
 898 extern int page_in_phys_avail(unsigned long paddr);
 899
 900 /*
 901  * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 902  * its high 4 bits.  These macros/functions put it there or get it from there.
 903  */
 904 #define MK_IOSPACE_PFN(space, pfn)      (pfn | (space << (BITS_PER_LONG - 4)))
 905 #define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
 906 #define GET_PFN(pfn)                    (pfn & 0x0fffffffffffffffUL)
 907
 908 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
 909                            unsigned long, pgprot_t);
 910
 911 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 912                                      unsigned long from, unsigned long pfn,
 913                                      unsigned long size, pgprot_t prot)
 914 {
 915         unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
 916         int space = GET_IOSPACE(pfn);
 917         unsigned long phys_base;
 918
 919         phys_base = offset | (((unsigned long) space) << 32UL);
 920
 921         return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
 922 }
 923 #define io_remap_pfn_range io_remap_pfn_range
 924
 925 #include <asm/tlbflush.h>
 926 #include <asm-generic/pgtable.h>
 927
 928 /* We provide our own get_unmapped_area to cope with VA holes and
 929  * SHM area cache aliasing for userland.
 930  */
 931 #define HAVE_ARCH_UNMAPPED_AREA
 932 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 933
 934 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
 935  * the largest alignment possible such that larget PTEs can be used.
 936  */
 937 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
 938                                           unsigned long, unsigned long,
 939                                           unsigned long);
 940 #define HAVE_ARCH_FB_UNMAPPED_AREA
 941
 942 extern void pgtable_cache_init(void);
 943 extern void sun4v_register_fault_status(void);
 944 extern void sun4v_ktsb_register(void);
 945 extern void __init cheetah_ecache_flush_init(void);
 946 extern void sun4v_patch_tlb_handlers(void);
 947
 948 extern unsigned long cmdline_memory_size;
 949
 950 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
 951
 952 #endif /* !(__ASSEMBLY__) */
 953
 954 #endif /* !(_SPARC64_PGTABLE_H) */