2 * include/asm/processor.h
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 #ifndef __ASM_SPARC64_PROCESSOR_H
8 #define __ASM_SPARC64_PROCESSOR_H
11 * Sparc64 implementation of macro that returns current
12 * instruction pointer ("program counter").
14 #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
17 #include <asm/pstate.h>
18 #include <asm/ptrace.h>
21 /* The sparc has no problems with write protection */
23 #define wp_works_ok__is_a_macro /* for versions in ksyms.c */
26 * User lives in his very own context, and cannot reference us. Note
27 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
28 * address that the kernel will allocate out.
30 * XXX No longer using virtual page tables, kill this upper limit...
34 #define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
36 #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
39 #define TASK_SIZE_OF(tsk) \
40 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
41 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
43 (test_thread_flag(TIF_32BIT) ? \
44 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
47 #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
48 #define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
50 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
51 STACK_TOP32 : STACK_TOP64)
53 #define STACK_TOP_MAX STACK_TOP64
63 /* The Sparc processor specific thread struct. */
64 /* XXX This should die, everything can go into thread_info now. */
65 struct thread_struct
{
66 #ifdef CONFIG_DEBUG_SPINLOCK
67 /* How many spinlocks held by this thread.
68 * Used with spin lock debugging to catch tasks
69 * sleeping illegally with locks held.
72 unsigned int smp_lock_pc
;
74 int dummy
; /* f'in gcc bug... */
78 #endif /* !(__ASSEMBLY__) */
80 #ifndef CONFIG_DEBUG_SPINLOCK
81 #define INIT_THREAD { \
84 #else /* CONFIG_DEBUG_SPINLOCK */
85 #define INIT_THREAD { \
86 /* smp_lock_count, smp_lock_pc, */ \
89 #endif /* !(CONFIG_DEBUG_SPINLOCK) */
93 #include <linux/types.h>
94 #include <asm/fpumacro.h>
96 /* Return saved PC of a blocked thread. */
98 extern unsigned long thread_saved_pc(struct task_struct
*);
100 /* On Uniprocessor, even in RMO processes see TSO semantics */
102 #define TSTATE_INITIAL_MM TSTATE_TSO
104 #define TSTATE_INITIAL_MM TSTATE_RMO
107 /* Do necessary setup to start up a newly executed thread. */
108 #define start_thread(regs, pc, sp) \
110 unsigned long __asi = ASI_PNF; \
111 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
112 regs->tpc = ((pc & (~3)) - 4); \
113 regs->tnpc = regs->tpc + 4; \
115 set_thread_wstate(1 << 3); \
116 if (current_thread_info()->utraps) { \
117 if (*(current_thread_info()->utraps) < 2) \
118 kfree(current_thread_info()->utraps); \
120 (*(current_thread_info()->utraps))--; \
121 current_thread_info()->utraps = NULL; \
123 __asm__ __volatile__( \
124 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
125 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
126 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
132 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
133 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
134 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
135 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
136 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
137 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
138 "stx %1, [%0 + %2 + 0x70]\n\t" \
139 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
140 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
142 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
143 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
145 current_thread_info()->xfsr[0] = 0; \
146 current_thread_info()->fpsaved[0] = 0; \
147 regs->tstate &= ~TSTATE_PEF; \
150 #define start_thread32(regs, pc, sp) \
152 unsigned long __asi = ASI_PNF; \
153 pc &= 0x00000000ffffffffUL; \
154 sp &= 0x00000000ffffffffUL; \
155 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
156 regs->tpc = ((pc & (~3)) - 4); \
157 regs->tnpc = regs->tpc + 4; \
159 set_thread_wstate(2 << 3); \
160 if (current_thread_info()->utraps) { \
161 if (*(current_thread_info()->utraps) < 2) \
162 kfree(current_thread_info()->utraps); \
164 (*(current_thread_info()->utraps))--; \
165 current_thread_info()->utraps = NULL; \
167 __asm__ __volatile__( \
168 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
172 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
174 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
175 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
176 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
177 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
178 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
179 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
180 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
181 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
182 "stx %1, [%0 + %2 + 0x70]\n\t" \
183 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
184 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
186 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
187 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
189 current_thread_info()->xfsr[0] = 0; \
190 current_thread_info()->fpsaved[0] = 0; \
191 regs->tstate &= ~TSTATE_PEF; \
194 /* Free all resources held by a thread. */
195 #define release_thread(tsk) do { } while (0)
197 extern unsigned long get_wchan(struct task_struct
*task
);
199 #define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
200 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
201 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
203 /* Please see the commentary in asm/backoff.h for a description of
204 * what these instructions are doing and how they have been choosen.
205 * To make a long story short, we are trying to yield the current cpu
206 * strand during busy loops.
208 #define cpu_relax() asm volatile("\n99:\n\t" \
209 "rd %%ccr, %%g0\n\t" \
210 "rd %%ccr, %%g0\n\t" \
211 "rd %%ccr, %%g0\n\t" \
212 ".section .pause_3insn_patch,\"ax\"\n\t"\
214 "wr %%g0, 128, %%asr27\n\t" \
220 /* Prefetch support. This is tuned for UltraSPARC-III and later.
221 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
222 * a shallower prefetch queue than later chips.
224 #define ARCH_HAS_PREFETCH
225 #define ARCH_HAS_PREFETCHW
226 #define ARCH_HAS_SPINLOCK_PREFETCH
228 static inline void prefetch(const void *x
)
230 /* We do not use the read prefetch mnemonic because that
231 * prefetches into the prefetch-cache which only is accessible
232 * by floating point operations in UltraSPARC-III and later.
233 * By contrast, "#one_write" prefetches into the L2 cache
236 __asm__
__volatile__("prefetch [%0], #one_write"
241 static inline void prefetchw(const void *x
)
243 /* The most optimal prefetch to use for writes is
244 * "#n_writes". This brings the cacheline into the
245 * L2 cache in "owned" state.
247 __asm__
__volatile__("prefetch [%0], #n_writes"
252 #define spin_lock_prefetch(x) prefetchw(x)
254 #define HAVE_ARCH_PICK_MMAP_LAYOUT
256 #endif /* !(__ASSEMBLY__) */
258 #endif /* !(__ASM_SPARC64_PROCESSOR_H) */