1 /* irq.c: UltraSparc IRQ handling/init/registry.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/sched.h>
9 #include <linux/linkage.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/ftrace.h>
23 #include <linux/irq.h>
24 #include <linux/kmemleak.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <linux/atomic.h>
31 #include <asm/iommu.h>
33 #include <asm/oplib.h>
35 #include <asm/timer.h>
37 #include <asm/starfire.h>
38 #include <asm/uaccess.h>
39 #include <asm/cache.h>
40 #include <asm/cpudata.h>
41 #include <asm/auxio.h>
43 #include <asm/hypervisor.h>
44 #include <asm/cacheflush.h>
50 #define NUM_IVECS (IMAP_INR + 1)
52 struct ino_bucket
*ivector_table
;
53 unsigned long ivector_table_pa
;
55 /* On several sun4u processors, it is illegal to mix bypass and
56 * non-bypass accesses. Therefore we access all INO buckets
57 * using bypass accesses only.
59 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa
)
63 __asm__
__volatile__("ldxa [%1] %2, %0"
66 offsetof(struct ino_bucket
,
68 "i" (ASI_PHYS_USE_EC
));
73 static void bucket_clear_chain_pa(unsigned long bucket_pa
)
75 __asm__
__volatile__("stxa %%g0, [%0] %1"
78 offsetof(struct ino_bucket
,
80 "i" (ASI_PHYS_USE_EC
));
83 static unsigned int bucket_get_irq(unsigned long bucket_pa
)
87 __asm__
__volatile__("lduwa [%1] %2, %0"
90 offsetof(struct ino_bucket
,
92 "i" (ASI_PHYS_USE_EC
));
97 static void bucket_set_irq(unsigned long bucket_pa
, unsigned int irq
)
99 __asm__
__volatile__("stwa %0, [%1] %2"
103 offsetof(struct ino_bucket
,
105 "i" (ASI_PHYS_USE_EC
));
108 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
111 unsigned int dev_handle
;
112 unsigned int dev_ino
;
114 } irq_table
[NR_IRQS
];
115 static DEFINE_SPINLOCK(irq_alloc_lock
);
117 unsigned char irq_alloc(unsigned int dev_handle
, unsigned int dev_ino
)
122 BUILD_BUG_ON(NR_IRQS
>= 256);
124 spin_lock_irqsave(&irq_alloc_lock
, flags
);
126 for (ent
= 1; ent
< NR_IRQS
; ent
++) {
127 if (!irq_table
[ent
].in_use
)
130 if (ent
>= NR_IRQS
) {
131 printk(KERN_ERR
"IRQ: Out of virtual IRQs.\n");
134 irq_table
[ent
].dev_handle
= dev_handle
;
135 irq_table
[ent
].dev_ino
= dev_ino
;
136 irq_table
[ent
].in_use
= 1;
139 spin_unlock_irqrestore(&irq_alloc_lock
, flags
);
144 #ifdef CONFIG_PCI_MSI
145 void irq_free(unsigned int irq
)
152 spin_lock_irqsave(&irq_alloc_lock
, flags
);
154 irq_table
[irq
].in_use
= 0;
156 spin_unlock_irqrestore(&irq_alloc_lock
, flags
);
161 * /proc/interrupts printing:
163 int arch_show_interrupts(struct seq_file
*p
, int prec
)
167 seq_printf(p
, "NMI: ");
168 for_each_online_cpu(j
)
169 seq_printf(p
, "%10u ", cpu_data(j
).__nmi_count
);
170 seq_printf(p
, " Non-maskable interrupts\n");
174 static unsigned int sun4u_compute_tid(unsigned long imap
, unsigned long cpuid
)
178 if (this_is_starfire
) {
179 tid
= starfire_translate(imap
, cpuid
);
180 tid
<<= IMAP_TID_SHIFT
;
183 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
186 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
187 if ((ver
>> 32UL) == __JALAPENO_ID
||
188 (ver
>> 32UL) == __SERRANO_ID
) {
189 tid
= cpuid
<< IMAP_TID_SHIFT
;
190 tid
&= IMAP_TID_JBUS
;
192 unsigned int a
= cpuid
& 0x1f;
193 unsigned int n
= (cpuid
>> 5) & 0x1f;
195 tid
= ((a
<< IMAP_AID_SHIFT
) |
196 (n
<< IMAP_NID_SHIFT
));
197 tid
&= (IMAP_AID_SAFARI
|
201 tid
= cpuid
<< IMAP_TID_SHIFT
;
209 struct irq_handler_data
{
213 void (*pre_handler
)(unsigned int, void *, void *);
219 static int irq_choose_cpu(unsigned int irq
, const struct cpumask
*affinity
)
224 cpumask_copy(&mask
, affinity
);
225 if (cpumask_equal(&mask
, cpu_online_mask
)) {
226 cpuid
= map_to_cpu(irq
);
230 cpumask_and(&tmp
, cpu_online_mask
, &mask
);
231 cpuid
= cpumask_empty(&tmp
) ? map_to_cpu(irq
) : cpumask_first(&tmp
);
237 #define irq_choose_cpu(irq, affinity) \
238 real_hard_smp_processor_id()
241 static void sun4u_irq_enable(struct irq_data
*data
)
243 struct irq_handler_data
*handler_data
= data
->handler_data
;
245 if (likely(handler_data
)) {
246 unsigned long cpuid
, imap
, val
;
249 cpuid
= irq_choose_cpu(data
->irq
, data
->affinity
);
250 imap
= handler_data
->imap
;
252 tid
= sun4u_compute_tid(imap
, cpuid
);
254 val
= upa_readq(imap
);
255 val
&= ~(IMAP_TID_UPA
| IMAP_TID_JBUS
|
256 IMAP_AID_SAFARI
| IMAP_NID_SAFARI
);
257 val
|= tid
| IMAP_VALID
;
258 upa_writeq(val
, imap
);
259 upa_writeq(ICLR_IDLE
, handler_data
->iclr
);
263 static int sun4u_set_affinity(struct irq_data
*data
,
264 const struct cpumask
*mask
, bool force
)
266 struct irq_handler_data
*handler_data
= data
->handler_data
;
268 if (likely(handler_data
)) {
269 unsigned long cpuid
, imap
, val
;
272 cpuid
= irq_choose_cpu(data
->irq
, mask
);
273 imap
= handler_data
->imap
;
275 tid
= sun4u_compute_tid(imap
, cpuid
);
277 val
= upa_readq(imap
);
278 val
&= ~(IMAP_TID_UPA
| IMAP_TID_JBUS
|
279 IMAP_AID_SAFARI
| IMAP_NID_SAFARI
);
280 val
|= tid
| IMAP_VALID
;
281 upa_writeq(val
, imap
);
282 upa_writeq(ICLR_IDLE
, handler_data
->iclr
);
288 /* Don't do anything. The desc->status check for IRQ_DISABLED in
289 * handler_irq() will skip the handler call and that will leave the
290 * interrupt in the sent state. The next ->enable() call will hit the
291 * ICLR register to reset the state machine.
293 * This scheme is necessary, instead of clearing the Valid bit in the
294 * IMAP register, to handle the case of IMAP registers being shared by
295 * multiple INOs (and thus ICLR registers). Since we use a different
296 * virtual IRQ for each shared IMAP instance, the generic code thinks
297 * there is only one user so it prematurely calls ->disable() on
300 * We have to provide an explicit ->disable() method instead of using
301 * NULL to get the default. The reason is that if the generic code
302 * sees that, it also hooks up a default ->shutdown method which
303 * invokes ->mask() which we do not want. See irq_chip_set_defaults().
305 static void sun4u_irq_disable(struct irq_data
*data
)
309 static void sun4u_irq_eoi(struct irq_data
*data
)
311 struct irq_handler_data
*handler_data
= data
->handler_data
;
313 if (likely(handler_data
))
314 upa_writeq(ICLR_IDLE
, handler_data
->iclr
);
317 static void sun4v_irq_enable(struct irq_data
*data
)
319 unsigned int ino
= irq_table
[data
->irq
].dev_ino
;
320 unsigned long cpuid
= irq_choose_cpu(data
->irq
, data
->affinity
);
323 err
= sun4v_intr_settarget(ino
, cpuid
);
325 printk(KERN_ERR
"sun4v_intr_settarget(%x,%lu): "
326 "err(%d)\n", ino
, cpuid
, err
);
327 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
329 printk(KERN_ERR
"sun4v_intr_setstate(%x): "
330 "err(%d)\n", ino
, err
);
331 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
333 printk(KERN_ERR
"sun4v_intr_setenabled(%x): err(%d)\n",
337 static int sun4v_set_affinity(struct irq_data
*data
,
338 const struct cpumask
*mask
, bool force
)
340 unsigned int ino
= irq_table
[data
->irq
].dev_ino
;
341 unsigned long cpuid
= irq_choose_cpu(data
->irq
, mask
);
344 err
= sun4v_intr_settarget(ino
, cpuid
);
346 printk(KERN_ERR
"sun4v_intr_settarget(%x,%lu): "
347 "err(%d)\n", ino
, cpuid
, err
);
352 static void sun4v_irq_disable(struct irq_data
*data
)
354 unsigned int ino
= irq_table
[data
->irq
].dev_ino
;
357 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
359 printk(KERN_ERR
"sun4v_intr_setenabled(%x): "
360 "err(%d)\n", ino
, err
);
363 static void sun4v_irq_eoi(struct irq_data
*data
)
365 unsigned int ino
= irq_table
[data
->irq
].dev_ino
;
368 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
370 printk(KERN_ERR
"sun4v_intr_setstate(%x): "
371 "err(%d)\n", ino
, err
);
374 static void sun4v_virq_enable(struct irq_data
*data
)
376 unsigned long cpuid
, dev_handle
, dev_ino
;
379 cpuid
= irq_choose_cpu(data
->irq
, data
->affinity
);
381 dev_handle
= irq_table
[data
->irq
].dev_handle
;
382 dev_ino
= irq_table
[data
->irq
].dev_ino
;
384 err
= sun4v_vintr_set_target(dev_handle
, dev_ino
, cpuid
);
386 printk(KERN_ERR
"sun4v_vintr_set_target(%lx,%lx,%lu): "
388 dev_handle
, dev_ino
, cpuid
, err
);
389 err
= sun4v_vintr_set_state(dev_handle
, dev_ino
,
392 printk(KERN_ERR
"sun4v_vintr_set_state(%lx,%lx,"
393 "HV_INTR_STATE_IDLE): err(%d)\n",
394 dev_handle
, dev_ino
, err
);
395 err
= sun4v_vintr_set_valid(dev_handle
, dev_ino
,
398 printk(KERN_ERR
"sun4v_vintr_set_state(%lx,%lx,"
399 "HV_INTR_ENABLED): err(%d)\n",
400 dev_handle
, dev_ino
, err
);
403 static int sun4v_virt_set_affinity(struct irq_data
*data
,
404 const struct cpumask
*mask
, bool force
)
406 unsigned long cpuid
, dev_handle
, dev_ino
;
409 cpuid
= irq_choose_cpu(data
->irq
, mask
);
411 dev_handle
= irq_table
[data
->irq
].dev_handle
;
412 dev_ino
= irq_table
[data
->irq
].dev_ino
;
414 err
= sun4v_vintr_set_target(dev_handle
, dev_ino
, cpuid
);
416 printk(KERN_ERR
"sun4v_vintr_set_target(%lx,%lx,%lu): "
418 dev_handle
, dev_ino
, cpuid
, err
);
423 static void sun4v_virq_disable(struct irq_data
*data
)
425 unsigned long dev_handle
, dev_ino
;
428 dev_handle
= irq_table
[data
->irq
].dev_handle
;
429 dev_ino
= irq_table
[data
->irq
].dev_ino
;
431 err
= sun4v_vintr_set_valid(dev_handle
, dev_ino
,
434 printk(KERN_ERR
"sun4v_vintr_set_state(%lx,%lx,"
435 "HV_INTR_DISABLED): err(%d)\n",
436 dev_handle
, dev_ino
, err
);
439 static void sun4v_virq_eoi(struct irq_data
*data
)
441 unsigned long dev_handle
, dev_ino
;
444 dev_handle
= irq_table
[data
->irq
].dev_handle
;
445 dev_ino
= irq_table
[data
->irq
].dev_ino
;
447 err
= sun4v_vintr_set_state(dev_handle
, dev_ino
,
450 printk(KERN_ERR
"sun4v_vintr_set_state(%lx,%lx,"
451 "HV_INTR_STATE_IDLE): err(%d)\n",
452 dev_handle
, dev_ino
, err
);
455 static struct irq_chip sun4u_irq
= {
457 .irq_enable
= sun4u_irq_enable
,
458 .irq_disable
= sun4u_irq_disable
,
459 .irq_eoi
= sun4u_irq_eoi
,
460 .irq_set_affinity
= sun4u_set_affinity
,
461 .flags
= IRQCHIP_EOI_IF_HANDLED
,
464 static struct irq_chip sun4v_irq
= {
466 .irq_enable
= sun4v_irq_enable
,
467 .irq_disable
= sun4v_irq_disable
,
468 .irq_eoi
= sun4v_irq_eoi
,
469 .irq_set_affinity
= sun4v_set_affinity
,
470 .flags
= IRQCHIP_EOI_IF_HANDLED
,
473 static struct irq_chip sun4v_virq
= {
475 .irq_enable
= sun4v_virq_enable
,
476 .irq_disable
= sun4v_virq_disable
,
477 .irq_eoi
= sun4v_virq_eoi
,
478 .irq_set_affinity
= sun4v_virt_set_affinity
,
479 .flags
= IRQCHIP_EOI_IF_HANDLED
,
482 static void pre_flow_handler(struct irq_data
*d
)
484 struct irq_handler_data
*handler_data
= irq_data_get_irq_handler_data(d
);
485 unsigned int ino
= irq_table
[d
->irq
].dev_ino
;
487 handler_data
->pre_handler(ino
, handler_data
->arg1
, handler_data
->arg2
);
490 void irq_install_pre_handler(int irq
,
491 void (*func
)(unsigned int, void *, void *),
492 void *arg1
, void *arg2
)
494 struct irq_handler_data
*handler_data
= irq_get_handler_data(irq
);
496 handler_data
->pre_handler
= func
;
497 handler_data
->arg1
= arg1
;
498 handler_data
->arg2
= arg2
;
500 __irq_set_preflow_handler(irq
, pre_flow_handler
);
503 unsigned int build_irq(int inofixup
, unsigned long iclr
, unsigned long imap
)
505 struct ino_bucket
*bucket
;
506 struct irq_handler_data
*handler_data
;
510 BUG_ON(tlb_type
== hypervisor
);
512 ino
= (upa_readq(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
513 bucket
= &ivector_table
[ino
];
514 irq
= bucket_get_irq(__pa(bucket
));
516 irq
= irq_alloc(0, ino
);
517 bucket_set_irq(__pa(bucket
), irq
);
518 irq_set_chip_and_handler_name(irq
, &sun4u_irq
,
519 handle_fasteoi_irq
, "IVEC");
522 handler_data
= irq_get_handler_data(irq
);
523 if (unlikely(handler_data
))
526 handler_data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
527 if (unlikely(!handler_data
)) {
528 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
531 irq_set_handler_data(irq
, handler_data
);
533 handler_data
->imap
= imap
;
534 handler_data
->iclr
= iclr
;
540 static unsigned int sun4v_build_common(unsigned long sysino
,
541 struct irq_chip
*chip
)
543 struct ino_bucket
*bucket
;
544 struct irq_handler_data
*handler_data
;
547 BUG_ON(tlb_type
!= hypervisor
);
549 bucket
= &ivector_table
[sysino
];
550 irq
= bucket_get_irq(__pa(bucket
));
552 irq
= irq_alloc(0, sysino
);
553 bucket_set_irq(__pa(bucket
), irq
);
554 irq_set_chip_and_handler_name(irq
, chip
, handle_fasteoi_irq
,
558 handler_data
= irq_get_handler_data(irq
);
559 if (unlikely(handler_data
))
562 handler_data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
563 if (unlikely(!handler_data
)) {
564 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
567 irq_set_handler_data(irq
, handler_data
);
569 /* Catch accidental accesses to these things. IMAP/ICLR handling
570 * is done by hypervisor calls on sun4v platforms, not by direct
573 handler_data
->imap
= ~0UL;
574 handler_data
->iclr
= ~0UL;
580 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
)
582 unsigned long sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
584 return sun4v_build_common(sysino
, &sun4v_irq
);
587 unsigned int sun4v_build_virq(u32 devhandle
, unsigned int devino
)
589 struct irq_handler_data
*handler_data
;
590 unsigned long hv_err
, cookie
;
591 struct ino_bucket
*bucket
;
594 bucket
= kzalloc(sizeof(struct ino_bucket
), GFP_ATOMIC
);
595 if (unlikely(!bucket
))
598 /* The only reference we store to the IRQ bucket is
599 * by physical address which kmemleak can't see, tell
600 * it that this object explicitly is not a leak and
603 kmemleak_not_leak(bucket
);
605 __flush_dcache_range((unsigned long) bucket
,
606 ((unsigned long) bucket
+
607 sizeof(struct ino_bucket
)));
609 irq
= irq_alloc(devhandle
, devino
);
610 bucket_set_irq(__pa(bucket
), irq
);
612 irq_set_chip_and_handler_name(irq
, &sun4v_virq
, handle_fasteoi_irq
,
615 handler_data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
616 if (unlikely(!handler_data
))
619 /* In order to make the LDC channel startup sequence easier,
620 * especially wrt. locking, we do not let request_irq() enable
623 irq_set_status_flags(irq
, IRQ_NOAUTOEN
);
624 irq_set_handler_data(irq
, handler_data
);
626 /* Catch accidental accesses to these things. IMAP/ICLR handling
627 * is done by hypervisor calls on sun4v platforms, not by direct
630 handler_data
->imap
= ~0UL;
631 handler_data
->iclr
= ~0UL;
633 cookie
= ~__pa(bucket
);
634 hv_err
= sun4v_vintr_set_cookie(devhandle
, devino
, cookie
);
636 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
637 "err=%lu\n", devhandle
, devino
, hv_err
);
644 void ack_bad_irq(unsigned int irq
)
646 unsigned int ino
= irq_table
[irq
].dev_ino
;
651 printk(KERN_CRIT
"Unexpected IRQ from ino[%x] irq[%u]\n",
655 void *hardirq_stack
[NR_CPUS
];
656 void *softirq_stack
[NR_CPUS
];
658 void __irq_entry
handler_irq(int pil
, struct pt_regs
*regs
)
660 unsigned long pstate
, bucket_pa
;
661 struct pt_regs
*old_regs
;
664 clear_softint(1 << pil
);
666 old_regs
= set_irq_regs(regs
);
669 /* Grab an atomic snapshot of the pending IVECs. */
670 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
671 "wrpr %0, %3, %%pstate\n\t"
674 "wrpr %0, 0x0, %%pstate\n\t"
675 : "=&r" (pstate
), "=&r" (bucket_pa
)
676 : "r" (irq_work_pa(smp_processor_id())),
680 orig_sp
= set_hardirq_stack();
683 unsigned long next_pa
;
686 next_pa
= bucket_get_chain_pa(bucket_pa
);
687 irq
= bucket_get_irq(bucket_pa
);
688 bucket_clear_chain_pa(bucket_pa
);
690 generic_handle_irq(irq
);
695 restore_hardirq_stack(orig_sp
);
698 set_irq_regs(old_regs
);
701 void do_softirq(void)
708 local_irq_save(flags
);
710 if (local_softirq_pending()) {
711 void *orig_sp
, *sp
= softirq_stack
[smp_processor_id()];
713 sp
+= THREAD_SIZE
- 192 - STACK_BIAS
;
715 __asm__
__volatile__("mov %%sp, %0\n\t"
720 __asm__
__volatile__("mov %0, %%sp"
724 local_irq_restore(flags
);
727 #ifdef CONFIG_HOTPLUG_CPU
728 void fixup_irqs(void)
732 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
733 struct irq_desc
*desc
= irq_to_desc(irq
);
734 struct irq_data
*data
= irq_desc_get_irq_data(desc
);
737 raw_spin_lock_irqsave(&desc
->lock
, flags
);
738 if (desc
->action
&& !irqd_is_per_cpu(data
)) {
739 if (data
->chip
->irq_set_affinity
)
740 data
->chip
->irq_set_affinity(data
,
744 raw_spin_unlock_irqrestore(&desc
->lock
, flags
);
747 tick_ops
->disable_irq();
758 static struct sun5_timer
*prom_timers
;
759 static u64 prom_limit0
, prom_limit1
;
761 static void map_prom_timers(void)
763 struct device_node
*dp
;
764 const unsigned int *addr
;
766 /* PROM timer node hangs out in the top level of device siblings... */
767 dp
= of_find_node_by_path("/");
770 if (!strcmp(dp
->name
, "counter-timer"))
775 /* Assume if node is not present, PROM uses different tick mechanism
776 * which we should not care about.
779 prom_timers
= (struct sun5_timer
*) 0;
783 /* If PROM is really using this, it must be mapped by him. */
784 addr
= of_get_property(dp
, "address", NULL
);
786 prom_printf("PROM does not have timer mapped, trying to continue.\n");
787 prom_timers
= (struct sun5_timer
*) 0;
790 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
793 static void kill_prom_timer(void)
798 /* Save them away for later. */
799 prom_limit0
= prom_timers
->limit0
;
800 prom_limit1
= prom_timers
->limit1
;
802 /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
803 * We turn both off here just to be paranoid.
805 prom_timers
->limit0
= 0;
806 prom_timers
->limit1
= 0;
808 /* Wheee, eat the interrupt packet too... */
809 __asm__
__volatile__(
811 " ldxa [%%g0] %0, %%g1\n"
812 " ldxa [%%g2] %1, %%g1\n"
813 " stxa %%g0, [%%g0] %0\n"
816 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
820 void notrace
init_irqwork_curcpu(void)
822 int cpu
= hard_smp_processor_id();
824 trap_block
[cpu
].irq_worklist_pa
= 0UL;
827 /* Please be very careful with register_one_mondo() and
828 * sun4v_register_mondo_queues().
830 * On SMP this gets invoked from the CPU trampoline before
831 * the cpu has fully taken over the trap table from OBP,
832 * and it's kernel stack + %g6 thread register state is
833 * not fully cooked yet.
835 * Therefore you cannot make any OBP calls, not even prom_printf,
836 * from these two routines.
838 static void notrace
register_one_mondo(unsigned long paddr
, unsigned long type
,
841 unsigned long num_entries
= (qmask
+ 1) / 64;
842 unsigned long status
;
844 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
845 if (status
!= HV_EOK
) {
846 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
847 "err %lu\n", type
, paddr
, num_entries
, status
);
852 void notrace
sun4v_register_mondo_queues(int this_cpu
)
854 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
856 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
,
857 tb
->cpu_mondo_qmask
);
858 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
,
859 tb
->dev_mondo_qmask
);
860 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
,
862 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
,
866 /* Each queue region must be a power of 2 multiple of 64 bytes in
867 * size. The base real address must be aligned to the size of the
868 * region. Thus, an 8KB queue must be 8KB aligned, for example.
870 static void __init
alloc_one_queue(unsigned long *pa_ptr
, unsigned long qmask
)
872 unsigned long size
= PAGE_ALIGN(qmask
+ 1);
873 unsigned long order
= get_order(size
);
876 p
= __get_free_pages(GFP_KERNEL
, order
);
878 prom_printf("SUN4V: Error, cannot allocate queue.\n");
885 static void __init
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
)
890 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
892 page
= get_zeroed_page(GFP_KERNEL
);
894 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
898 tb
->cpu_mondo_block_pa
= __pa(page
);
899 tb
->cpu_list_pa
= __pa(page
+ 64);
903 /* Allocate mondo and error queues for all possible cpus. */
904 static void __init
sun4v_init_mondo_queues(void)
908 for_each_possible_cpu(cpu
) {
909 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
911 alloc_one_queue(&tb
->cpu_mondo_pa
, tb
->cpu_mondo_qmask
);
912 alloc_one_queue(&tb
->dev_mondo_pa
, tb
->dev_mondo_qmask
);
913 alloc_one_queue(&tb
->resum_mondo_pa
, tb
->resum_qmask
);
914 alloc_one_queue(&tb
->resum_kernel_buf_pa
, tb
->resum_qmask
);
915 alloc_one_queue(&tb
->nonresum_mondo_pa
, tb
->nonresum_qmask
);
916 alloc_one_queue(&tb
->nonresum_kernel_buf_pa
,
921 static void __init
init_send_mondo_info(void)
925 for_each_possible_cpu(cpu
) {
926 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
928 init_cpu_send_mondo_info(tb
);
932 static struct irqaction timer_irq_action
= {
936 /* Only invoked on boot processor. */
937 void __init
init_IRQ(void)
944 size
= sizeof(struct ino_bucket
) * NUM_IVECS
;
945 ivector_table
= kzalloc(size
, GFP_KERNEL
);
946 if (!ivector_table
) {
947 prom_printf("Fatal error, cannot allocate ivector_table\n");
950 __flush_dcache_range((unsigned long) ivector_table
,
951 ((unsigned long) ivector_table
) + size
);
953 ivector_table_pa
= __pa(ivector_table
);
955 if (tlb_type
== hypervisor
)
956 sun4v_init_mondo_queues();
958 init_send_mondo_info();
960 if (tlb_type
== hypervisor
) {
961 /* Load up the boot cpu's entries. */
962 sun4v_register_mondo_queues(hard_smp_processor_id());
965 /* We need to clear any IRQ's pending in the soft interrupt
966 * registers, a spurious one could be left around from the
967 * PROM timer which we just disabled.
969 clear_softint(get_softint());
971 /* Now that ivector table is initialized, it is safe
972 * to receive IRQ vector traps. We will normally take
973 * one or two right now, in case some device PROM used
974 * to boot us wants to speak to us. We just ignore them.
976 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
977 "or %%g1, %0, %%g1\n\t"
978 "wrpr %%g1, 0x0, %%pstate"
983 irq_to_desc(0)->action
= &timer_irq_action
;