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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / sparc / kernel / leon_pci_grpci2.c
blob5f0402aab7fb3677ad08517d189a8722cb015adc
1 /*
2 * leon_pci_grpci2.c: GRPCI2 Host PCI driver
3 *
4 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
5 *
6 */
7
8 #include <linux/of_device.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13 #include <asm/io.h>
14 #include <asm/leon.h>
15 #include <asm/vaddrs.h>
16 #include <asm/sections.h>
17 #include <asm/leon_pci.h>
18
19 #include "irq.h"
20
21 struct grpci2_barcfg {
22 unsigned long pciadr; /* PCI Space Address */
23 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
24 };
25
26 /* Device Node Configuration options:
27 * - barcfgs : Custom Configuration of Host's 6 target BARs
28 * - irq_mask : Limit which PCI interrupts are enabled
29 * - do_reset : Force PCI Reset on startup
30 *
31 * barcfgs
32 * =======
33 *
34 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
35 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
36 *
37 * -1 means not configured (let host driver do default setup).
38 *
39 * [i*2+0] = PCI Address of BAR[i] on target interface
40 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
41 *
42 *
43 * irq_mask
44 * ========
45 *
46 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
47 * all are enabled. Use this when PCI interrupt pins are floating on PCB.
48 * int, len=4.
49 * bit0 = PCI INTA#
50 * bit1 = PCI INTB#
51 * bit2 = PCI INTC#
52 * bit3 = PCI INTD#
53 *
54 *
55 * reset
56 * =====
57 *
58 * Force PCI reset on startup. int, len=4
59 */
60
61 /* Enable Debugging Configuration Space Access */
62 #undef GRPCI2_DEBUG_CFGACCESS
63
64 /*
65 * GRPCI2 APB Register MAP
66 */
67 struct grpci2_regs {
68 unsigned int ctrl; /* 0x00 Control */
69 unsigned int sts_cap; /* 0x04 Status / Capabilities */
70 int res1; /* 0x08 */
71 unsigned int io_map; /* 0x0C I/O Map address */
72 unsigned int dma_ctrl; /* 0x10 DMA */
73 unsigned int dma_bdbase; /* 0x14 DMA */
74 int res2[2]; /* 0x18 */
75 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
76 int res3[2]; /* 0x38 */
77 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
78
79 /* PCI Trace Buffer Registers (OPTIONAL) */
80 unsigned int t_ctrl; /* 0x80 */
81 unsigned int t_cnt; /* 0x84 */
82 unsigned int t_adpat; /* 0x88 */
83 unsigned int t_admask; /* 0x8C */
84 unsigned int t_sigpat; /* 0x90 */
85 unsigned int t_sigmask; /* 0x94 */
86 unsigned int t_adstate; /* 0x98 */
87 unsigned int t_sigstate; /* 0x9C */
88 };
89
90 #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
91 #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
92
93 #define CTRL_BUS_BIT 16
94
95 #define CTRL_RESET (1<<31)
96 #define CTRL_SI (1<<27)
97 #define CTRL_PE (1<<26)
98 #define CTRL_EI (1<<25)
99 #define CTRL_ER (1<<24)
100 #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
101 #define CTRL_HOSTINT 0xf
102
103 #define STS_HOST_BIT 31
104 #define STS_MST_BIT 30
105 #define STS_TAR_BIT 29
106 #define STS_DMA_BIT 28
107 #define STS_DI_BIT 27
108 #define STS_HI_BIT 26
109 #define STS_IRQMODE_BIT 24
110 #define STS_TRACE_BIT 23
111 #define STS_CFGERRVALID_BIT 20
112 #define STS_CFGERR_BIT 19
113 #define STS_INTTYPE_BIT 12
114 #define STS_INTSTS_BIT 8
115 #define STS_FDEPTH_BIT 2
116 #define STS_FNUM_BIT 0
117
118 #define STS_HOST (1<<STS_HOST_BIT)
119 #define STS_MST (1<<STS_MST_BIT)
120 #define STS_TAR (1<<STS_TAR_BIT)
121 #define STS_DMA (1<<STS_DMA_BIT)
122 #define STS_DI (1<<STS_DI_BIT)
123 #define STS_HI (1<<STS_HI_BIT)
124 #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
125 #define STS_TRACE (1<<STS_TRACE_BIT)
126 #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
127 #define STS_CFGERR (1<<STS_CFGERR_BIT)
128 #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
129 #define STS_INTSTS (0xf<<STS_INTSTS_BIT)
130 #define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
131 #define STS_FNUM (0x3<<STS_FNUM_BIT)
132
133 #define STS_ISYSERR (1<<17)
134 #define STS_IDMA (1<<16)
135 #define STS_IDMAERR (1<<15)
136 #define STS_IMSTABRT (1<<14)
137 #define STS_ITGTABRT (1<<13)
138 #define STS_IPARERR (1<<12)
139
140 #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
141
142 struct grpci2_bd_chan {
143 unsigned int ctrl; /* 0x00 DMA Control */
144 unsigned int nchan; /* 0x04 Next DMA Channel Address */
145 unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
146 unsigned int res; /* 0x0C Reserved */
147 };
148
149 #define BD_CHAN_EN 0x80000000
150 #define BD_CHAN_TYPE 0x00300000
151 #define BD_CHAN_BDCNT 0x0000ffff
152 #define BD_CHAN_EN_BIT 31
153 #define BD_CHAN_TYPE_BIT 20
154 #define BD_CHAN_BDCNT_BIT 0
155
156 struct grpci2_bd_data {
157 unsigned int ctrl; /* 0x00 DMA Data Control */
158 unsigned int pci_adr; /* 0x04 PCI Start Address */
159 unsigned int ahb_adr; /* 0x08 AHB Start address */
160 unsigned int next; /* 0x0C Next Data Descriptor in chan */
161 };
162
163 #define BD_DATA_EN 0x80000000
164 #define BD_DATA_IE 0x40000000
165 #define BD_DATA_DR 0x20000000
166 #define BD_DATA_TYPE 0x00300000
167 #define BD_DATA_ER 0x00080000
168 #define BD_DATA_LEN 0x0000ffff
169 #define BD_DATA_EN_BIT 31
170 #define BD_DATA_IE_BIT 30
171 #define BD_DATA_DR_BIT 29
172 #define BD_DATA_TYPE_BIT 20
173 #define BD_DATA_ER_BIT 19
174 #define BD_DATA_LEN_BIT 0
175
176 /* GRPCI2 Capability */
177 struct grpci2_cap_first {
178 unsigned int ctrl;
179 unsigned int pci2ahb_map[6];
180 unsigned int ext2ahb_map;
181 unsigned int io_map;
182 unsigned int pcibar_size[6];
183 };
184 #define CAP9_CTRL_OFS 0
185 #define CAP9_BAR_OFS 0x4
186 #define CAP9_IOMAP_OFS 0x20
187 #define CAP9_BARSIZE_OFS 0x24
188
189 #define TGT 256
190
191 struct grpci2_priv {
192 struct leon_pci_info info; /* must be on top of this structure */
193 struct grpci2_regs *regs;
194 char irq;
195 char irq_mode; /* IRQ Mode from CAPSTS REG */
196 char bt_enabled;
197 char do_reset;
198 char irq_mask;
199 u32 pciid; /* PCI ID of Host */
200 unsigned char irq_map[4];
201
202 /* Virtual IRQ numbers */
203 unsigned int virq_err;
204 unsigned int virq_dma;
205
206 /* AHB PCI Windows */
207 unsigned long pci_area; /* MEMORY */
208 unsigned long pci_area_end;
209 unsigned long pci_io; /* I/O */
210 unsigned long pci_conf; /* CONFIGURATION */
211 unsigned long pci_conf_end;
212 unsigned long pci_io_va;
213
214 struct grpci2_barcfg tgtbars[6];
215 };
216
217 DEFINE_SPINLOCK(grpci2_dev_lock);
218 struct grpci2_priv *grpci2priv;
219
220 int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
221 {
222 struct grpci2_priv *priv = dev->bus->sysdata;
223 int irq_group;
224
225 /* Use default IRQ decoding on PCI BUS0 according slot numbering */
226 irq_group = slot & 0x3;
227 pin = ((pin - 1) + irq_group) & 0x3;
228
229 return priv->irq_map[pin];
230 }
231
232 static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
233 unsigned int devfn, int where, u32 *val)
234 {
235 unsigned int *pci_conf;
236 unsigned long flags;
237 u32 tmp;
238
239 if (where & 0x3)
240 return -EINVAL;
241
242 if (bus == 0) {
243 devfn += (0x8 * 6); /* start at AD16=Device0 */
244 } else if (bus == TGT) {
245 bus = 0;
246 devfn = 0; /* special case: bridge controller itself */
247 }
248
249 /* Select bus */
250 spin_lock_irqsave(&grpci2_dev_lock, flags);
251 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
252 (bus << 16));
253 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
254
255 /* clear old status */
256 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
257
258 pci_conf = (unsigned int *) (priv->pci_conf |
259 (devfn << 8) | (where & 0xfc));
260 tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
261
262 /* Wait until GRPCI2 signals that CFG access is done, it should be
263 * done instantaneously unless a DMA operation is ongoing...
264 */
265 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
266 ;
267
268 if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
269 *val = 0xffffffff;
270 } else {
271 /* Bus always little endian (unaffected by byte-swapping) */
272 *val = flip_dword(tmp);
273 }
274
275 return 0;
276 }
277
278 static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
279 unsigned int devfn, int where, u32 *val)
280 {
281 u32 v;
282 int ret;
283
284 if (where & 0x1)
285 return -EINVAL;
286 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
287 *val = 0xffff & (v >> (8 * (where & 0x3)));
288 return ret;
289 }
290
291 static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
292 unsigned int devfn, int where, u32 *val)
293 {
294 u32 v;
295 int ret;
296
297 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
298 *val = 0xff & (v >> (8 * (where & 3)));
299
300 return ret;
301 }
302
303 static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
304 unsigned int devfn, int where, u32 val)
305 {
306 unsigned int *pci_conf;
307 unsigned long flags;
308
309 if (where & 0x3)
310 return -EINVAL;
311
312 if (bus == 0) {
313 devfn += (0x8 * 6); /* start at AD16=Device0 */
314 } else if (bus == TGT) {
315 bus = 0;
316 devfn = 0; /* special case: bridge controller itself */
317 }
318
319 /* Select bus */
320 spin_lock_irqsave(&grpci2_dev_lock, flags);
321 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
322 (bus << 16));
323 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
324
325 /* clear old status */
326 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
327
328 pci_conf = (unsigned int *) (priv->pci_conf |
329 (devfn << 8) | (where & 0xfc));
330 LEON3_BYPASS_STORE_PA(pci_conf, flip_dword(val));
331
332 /* Wait until GRPCI2 signals that CFG access is done, it should be
333 * done instantaneously unless a DMA operation is ongoing...
334 */
335 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
336 ;
337
338 return 0;
339 }
340
341 static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
342 unsigned int devfn, int where, u32 val)
343 {
344 int ret;
345 u32 v;
346
347 if (where & 0x1)
348 return -EINVAL;
349 ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
350 if (ret)
351 return ret;
352 v = (v & ~(0xffff << (8 * (where & 0x3)))) |
353 ((0xffff & val) << (8 * (where & 0x3)));
354 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
355 }
356
357 static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
358 unsigned int devfn, int where, u32 val)
359 {
360 int ret;
361 u32 v;
362
363 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
364 if (ret != 0)
365 return ret;
366 v = (v & ~(0xff << (8 * (where & 0x3)))) |
367 ((0xff & val) << (8 * (where & 0x3)));
368 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
369 }
370
371 /* Read from Configuration Space. When entering here the PCI layer has taken
372 * the pci_lock spinlock and IRQ is off.
373 */
374 static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
375 int where, int size, u32 *val)
376 {
377 struct grpci2_priv *priv = grpci2priv;
378 unsigned int busno = bus->number;
379 int ret;
380
381 if (PCI_SLOT(devfn) > 15 || busno > 255) {
382 *val = ~0;
383 return 0;
384 }
385
386 switch (size) {
387 case 1:
388 ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
389 break;
390 case 2:
391 ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
392 break;
393 case 4:
394 ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
395 break;
396 default:
397 ret = -EINVAL;
398 break;
399 }
400
401 #ifdef GRPCI2_DEBUG_CFGACCESS
402 printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
403 "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
404 *val, size);
405 #endif
406
407 return ret;
408 }
409
410 /* Write to Configuration Space. When entering here the PCI layer has taken
411 * the pci_lock spinlock and IRQ is off.
412 */
413 static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
414 int where, int size, u32 val)
415 {
416 struct grpci2_priv *priv = grpci2priv;
417 unsigned int busno = bus->number;
418
419 if (PCI_SLOT(devfn) > 15 || busno > 255)
420 return 0;
421
422 #ifdef GRPCI2_DEBUG_CFGACCESS
423 printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
424 "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
425 where, size, val);
426 #endif
427
428 switch (size) {
429 default:
430 return -EINVAL;
431 case 1:
432 return grpci2_cfg_w8(priv, busno, devfn, where, val);
433 case 2:
434 return grpci2_cfg_w16(priv, busno, devfn, where, val);
435 case 4:
436 return grpci2_cfg_w32(priv, busno, devfn, where, val);
437 }
438 }
439
440 static struct pci_ops grpci2_ops = {
441 .read = grpci2_read_config,
442 .write = grpci2_write_config,
443 };
444
445 /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
446 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
447 * this is not needed and the standard IRQ controller can be used.
448 */
449
450 static void grpci2_mask_irq(struct irq_data *data)
451 {
452 unsigned long flags;
453 unsigned int irqidx;
454 struct grpci2_priv *priv = grpci2priv;
455
456 irqidx = (unsigned int)data->chip_data - 1;
457 if (irqidx > 3) /* only mask PCI interrupts here */
458 return;
459
460 spin_lock_irqsave(&grpci2_dev_lock, flags);
461 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
462 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
463 }
464
465 static void grpci2_unmask_irq(struct irq_data *data)
466 {
467 unsigned long flags;
468 unsigned int irqidx;
469 struct grpci2_priv *priv = grpci2priv;
470
471 irqidx = (unsigned int)data->chip_data - 1;
472 if (irqidx > 3) /* only unmask PCI interrupts here */
473 return;
474
475 spin_lock_irqsave(&grpci2_dev_lock, flags);
476 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
477 spin_unlock_irqrestore(&grpci2_dev_lock, flags);
478 }
479
480 static unsigned int grpci2_startup_irq(struct irq_data *data)
481 {
482 grpci2_unmask_irq(data);
483 return 0;
484 }
485
486 static void grpci2_shutdown_irq(struct irq_data *data)
487 {
488 grpci2_mask_irq(data);
489 }
490
491 static struct irq_chip grpci2_irq = {
492 .name = "grpci2",
493 .irq_startup = grpci2_startup_irq,
494 .irq_shutdown = grpci2_shutdown_irq,
495 .irq_mask = grpci2_mask_irq,
496 .irq_unmask = grpci2_unmask_irq,
497 };
498
499 /* Handle one or multiple IRQs from the PCI core */
500 static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
501 {
502 struct grpci2_priv *priv = grpci2priv;
503 int i, ack = 0;
504 unsigned int ctrl, sts_cap, pci_ints;
505
506 ctrl = REGLOAD(priv->regs->ctrl);
507 sts_cap = REGLOAD(priv->regs->sts_cap);
508
509 /* Error Interrupt? */
510 if (sts_cap & STS_ERR_IRQ) {
511 generic_handle_irq(priv->virq_err);
512 ack = 1;
513 }
514
515 /* PCI Interrupt? */
516 pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
517 if (pci_ints) {
518 /* Call respective PCI Interrupt handler */
519 for (i = 0; i < 4; i++) {
520 if (pci_ints & (1 << i))
521 generic_handle_irq(priv->irq_map[i]);
522 }
523 ack = 1;
524 }
525
526 /*
527 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
528 * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
529 * goes directly to DMA ISR.
530 */
531 if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
532 generic_handle_irq(priv->virq_dma);
533 ack = 1;
534 }
535
536 /*
537 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
538 * Controller, this must be done after IRQ sources have been handled to
539 * avoid double IRQ generation
540 */
541 if (ack)
542 desc->irq_data.chip->irq_eoi(&desc->irq_data);
543 }
544
545 /* Create a virtual IRQ */
546 static unsigned int grpci2_build_device_irq(unsigned int irq)
547 {
548 unsigned int virq = 0, pil;
549
550 pil = 1 << 8;
551 virq = irq_alloc(irq, pil);
552 if (virq == 0)
553 goto out;
554
555 irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
556 "pcilvl");
557 irq_set_chip_data(virq, (void *)irq);
558
559 out:
560 return virq;
561 }
562
563 void grpci2_hw_init(struct grpci2_priv *priv)
564 {
565 u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
566 struct grpci2_regs *regs = priv->regs;
567 int i;
568 struct grpci2_barcfg *barcfg = priv->tgtbars;
569
570 /* Reset any earlier setup */
571 if (priv->do_reset) {
572 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
573 REGSTORE(regs->ctrl, CTRL_RESET);
574 ssleep(1); /* Wait for boards to settle */
575 }
576 REGSTORE(regs->ctrl, 0);
577 REGSTORE(regs->sts_cap, ~0); /* Clear Status */
578 REGSTORE(regs->dma_ctrl, 0);
579 REGSTORE(regs->dma_bdbase, 0);
580
581 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
582 REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
583
584 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
585 * Each AHB master has it's own mapping registers. Max 16 AHB masters.
586 */
587 for (i = 0; i < 16; i++)
588 REGSTORE(regs->ahbmst_map[i], priv->pci_area);
589
590 /* Get the GRPCI2 Host PCI ID */
591 grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
592
593 /* Get address to first (always defined) capability structure */
594 grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
595
596 /* Enable/Disable Byte twisting */
597 grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
598 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
599 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
600
601 /* Setup the Host's PCI Target BARs for other peripherals to access,
602 * and do DMA to the host's memory. The target BARs can be sized and
603 * enabled individually.
604 *
605 * User may set custom target BARs, but default is:
606 * The first BARs is used to map kernel low (DMA is part of normal
607 * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
608 * PCI bus, the other BARs are disabled. We assume that the first BAR
609 * is always available.
610 */
611 for (i = 0; i < 6; i++) {
612 if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
613 /* Target BARs must have the proper alignment */
614 ahbadr = barcfg[i].ahbadr;
615 pciadr = barcfg[i].pciadr;
616 bar_sz = ((pciadr - 1) & ~pciadr) + 1;
617 } else {
618 if (i == 0) {
619 /* Map main memory */
620 bar_sz = 0xf0000008; /* 256MB prefetchable */
621 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
622 (unsigned long) &_end));
623 pciadr = ahbadr;
624 } else {
625 bar_sz = 0;
626 ahbadr = 0;
627 pciadr = 0;
628 }
629 }
630 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
631 bar_sz);
632 grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
633 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
634 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
635 i, pciadr, ahbadr);
636 }
637
638 /* set as bus master and enable pci memory responses */
639 grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
640 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
641 grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
642
643 /* Enable Error respone (CPU-TRAP) on illegal memory access. */
644 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
645 }
646
647 static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
648 {
649 printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
650 return IRQ_NONE;
651 }
652
653 /* Handle GRPCI2 Error Interrupt */
654 static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
655 {
656 struct grpci2_priv *priv = arg;
657 struct grpci2_regs *regs = priv->regs;
658 unsigned int status;
659
660 status = REGLOAD(regs->sts_cap);
661 if ((status & STS_ERR_IRQ) == 0)
662 return IRQ_NONE;
663
664 if (status & STS_IPARERR)
665 printk(KERN_ERR "GRPCI2: Parity Error\n");
666
667 if (status & STS_ITGTABRT)
668 printk(KERN_ERR "GRPCI2: Target Abort\n");
669
670 if (status & STS_IMSTABRT)
671 printk(KERN_ERR "GRPCI2: Master Abort\n");
672
673 if (status & STS_ISYSERR)
674 printk(KERN_ERR "GRPCI2: System Error\n");
675
676 /* Clear handled INT TYPE IRQs */
677 REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
678
679 return IRQ_HANDLED;
680 }
681
682 static int grpci2_of_probe(struct platform_device *ofdev)
683 {
684 struct grpci2_regs *regs;
685 struct grpci2_priv *priv;
686 int err, i, len;
687 const int *tmp;
688 unsigned int capability;
689
690 if (grpci2priv) {
691 printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
692 return -ENODEV;
693 }
694
695 if (ofdev->num_resources < 3) {
696 printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
697 return -EIO;
698 }
699
700 /* Find Device Address */
701 regs = of_ioremap(&ofdev->resource[0], 0,
702 resource_size(&ofdev->resource[0]),
703 "grlib-grpci2 regs");
704 if (regs == NULL) {
705 printk(KERN_ERR "GRPCI2: ioremap failed\n");
706 return -EIO;
707 }
708
709 /*
710 * Check that we're in Host Slot and that we can act as a Host Bridge
711 * and not only as target.
712 */
713 capability = REGLOAD(regs->sts_cap);
714 if ((capability & STS_HOST) || !(capability & STS_MST)) {
715 printk(KERN_INFO "GRPCI2: not in host system slot\n");
716 err = -EIO;
717 goto err1;
718 }
719
720 priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
721 if (grpci2priv == NULL) {
722 err = -ENOMEM;
723 goto err1;
724 }
725 memset(grpci2priv, 0, sizeof(*grpci2priv));
726 priv->regs = regs;
727 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
728 priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
729
730 printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
731
732 /* Byte twisting should be made configurable from kernel command line */
733 priv->bt_enabled = 1;
734
735 /* Let user do custom Target BAR assignment */
736 tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
737 if (tmp && (len == 2*4*6))
738 memcpy(priv->tgtbars, tmp, 2*4*6);
739 else
740 memset(priv->tgtbars, -1, 2*4*6);
741
742 /* Limit IRQ unmasking in irq_mode 2 and 3 */
743 tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
744 if (tmp && (len == 4))
745 priv->do_reset = *tmp;
746 else
747 priv->irq_mask = 0xf;
748
749 /* Optional PCI reset. Force PCI reset on startup */
750 tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
751 if (tmp && (len == 4))
752 priv->do_reset = *tmp;
753 else
754 priv->do_reset = 0;
755
756 /* Find PCI Memory, I/O and Configuration Space Windows */
757 priv->pci_area = ofdev->resource[1].start;
758 priv->pci_area_end = ofdev->resource[1].end+1;
759 priv->pci_io = ofdev->resource[2].start;
760 priv->pci_conf = ofdev->resource[2].start + 0x10000;
761 priv->pci_conf_end = priv->pci_conf + 0x10000;
762 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
763 if (!priv->pci_io_va) {
764 err = -EIO;
765 goto err2;
766 }
767
768 printk(KERN_INFO
769 "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
770 " I/O SPACE [0x%08lx - 0x%08lx]\n"
771 " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
772 priv->pci_area, priv->pci_area_end-1,
773 priv->pci_io, priv->pci_conf-1,
774 priv->pci_conf, priv->pci_conf_end-1);
775
776 /*
777 * I/O Space resources in I/O Window mapped into Virtual Adr Space
778 * We never use low 4KB because some devices seem have problems using
779 * address 0.
780 */
781 memset(&priv->info.io_space, 0, sizeof(struct resource));
782 priv->info.io_space.name = "GRPCI2 PCI I/O Space";
783 priv->info.io_space.start = priv->pci_io_va + 0x1000;
784 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
785 priv->info.io_space.flags = IORESOURCE_IO;
786
787 /*
788 * GRPCI2 has no prefetchable memory, map everything as
789 * non-prefetchable memory
790 */
791 memset(&priv->info.mem_space, 0, sizeof(struct resource));
792 priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
793 priv->info.mem_space.start = priv->pci_area;
794 priv->info.mem_space.end = priv->pci_area_end - 1;
795 priv->info.mem_space.flags = IORESOURCE_MEM;
796
797 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
798 goto err3;
799 if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
800 goto err4;
801
802 /* setup maximum supported PCI buses */
803 priv->info.busn.name = "GRPCI2 busn";
804 priv->info.busn.start = 0;
805 priv->info.busn.end = 255;
806
807 grpci2_hw_init(priv);
808
809 /*
810 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
811 * Error IRQ always on PCI INTA.
812 */
813 if (priv->irq_mode < 2) {
814 /* All PCI interrupts are shared using the same system IRQ */
815 leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
816 "pcilvl", 0);
817
818 priv->irq_map[0] = grpci2_build_device_irq(1);
819 priv->irq_map[1] = grpci2_build_device_irq(2);
820 priv->irq_map[2] = grpci2_build_device_irq(3);
821 priv->irq_map[3] = grpci2_build_device_irq(4);
822
823 priv->virq_err = grpci2_build_device_irq(5);
824 if (priv->irq_mode & 1)
825 priv->virq_dma = ofdev->archdata.irqs[1];
826 else
827 priv->virq_dma = grpci2_build_device_irq(6);
828
829 /* Enable IRQs on LEON IRQ controller */
830 err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
831 "GRPCI2_JUMP", priv);
832 if (err)
833 printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
834 } else {
835 /* All PCI interrupts have an unique IRQ interrupt */
836 for (i = 0; i < 4; i++) {
837 /* Make LEON IRQ layer handle level IRQ by acking */
838 leon_update_virq_handling(ofdev->archdata.irqs[i],
839 handle_fasteoi_irq, "pcilvl",
840 1);
841 priv->irq_map[i] = ofdev->archdata.irqs[i];
842 }
843 priv->virq_err = priv->irq_map[0];
844 if (priv->irq_mode & 1)
845 priv->virq_dma = ofdev->archdata.irqs[4];
846 else
847 priv->virq_dma = priv->irq_map[0];
848
849 /* Unmask all PCI interrupts, request_irq will not do that */
850 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
851 }
852
853 /* Setup IRQ handler for non-configuration space access errors */
854 err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
855 "GRPCI2_ERR", priv);
856 if (err) {
857 printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
858 goto err5;
859 }
860
861 /*
862 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
863 * is called by the PCI Device drivers
864 */
865 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
866
867 /* Init common layer and scan buses */
868 priv->info.ops = &grpci2_ops;
869 priv->info.map_irq = grpci2_map_irq;
870 leon_pci_init(ofdev, &priv->info);
871
872 return 0;
873
874 err5:
875 release_resource(&priv->info.io_space);
876 err4:
877 release_resource(&priv->info.mem_space);
878 err3:
879 err = -ENOMEM;
880 iounmap((void *)priv->pci_io_va);
881 err2:
882 kfree(priv);
883 err1:
884 of_iounmap(&ofdev->resource[0], regs,
885 resource_size(&ofdev->resource[0]));
886 return err;
887 }
888
889 static struct of_device_id grpci2_of_match[] = {
890 {
891 .name = "GAISLER_GRPCI2",
892 },
893 {
894 .name = "01_07c",
895 },
896 {},
897 };
898
899 static struct platform_driver grpci2_of_driver = {
900 .driver = {
901 .name = "grpci2",
902 .owner = THIS_MODULE,
903 .of_match_table = grpci2_of_match,
904 },
905 .probe = grpci2_of_probe,
906 };
907
908 static int __init grpci2_init(void)
909 {
910 return platform_driver_register(&grpci2_of_driver);
911 }
912
913 subsys_initcall(grpci2_init);
Linux with added FPC-III support