4 #include <uapi/asm/mce.h>
7 * Machine Check support for x86
10 /* MCG_CAP register defines */
11 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16 #define MCG_EXT_CNT_SHIFT 16
17 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
20 /* MCG_STATUS register defines */
21 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
22 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
23 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
25 /* MCi_STATUS register defines */
26 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
27 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
28 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
29 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
30 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
31 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
32 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
33 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
34 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
37 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
38 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
39 * errors to indicate that errors are being filtered by hardware.
40 * We should mask out bit 12 when looking for specific signatures
41 * of uncorrected errors - so the F bit is deliberately skipped
44 #define MCACOD 0xefff /* MCA Error Code */
46 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
47 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
48 #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
49 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
50 #define MCACOD_DATA 0x0134 /* Data Load */
51 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */
53 /* MCi_MISC register defines */
54 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
55 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
56 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
57 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
58 #define MCI_MISC_ADDR_PHYS 2 /* physical address */
59 #define MCI_MISC_ADDR_MEM 3 /* memory address */
60 #define MCI_MISC_ADDR_GENERIC 7 /* generic */
62 /* CTL2 register defines */
63 #define MCI_CTL2_CMCI_EN (1ULL << 30)
64 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
66 #define MCJ_CTX_MASK 3
67 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
68 #define MCJ_CTX_RANDOM 0 /* inject context: random */
69 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
70 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
71 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
72 #define MCJ_EXCEPTION 0x8 /* raise as exception */
73 #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
75 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
77 /* Software defined banks */
78 #define MCE_EXTENDED_BANK 128
79 #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
80 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
82 #define MCE_LOG_LEN 32
83 #define MCE_LOG_SIGNATURE "MACHINECHECK"
86 * This structure contains all data related to the MCE log. Also
87 * carries a signature to make it easier to find from external
88 * debugging tools. Each entry is only valid when its finished flag
92 char signature
[12]; /* "MACHINECHECK" */
93 unsigned len
; /* = MCE_LOG_LEN */
96 unsigned recordlen
; /* length of struct mce */
97 struct mce entry
[MCE_LOG_LEN
];
106 bool bios_cmci_threshold
;
115 extern struct mca_config mca_cfg
;
116 extern void mce_register_decode_chain(struct notifier_block
*nb
);
117 extern void mce_unregister_decode_chain(struct notifier_block
*nb
);
119 #include <linux/percpu.h>
120 #include <linux/init.h>
121 #include <linux/atomic.h>
123 extern int mce_p5_enabled
;
125 #ifdef CONFIG_X86_MCE
126 int mcheck_init(void);
127 void mcheck_cpu_init(struct cpuinfo_x86
*c
);
129 static inline int mcheck_init(void) { return 0; }
130 static inline void mcheck_cpu_init(struct cpuinfo_x86
*c
) {}
133 #ifdef CONFIG_X86_ANCIENT_MCE
134 void intel_p5_mcheck_init(struct cpuinfo_x86
*c
);
135 void winchip_mcheck_init(struct cpuinfo_x86
*c
);
136 static inline void enable_p5_mce(void) { mce_p5_enabled
= 1; }
138 static inline void intel_p5_mcheck_init(struct cpuinfo_x86
*c
) {}
139 static inline void winchip_mcheck_init(struct cpuinfo_x86
*c
) {}
140 static inline void enable_p5_mce(void) {}
143 void mce_setup(struct mce
*m
);
144 void mce_log(struct mce
*m
);
145 DECLARE_PER_CPU(struct device
*, mce_device
);
148 * Maximum banks number.
149 * This is the limit of the current register layout on
152 #define MAX_NR_BANKS 32
154 #ifdef CONFIG_X86_MCE_INTEL
155 void mce_intel_feature_init(struct cpuinfo_x86
*c
);
156 void cmci_clear(void);
157 void cmci_reenable(void);
158 void cmci_rediscover(void);
159 void cmci_recheck(void);
161 static inline void mce_intel_feature_init(struct cpuinfo_x86
*c
) { }
162 static inline void cmci_clear(void) {}
163 static inline void cmci_reenable(void) {}
164 static inline void cmci_rediscover(void) {}
165 static inline void cmci_recheck(void) {}
168 #ifdef CONFIG_X86_MCE_AMD
169 void mce_amd_feature_init(struct cpuinfo_x86
*c
);
171 static inline void mce_amd_feature_init(struct cpuinfo_x86
*c
) { }
174 int mce_available(struct cpuinfo_x86
*c
);
176 DECLARE_PER_CPU(unsigned, mce_exception_count
);
177 DECLARE_PER_CPU(unsigned, mce_poll_count
);
179 extern atomic_t mce_entry
;
181 typedef DECLARE_BITMAP(mce_banks_t
, MAX_NR_BANKS
);
182 DECLARE_PER_CPU(mce_banks_t
, mce_poll_banks
);
185 MCP_TIMESTAMP
= (1 << 0), /* log time stamp */
186 MCP_UC
= (1 << 1), /* log uncorrected errors */
187 MCP_DONTLOG
= (1 << 2), /* only clear, don't log */
189 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
);
191 int mce_notify_irq(void);
192 void mce_notify_process(void);
194 DECLARE_PER_CPU(struct mce
, injectm
);
196 extern void register_mce_write_callback(ssize_t (*)(struct file
*filp
,
197 const char __user
*ubuf
,
198 size_t usize
, loff_t
*off
));
200 /* Disable CMCI/polling for MCA bank claimed by firmware */
201 extern void mce_disable_bank(int bank
);
207 /* Call the installed machine check handler for this CPU setup. */
208 extern void (*machine_check_vector
)(struct pt_regs
*, long error_code
);
209 void do_machine_check(struct pt_regs
*, long);
215 extern void (*mce_threshold_vector
)(void);
216 extern void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
222 void intel_init_thermal(struct cpuinfo_x86
*c
);
224 void mce_log_therm_throt_event(__u64 status
);
226 /* Interrupt Handler for core thermal thresholds */
227 extern int (*platform_thermal_notify
)(__u64 msr_val
);
229 /* Interrupt Handler for package thermal thresholds */
230 extern int (*platform_thermal_package_notify
)(__u64 msr_val
);
232 /* Callback support of rate control, return true, if
233 * callback has rate control */
234 extern bool (*platform_thermal_package_rate_control
)(void);
236 #ifdef CONFIG_X86_THERMAL_VECTOR
237 extern void mcheck_intel_therm_init(void);
239 static inline void mcheck_intel_therm_init(void) { }
243 * Used by APEI to report memory error via /dev/mcelog
246 struct cper_sec_mem_err
;
247 extern void apei_mce_report_mem_error(int corrected
,
248 struct cper_sec_mem_err
*mem_err
);
250 #endif /* _ASM_X86_MCE_H */